include/asm/pm-cps.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2014 Imagination Technologies
0004  * Author: Paul Burton <paul.burton@mips.com>
0005  */
0006
0007 #ifndef __MIPS_ASM_PM_CPS_H__
0008 #define __MIPS_ASM_PM_CPS_H__
0009
0010 /*
0011  * The CM & CPC can only handle coherence & power control on a per-core basis,
0012  * thus in an MT system the VP(E)s within each core are coupled and can only
0013  * enter or exit states requiring CM or CPC assistance in unison.
0014  */
0015 #if defined(CONFIG_CPU_MIPSR6)
0016 # define coupled_coherence cpu_has_vp
0017 #elif defined(CONFIG_MIPS_MT)
0018 # define coupled_coherence cpu_has_mipsmt
0019 #else
0020 # define coupled_coherence 0
0021 #endif
0022
0023 /* Enumeration of possible PM states */
0024 enum cps_pm_state {
0025     CPS_PM_NC_WAIT,     /* MIPS wait instruction, non-coherent */
0026     CPS_PM_CLOCK_GATED, /* Core clock gated */
0027     CPS_PM_POWER_GATED, /* Core power gated */
0028     CPS_PM_STATE_COUNT,
0029 };
0030
0031 /**
0032  * cps_pm_support_state - determine whether the system supports a PM state
0033  * @state: the state to test for support
0034  *
0035  * Returns true if the system supports the given state, otherwise false.
0036  */
0037 extern bool cps_pm_support_state(enum cps_pm_state state);
0038
0039 /**
0040  * cps_pm_enter_state - enter a PM state
0041  * @state: the state to enter
0042  *
0043  * Enter the given PM state. If coupled_coherence is non-zero then it is
0044  * expected that this function be called at approximately the same time on
0045  * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
0046  */
0047 extern int cps_pm_enter_state(enum cps_pm_state state);
0048
0049 #endif /* __MIPS_ASM_PM_CPS_H__ */