include/asm/pgtable-bits.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1994 - 2002 by Ralf Baechle
0007  * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
0008  * Copyright (C) 2002  Maciej W. Rozycki
0009  */
0010 #ifndef _ASM_PGTABLE_BITS_H
0011 #define _ASM_PGTABLE_BITS_H
0012
0013
0014 /*
0015  * Note that we shift the lower 32bits of each EntryLo[01] entry
0016  * 6 bits to the left. That way we can convert the PFN into the
0017  * physical address by a single 'and' operation and gain 6 additional
0018  * bits for storing information which isn't present in a normal
0019  * MIPS page table.
0020  *
0021  * Similar to the Alpha port, we need to keep track of the ref
0022  * and mod bits in software.  We have a software "yeah you can read
0023  * from this page" bit, and a hardware one which actually lets the
0024  * process read from the page.  On the same token we have a software
0025  * writable bit and the real hardware one which actually lets the
0026  * process write to the page, this keeps a mod bit via the hardware
0027  * dirty bit.
0028  *
0029  * Certain revisions of the R4000 and R5000 have a bug where if a
0030  * certain sequence occurs in the last 3 instructions of an executable
0031  * page, and the following page is not mapped, the cpu can do
0032  * unpredictable things.  The code (when it is written) to deal with
0033  * this problem will be in the update_mmu_cache() code for the r4k.
0034  */
0035 #if defined(CONFIG_XPA)
0036
0037 /*
0038  * Page table bit offsets used for 64 bit physical addressing on
0039  * MIPS32r5 with XPA.
0040  */
0041 enum pgtable_bits {
0042     /* Used by TLB hardware (placed in EntryLo*) */
0043     _PAGE_NO_EXEC_SHIFT,
0044     _PAGE_NO_READ_SHIFT,
0045     _PAGE_GLOBAL_SHIFT,
0046     _PAGE_VALID_SHIFT,
0047     _PAGE_DIRTY_SHIFT,
0048     _CACHE_SHIFT,
0049
0050     /* Used only by software (masked out before writing EntryLo*) */
0051     _PAGE_PRESENT_SHIFT = 24,
0052     _PAGE_WRITE_SHIFT,
0053     _PAGE_ACCESSED_SHIFT,
0054     _PAGE_MODIFIED_SHIFT,
0055 #if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
0056     _PAGE_SPECIAL_SHIFT,
0057 #endif
0058 #if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
0059     _PAGE_SOFT_DIRTY_SHIFT,
0060 #endif
0061 };
0062
0063 /*
0064  * Bits for extended EntryLo0/EntryLo1 registers
0065  */
0066 #define _PFNX_MASK      0xffffff
0067
0068 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
0069
0070 /*
0071  * Page table bit offsets used for 36 bit physical addressing on MIPS32,
0072  * for example with Alchemy or Netlogic XLP/XLR.
0073  */
0074 enum pgtable_bits {
0075     /* Used by TLB hardware (placed in EntryLo*) */
0076     _PAGE_GLOBAL_SHIFT,
0077     _PAGE_VALID_SHIFT,
0078     _PAGE_DIRTY_SHIFT,
0079     _CACHE_SHIFT,
0080
0081     /* Used only by software (masked out before writing EntryLo*) */
0082     _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
0083     _PAGE_NO_READ_SHIFT,
0084     _PAGE_WRITE_SHIFT,
0085     _PAGE_ACCESSED_SHIFT,
0086     _PAGE_MODIFIED_SHIFT,
0087 #if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
0088     _PAGE_SPECIAL_SHIFT,
0089 #endif
0090 #if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
0091     _PAGE_SOFT_DIRTY_SHIFT,
0092 #endif
0093 };
0094
0095 #elif defined(CONFIG_CPU_R3K_TLB)
0096
0097 /* Page table bits used for r3k systems */
0098 enum pgtable_bits {
0099     /* Used only by software (writes to EntryLo ignored) */
0100     _PAGE_PRESENT_SHIFT,
0101     _PAGE_NO_READ_SHIFT,
0102     _PAGE_WRITE_SHIFT,
0103     _PAGE_ACCESSED_SHIFT,
0104     _PAGE_MODIFIED_SHIFT,
0105 #if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
0106     _PAGE_SPECIAL_SHIFT,
0107 #endif
0108 #if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
0109     _PAGE_SOFT_DIRTY_SHIFT,
0110 #endif
0111
0112     /* Used by TLB hardware (placed in EntryLo) */
0113     _PAGE_GLOBAL_SHIFT = 8,
0114     _PAGE_VALID_SHIFT,
0115     _PAGE_DIRTY_SHIFT,
0116     _CACHE_UNCACHED_SHIFT,
0117 };
0118
0119 #else
0120
0121 /* Page table bits used for r4k systems */
0122 enum pgtable_bits {
0123     /* Used only by software (masked out before writing EntryLo*) */
0124     _PAGE_PRESENT_SHIFT,
0125 #if !defined(CONFIG_CPU_HAS_RIXI)
0126     _PAGE_NO_READ_SHIFT,
0127 #endif
0128     _PAGE_WRITE_SHIFT,
0129     _PAGE_ACCESSED_SHIFT,
0130     _PAGE_MODIFIED_SHIFT,
0131 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
0132     _PAGE_HUGE_SHIFT,
0133 #endif
0134 #if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
0135     _PAGE_SPECIAL_SHIFT,
0136 #endif
0137 #if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
0138     _PAGE_SOFT_DIRTY_SHIFT,
0139 #endif
0140     /* Used by TLB hardware (placed in EntryLo*) */
0141 #if defined(CONFIG_CPU_HAS_RIXI)
0142     _PAGE_NO_EXEC_SHIFT,
0143     _PAGE_NO_READ_SHIFT,
0144 #endif
0145     _PAGE_GLOBAL_SHIFT,
0146     _PAGE_VALID_SHIFT,
0147     _PAGE_DIRTY_SHIFT,
0148     _CACHE_SHIFT,
0149 };
0150
0151 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
0152
0153 /* Used only by software */
0154 #define _PAGE_PRESENT       (1 << _PAGE_PRESENT_SHIFT)
0155 #define _PAGE_WRITE     (1 << _PAGE_WRITE_SHIFT)
0156 #define _PAGE_ACCESSED      (1 << _PAGE_ACCESSED_SHIFT)
0157 #define _PAGE_MODIFIED      (1 << _PAGE_MODIFIED_SHIFT)
0158 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
0159 # define _PAGE_HUGE     (1 << _PAGE_HUGE_SHIFT)
0160 #endif
0161 #if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
0162 # define _PAGE_SPECIAL      (1 << _PAGE_SPECIAL_SHIFT)
0163 #else
0164 # define _PAGE_SPECIAL      0
0165 #endif
0166 #if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
0167 # define _PAGE_SOFT_DIRTY   (1 << _PAGE_SOFT_DIRTY_SHIFT)
0168 #else
0169 # define _PAGE_SOFT_DIRTY   0
0170 #endif
0171
0172 /* Used by TLB hardware (placed in EntryLo*) */
0173 #if defined(CONFIG_XPA)
0174 # define _PAGE_NO_EXEC      (1 << _PAGE_NO_EXEC_SHIFT)
0175 #elif defined(CONFIG_CPU_HAS_RIXI)
0176 # define _PAGE_NO_EXEC      (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
0177 #endif
0178 #define _PAGE_NO_READ       (1 << _PAGE_NO_READ_SHIFT)
0179 #define _PAGE_GLOBAL        (1 << _PAGE_GLOBAL_SHIFT)
0180 #define _PAGE_VALID     (1 << _PAGE_VALID_SHIFT)
0181 #define _PAGE_DIRTY     (1 << _PAGE_DIRTY_SHIFT)
0182 #if defined(CONFIG_CPU_R3K_TLB)
0183 # define _CACHE_UNCACHED    (1 << _CACHE_UNCACHED_SHIFT)
0184 # define _CACHE_MASK        _CACHE_UNCACHED
0185 # define _PFN_SHIFT     PAGE_SHIFT
0186 #else
0187 # define _CACHE_MASK        (7 << _CACHE_SHIFT)
0188 # define _PFN_SHIFT     (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
0189 #endif
0190
0191 #ifndef _PAGE_NO_EXEC
0192 #define _PAGE_NO_EXEC       0
0193 #endif
0194
0195 #define _PAGE_SILENT_READ   _PAGE_VALID
0196 #define _PAGE_SILENT_WRITE  _PAGE_DIRTY
0197
0198 #define _PFN_MASK       (~((1 << (_PFN_SHIFT)) - 1))
0199
0200 /*
0201  * The final layouts of the PTE bits are:
0202  *
0203  *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
0204  *   32-bit, R1 or earler:      CCC D V G M A W R P
0205  *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
0206  *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
0207  */
0208
0209
0210 /*
0211  * pte_to_entrylo converts a page table entry (PTE) into a Mips
0212  * entrylo0/1 value.
0213  */
0214 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
0215 {
0216 #ifdef CONFIG_CPU_HAS_RIXI
0217     if (cpu_has_rixi) {
0218         int sa;
0219 #ifdef CONFIG_32BIT
0220         sa = 31 - _PAGE_NO_READ_SHIFT;
0221 #else
0222         sa = 63 - _PAGE_NO_READ_SHIFT;
0223 #endif
0224         /*
0225          * C has no way to express that this is a DSRL
0226          * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
0227          * in the fast path this is done in assembly
0228          */
0229         return (pte_val >> _PAGE_GLOBAL_SHIFT) |
0230             ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
0231     }
0232 #endif
0233
0234     return pte_val >> _PAGE_GLOBAL_SHIFT;
0235 }
0236
0237 /*
0238  * Cache attributes
0239  */
0240 #if defined(CONFIG_CPU_R3K_TLB)
0241
0242 #define _CACHE_CACHABLE_NONCOHERENT 0
0243 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
0244
0245 #elif defined(CONFIG_CPU_SB1)
0246
0247 /* No penalty for being coherent on the SB1, so just
0248    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
0249
0250 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
0251
0252 #endif
0253
0254 #ifndef _CACHE_CACHABLE_NO_WA
0255 #define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)
0256 #endif
0257 #ifndef _CACHE_CACHABLE_WA
0258 #define _CACHE_CACHABLE_WA      (1<<_CACHE_SHIFT)
0259 #endif
0260 #ifndef _CACHE_UNCACHED
0261 #define _CACHE_UNCACHED         (2<<_CACHE_SHIFT)
0262 #endif
0263 #ifndef _CACHE_CACHABLE_NONCOHERENT
0264 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
0265 #endif
0266 #ifndef _CACHE_CACHABLE_CE
0267 #define _CACHE_CACHABLE_CE      (4<<_CACHE_SHIFT)
0268 #endif
0269 #ifndef _CACHE_CACHABLE_COW
0270 #define _CACHE_CACHABLE_COW     (5<<_CACHE_SHIFT)
0271 #endif
0272 #ifndef _CACHE_CACHABLE_CUW
0273 #define _CACHE_CACHABLE_CUW     (6<<_CACHE_SHIFT)
0274 #endif
0275 #ifndef _CACHE_UNCACHED_ACCELERATED
0276 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
0277 #endif
0278
0279 #define __READABLE  (_PAGE_SILENT_READ | _PAGE_ACCESSED)
0280 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
0281
0282 #define _PAGE_CHG_MASK  (_PAGE_ACCESSED | _PAGE_MODIFIED |  \
0283              _PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK)
0284
0285 #endif /* _ASM_PGTABLE_BITS_H */