include/asm/pgtable-32.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
0007  * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
0008  */
0009 #ifndef _ASM_PGTABLE_32_H
0010 #define _ASM_PGTABLE_32_H
0011
0012 #include <asm/addrspace.h>
0013 #include <asm/page.h>
0014
0015 #include <linux/linkage.h>
0016 #include <asm/cachectl.h>
0017 #include <asm/fixmap.h>
0018
0019 #include <asm-generic/pgtable-nopmd.h>
0020
0021 #ifdef CONFIG_HIGHMEM
0022 #include <asm/highmem.h>
0023 #endif
0024
0025 /*
0026  * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
0027  *
0028  *  We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
0029  * our 2-level table layout would normally have a PGD entry cover a contiguous
0030  * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
0031  * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
0032  * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
0033  * support, not one of the standard supported sizes (1MB,4MB,16MB,...).
0034  *  To correct for this, when huge pages are enabled, we halve the number of
0035  * pointers a PTE page holds, making its last half go to waste. Correspondingly,
0036  * we double the number of PGD pages. Overall, page table memory overhead
0037  * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
0038  *
0039  * NOTE: We don't yet support huge pages if extended-addressing is enabled
0040  *       (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
0041  */
0042
0043 extern int temp_tlb_entry;
0044
0045 /*
0046  * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
0047  *  starting at the top and working down. This is for populating the
0048  *  TLB before trap_init() puts the TLB miss handler in place. It
0049  *  should be used only for entries matching the actual page tables,
0050  *  to prevent inconsistencies.
0051  */
0052 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
0053                    unsigned long entryhi, unsigned long pagemask);
0054
0055 /*
0056  * Basically we have the same two-level (which is the logical three level
0057  * Linux page table layout folded) page tables as the i386.  Some day
0058  * when we have proper page coloring support we can have a 1% quicker
0059  * tlb refill handling mechanism, but for now it is a bit slower but
0060  * works even with the cache aliasing problem the R4k and above have.
0061  */
0062
0063 /* PGDIR_SHIFT determines what a third-level page table entry can map */
0064 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
0065 # define PGDIR_SHIFT    (2 * PAGE_SHIFT - PTE_T_LOG2 - 1)
0066 #else
0067 # define PGDIR_SHIFT    (2 * PAGE_SHIFT - PTE_T_LOG2)
0068 #endif
0069
0070 #define PGDIR_SIZE  (1UL << PGDIR_SHIFT)
0071 #define PGDIR_MASK  (~(PGDIR_SIZE-1))
0072
0073 /*
0074  * Entries per page directory level: we use two-level, so
0075  * we don't really have any PUD/PMD directory physically.
0076  */
0077 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
0078 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
0079 #else
0080 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
0081 #endif
0082
0083 #define PGD_TABLE_ORDER (__PGD_TABLE_ORDER >= 0 ? __PGD_TABLE_ORDER : 0)
0084 #define PUD_TABLE_ORDER aieeee_attempt_to_allocate_pud
0085 #define PMD_TABLE_ORDER aieeee_attempt_to_allocate_pmd
0086
0087 #define PTRS_PER_PGD    (USER_PTRS_PER_PGD * 2)
0088 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
0089 # define PTRS_PER_PTE   (PAGE_SIZE / sizeof(pte_t) / 2)
0090 #else
0091 # define PTRS_PER_PTE   (PAGE_SIZE / sizeof(pte_t))
0092 #endif
0093
0094 #define USER_PTRS_PER_PGD   (0x80000000UL/PGDIR_SIZE)
0095
0096 #define VMALLOC_START     MAP_BASE
0097
0098 #define PKMAP_END   ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
0099 #define PKMAP_BASE  (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
0100
0101 #ifdef CONFIG_HIGHMEM
0102 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
0103 #else
0104 # define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
0105 #endif
0106
0107 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0108 #define pte_ERROR(e) \
0109     printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
0110 #else
0111 #define pte_ERROR(e) \
0112     printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
0113 #endif
0114 #define pgd_ERROR(e) \
0115     printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
0116
0117 extern void load_pgd(unsigned long pg_dir);
0118
0119 extern pte_t invalid_pte_table[PTRS_PER_PTE];
0120
0121 /*
0122  * Empty pgd/pmd entries point to the invalid_pte_table.
0123  */
0124 static inline int pmd_none(pmd_t pmd)
0125 {
0126     return pmd_val(pmd) == (unsigned long) invalid_pte_table;
0127 }
0128
0129 static inline int pmd_bad(pmd_t pmd)
0130 {
0131 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
0132     /* pmd_huge(pmd) but inline */
0133     if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
0134         return 0;
0135 #endif
0136
0137     if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
0138         return 1;
0139
0140     return 0;
0141 }
0142
0143 static inline int pmd_present(pmd_t pmd)
0144 {
0145     return pmd_val(pmd) != (unsigned long) invalid_pte_table;
0146 }
0147
0148 static inline void pmd_clear(pmd_t *pmdp)
0149 {
0150     pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
0151 }
0152
0153 #if defined(CONFIG_XPA)
0154
0155 #define MAX_POSSIBLE_PHYSMEM_BITS 40
0156 #define pte_pfn(x)      (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
0157 static inline pte_t
0158 pfn_pte(unsigned long pfn, pgprot_t prot)
0159 {
0160     pte_t pte;
0161
0162     pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
0163                 (pgprot_val(prot) & ~_PFNX_MASK);
0164     pte.pte_high = (pfn << _PFN_SHIFT) |
0165                 (pgprot_val(prot) & ~_PFN_MASK);
0166     return pte;
0167 }
0168
0169 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
0170
0171 #define MAX_POSSIBLE_PHYSMEM_BITS 36
0172 #define pte_pfn(x)      ((unsigned long)((x).pte_high >> 6))
0173
0174 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
0175 {
0176     pte_t pte;
0177
0178     pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
0179     pte.pte_low = pgprot_val(prot);
0180
0181     return pte;
0182 }
0183
0184 #else
0185
0186 #define MAX_POSSIBLE_PHYSMEM_BITS 32
0187 #define pte_pfn(x)      ((unsigned long)((x).pte >> _PFN_SHIFT))
0188 #define pfn_pte(pfn, prot)  __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
0189 #define pfn_pmd(pfn, prot)  __pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
0190 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
0191
0192 #define pte_page(x)     pfn_to_page(pte_pfn(x))
0193
0194 #if defined(CONFIG_CPU_R3K_TLB)
0195
0196 /* Swap entries must have VALID bit cleared. */
0197 #define __swp_type(x)           (((x).val >> 10) & 0x1f)
0198 #define __swp_offset(x)         ((x).val >> 15)
0199 #define __swp_entry(type,offset)    ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
0200 #define __pte_to_swp_entry(pte)     ((swp_entry_t) { pte_val(pte) })
0201 #define __swp_entry_to_pte(x)       ((pte_t) { (x).val })
0202
0203 #else
0204
0205 #if defined(CONFIG_XPA)
0206
0207 /* Swap entries must have VALID and GLOBAL bits cleared. */
0208 #define __swp_type(x)           (((x).val >> 4) & 0x1f)
0209 #define __swp_offset(x)          ((x).val >> 9)
0210 #define __swp_entry(type,offset)    ((swp_entry_t)  { ((type) << 4) | ((offset) << 9) })
0211 #define __pte_to_swp_entry(pte)     ((swp_entry_t) { (pte).pte_high })
0212 #define __swp_entry_to_pte(x)       ((pte_t) { 0, (x).val })
0213
0214 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
0215
0216 /* Swap entries must have VALID and GLOBAL bits cleared. */
0217 #define __swp_type(x)           (((x).val >> 2) & 0x1f)
0218 #define __swp_offset(x)          ((x).val >> 7)
0219 #define __swp_entry(type, offset)   ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
0220 #define __pte_to_swp_entry(pte)     ((swp_entry_t) { (pte).pte_high })
0221 #define __swp_entry_to_pte(x)       ((pte_t) { 0, (x).val })
0222
0223 #else
0224 /*
0225  * Constraints:
0226  *      _PAGE_PRESENT at bit 0
0227  *      _PAGE_MODIFIED at bit 4
0228  *      _PAGE_GLOBAL at bit 6
0229  *      _PAGE_VALID at bit 7
0230  */
0231 #define __swp_type(x)           (((x).val >> 8) & 0x1f)
0232 #define __swp_offset(x)          ((x).val >> 13)
0233 #define __swp_entry(type,offset)    ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
0234 #define __pte_to_swp_entry(pte)     ((swp_entry_t) { pte_val(pte) })
0235 #define __swp_entry_to_pte(x)       ((pte_t) { (x).val })
0236
0237 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
0238
0239 #endif /* defined(CONFIG_CPU_R3K_TLB) */
0240
0241 #endif /* _ASM_PGTABLE_32_H */