Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
0007  * revision 1.76.
0008  *
0009  * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
0010  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
0011  */
0012 #ifndef _ASM_PCI_BRIDGE_H
0013 #define _ASM_PCI_BRIDGE_H
0014 
0015 #include <linux/types.h>
0016 #include <linux/pci.h>
0017 #include <asm/xtalk/xwidget.h>      /* generic widget header */
0018 #include <asm/sn/types.h>
0019 
0020 /* I/O page size */
0021 
0022 #define IOPFNSHIFT      12  /* 4K per mapped page */
0023 
0024 #define IOPGSIZE        (1 << IOPFNSHIFT)
0025 #define IOPG(x)         ((x) >> IOPFNSHIFT)
0026 #define IOPGOFF(x)      ((x) & (IOPGSIZE-1))
0027 
0028 /* Bridge RAM sizes */
0029 
0030 #define BRIDGE_ATE_RAM_SIZE 0x00000400  /* 1kB ATE RAM */
0031 
0032 #define BRIDGE_CONFIG_BASE  0x20000
0033 #define BRIDGE_CONFIG1_BASE 0x28000
0034 #define BRIDGE_CONFIG_END   0x30000
0035 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
0036 
0037 #define BRIDGE_SSRAM_512K   0x00080000  /* 512kB */
0038 #define BRIDGE_SSRAM_128K   0x00020000  /* 128kB */
0039 #define BRIDGE_SSRAM_64K    0x00010000  /* 64kB */
0040 #define BRIDGE_SSRAM_0K     0x00000000  /* 0kB */
0041 
0042 /* ========================================================================
0043  *    Bridge address map
0044  */
0045 
0046 #ifndef __ASSEMBLY__
0047 
0048 #define ATE_V       0x01
0049 #define ATE_CO      0x02
0050 #define ATE_PREC    0x04
0051 #define ATE_PREF    0x08
0052 #define ATE_BAR     0x10
0053 
0054 #define ATE_PFNSHIFT        12
0055 #define ATE_TIDSHIFT        8
0056 #define ATE_RMFSHIFT        48
0057 
0058 #define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
0059                  ((xid)<<ATE_TIDSHIFT) | \
0060                  (attr))
0061 
0062 #define BRIDGE_INTERNAL_ATES    128
0063 
0064 /*
0065  * It is generally preferred that hardware registers on the bridge
0066  * are located from C code via this structure.
0067  *
0068  * Generated from Bridge spec dated 04oct95
0069  */
0070 
0071 struct bridge_regs {
0072     /* Local Registers                 0x000000-0x00FFFF */
0073 
0074     /* standard widget configuration           0x000000-0x000057 */
0075     widget_cfg_t        b_widget;           /* 0x000000 */
0076 
0077     /* helper fieldnames for accessing bridge widget */
0078 
0079 #define b_wid_id            b_widget.w_id
0080 #define b_wid_stat          b_widget.w_status
0081 #define b_wid_err_upper         b_widget.w_err_upper_addr
0082 #define b_wid_err_lower         b_widget.w_err_lower_addr
0083 #define b_wid_control           b_widget.w_control
0084 #define b_wid_req_timeout       b_widget.w_req_timeout
0085 #define b_wid_int_upper         b_widget.w_intdest_upper_addr
0086 #define b_wid_int_lower         b_widget.w_intdest_lower_addr
0087 #define b_wid_err_cmdword       b_widget.w_err_cmd_word
0088 #define b_wid_llp           b_widget.w_llp_cfg
0089 #define b_wid_tflush            b_widget.w_tflush
0090 
0091     /* bridge-specific widget configuration 0x000058-0x00007F */
0092     u32 _pad_000058;
0093     u32 b_wid_aux_err;      /* 0x00005C */
0094     u32 _pad_000060;
0095     u32 b_wid_resp_upper;       /* 0x000064 */
0096     u32 _pad_000068;
0097     u32 b_wid_resp_lower;       /* 0x00006C */
0098     u32 _pad_000070;
0099     u32  b_wid_tst_pin_ctrl;        /* 0x000074 */
0100     u32 _pad_000078[2];
0101 
0102     /* PMU & Map 0x000080-0x00008F */
0103     u32 _pad_000080;
0104     u32 b_dir_map;          /* 0x000084 */
0105     u32 _pad_000088[2];
0106 
0107     /* SSRAM 0x000090-0x00009F */
0108     u32 _pad_000090;
0109     u32 b_ram_perr;         /* 0x000094 */
0110     u32 _pad_000098[2];
0111 
0112     /* Arbitration 0x0000A0-0x0000AF */
0113     u32 _pad_0000A0;
0114     u32 b_arb;              /* 0x0000A4 */
0115     u32 _pad_0000A8[2];
0116 
0117     /* Number In A Can 0x0000B0-0x0000BF */
0118     u32 _pad_0000B0;
0119     u32 b_nic;              /* 0x0000B4 */
0120     u32 _pad_0000B8[2];
0121 
0122     /* PCI/GIO 0x0000C0-0x0000FF */
0123     u32 _pad_0000C0;
0124     u32 b_bus_timeout;          /* 0x0000C4 */
0125 #define b_pci_bus_timeout b_bus_timeout
0126 
0127     u32 _pad_0000C8;
0128     u32 b_pci_cfg;          /* 0x0000CC */
0129     u32 _pad_0000D0;
0130     u32 b_pci_err_upper;        /* 0x0000D4 */
0131     u32 _pad_0000D8;
0132     u32 b_pci_err_lower;        /* 0x0000DC */
0133     u32 _pad_0000E0[8];
0134 #define b_gio_err_lower b_pci_err_lower
0135 #define b_gio_err_upper b_pci_err_upper
0136 
0137     /* Interrupt 0x000100-0x0001FF */
0138     u32 _pad_000100;
0139     u32 b_int_status;           /* 0x000104 */
0140     u32 _pad_000108;
0141     u32 b_int_enable;           /* 0x00010C */
0142     u32 _pad_000110;
0143     u32 b_int_rst_stat;         /* 0x000114 */
0144     u32 _pad_000118;
0145     u32 b_int_mode;         /* 0x00011C */
0146     u32 _pad_000120;
0147     u32 b_int_device;           /* 0x000124 */
0148     u32 _pad_000128;
0149     u32 b_int_host_err;         /* 0x00012C */
0150 
0151     struct {
0152         u32 __pad;          /* 0x0001{30,,,68} */
0153         u32 addr;           /* 0x0001{34,,,6C} */
0154     } b_int_addr[8];                /* 0x000130 */
0155 
0156     u32 _pad_000170[36];
0157 
0158     /* Device 0x000200-0x0003FF */
0159     struct {
0160         u32 __pad;          /* 0x0002{00,,,38} */
0161         u32 reg;            /* 0x0002{04,,,3C} */
0162     } b_device[8];                  /* 0x000200 */
0163 
0164     struct {
0165         u32 __pad;          /* 0x0002{40,,,78} */
0166         u32 reg;            /* 0x0002{44,,,7C} */
0167     } b_wr_req_buf[8];              /* 0x000240 */
0168 
0169     struct {
0170         u32 __pad;          /* 0x0002{80,,,88} */
0171         u32 reg;            /* 0x0002{84,,,8C} */
0172     } b_rrb_map[2];                 /* 0x000280 */
0173 #define b_even_resp b_rrb_map[0].reg        /* 0x000284 */
0174 #define b_odd_resp  b_rrb_map[1].reg        /* 0x00028C */
0175 
0176     u32 _pad_000290;
0177     u32 b_resp_status;          /* 0x000294 */
0178     u32 _pad_000298;
0179     u32 b_resp_clear;           /* 0x00029C */
0180 
0181     u32 _pad_0002A0[24];
0182 
0183     char        _pad_000300[0x10000 - 0x000300];
0184 
0185     /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
0186     union {
0187         u64 wr;         /* write-only */
0188         struct {
0189             u32 _p_pad;
0190             u32 rd;     /* read-only */
0191         }           hi;
0192     }               b_int_ate_ram[128];
0193 
0194     char    _pad_010400[0x11000 - 0x010400];
0195 
0196     /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
0197     struct {
0198         u32 _p_pad;
0199         u32 rd;     /* read-only */
0200     } b_int_ate_ram_lo[128];
0201 
0202     char    _pad_011400[0x20000 - 0x011400];
0203 
0204     /* PCI Device Configuration Spaces 0x020000-0x027FFF */
0205     union {             /* make all access sizes available. */
0206         u8  c[0x1000 / 1];
0207         u16 s[0x1000 / 2];
0208         u32 l[0x1000 / 4];
0209         u64 d[0x1000 / 8];
0210         union {
0211             u8  c[0x100 / 1];
0212             u16 s[0x100 / 2];
0213             u32 l[0x100 / 4];
0214             u64 d[0x100 / 8];
0215         } f[8];
0216     } b_type0_cfg_dev[8];                   /* 0x020000 */
0217 
0218     /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
0219     union {             /* make all access sizes available. */
0220         u8  c[0x1000 / 1];
0221         u16 s[0x1000 / 2];
0222         u32 l[0x1000 / 4];
0223         u64 d[0x1000 / 8];
0224     } b_type1_cfg;                  /* 0x028000-0x029000 */
0225 
0226     char    _pad_029000[0x007000];          /* 0x029000-0x030000 */
0227 
0228     /* PCI Interrupt Acknowledge Cycle 0x030000 */
0229     union {
0230         u8  c[8 / 1];
0231         u16 s[8 / 2];
0232         u32 l[8 / 4];
0233         u64 d[8 / 8];
0234     } b_pci_iack;                       /* 0x030000 */
0235 
0236     u8  _pad_030007[0x04fff8];          /* 0x030008-0x07FFFF */
0237 
0238     /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
0239     u64 b_ext_ate_ram[0x10000];
0240 
0241     /* Reserved 0x100000-0x1FFFFF */
0242     char    _pad_100000[0x200000-0x100000];
0243 
0244     /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
0245     union {             /* make all access sizes available. */
0246         u8  c[0x100000 / 1];
0247         u16 s[0x100000 / 2];
0248         u32 l[0x100000 / 4];
0249         u64 d[0x100000 / 8];
0250     } b_devio_raw[10];              /* 0x200000 */
0251 
0252     /* b_devio macro is a bit strange; it reflects the
0253      * fact that the Bridge ASIC provides 2M for the
0254      * first two DevIO windows and 1M for the other six.
0255      */
0256 #define b_devio(n)  b_devio_raw[((n)<2)?(n*2):(n+2)]
0257 
0258     /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
0259     union {     /* make all access sizes available. */
0260         u8  c[0x400000 / 1];    /* read-only */
0261         u16 s[0x400000 / 2];    /* read-write */
0262         u32 l[0x400000 / 4];    /* read-only */
0263         u64 d[0x400000 / 8];    /* read-only */
0264     } b_external_flash;         /* 0xC00000 */
0265 };
0266 
0267 /*
0268  * Field formats for Error Command Word and Auxiliary Error Command Word
0269  * of bridge.
0270  */
0271 struct bridge_err_cmdword {
0272     union {
0273         u32     cmd_word;
0274         struct {
0275             u32 didn:4,     /* Destination ID  */
0276                 sidn:4,     /* Source ID       */
0277                 pactyp:4,   /* Packet type     */
0278                 tnum:5,     /* Trans Number    */
0279                 coh:1,      /* Coh Transaction */
0280                 ds:2,       /* Data size       */
0281                 gbr:1,      /* GBR enable      */
0282                 vbpm:1,     /* VBPM message    */
0283                 error:1,    /* Error occurred  */
0284                 barr:1,     /* Barrier op      */
0285                 rsvd:8;
0286         } berr_st;
0287     } berr_un;
0288 };
0289 
0290 #define berr_field  berr_un.berr_st
0291 #endif /* !__ASSEMBLY__ */
0292 
0293 /*
0294  * The values of these macros can and should be crosschecked
0295  * regularly against the offsets of the like-named fields
0296  * within the bridge_regs structure above.
0297  */
0298 
0299 /* Byte offset macros for Bridge internal registers */
0300 
0301 #define BRIDGE_WID_ID       WIDGET_ID
0302 #define BRIDGE_WID_STAT     WIDGET_STATUS
0303 #define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
0304 #define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
0305 #define BRIDGE_WID_CONTROL  WIDGET_CONTROL
0306 #define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
0307 #define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
0308 #define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
0309 #define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
0310 #define BRIDGE_WID_LLP      WIDGET_LLP_CFG
0311 #define BRIDGE_WID_TFLUSH   WIDGET_TFLUSH
0312 
0313 #define BRIDGE_WID_AUX_ERR  0x00005C    /* Aux Error Command Word */
0314 #define BRIDGE_WID_RESP_UPPER   0x000064    /* Response Buf Upper Addr */
0315 #define BRIDGE_WID_RESP_LOWER   0x00006C    /* Response Buf Lower Addr */
0316 #define BRIDGE_WID_TST_PIN_CTRL 0x000074    /* Test pin control */
0317 
0318 #define BRIDGE_DIR_MAP      0x000084    /* Direct Map reg */
0319 
0320 #define BRIDGE_RAM_PERR     0x000094    /* SSRAM Parity Error */
0321 
0322 #define BRIDGE_ARB      0x0000A4    /* Arbitration Priority reg */
0323 
0324 #define BRIDGE_NIC      0x0000B4    /* Number In A Can */
0325 
0326 #define BRIDGE_BUS_TIMEOUT  0x0000C4    /* Bus Timeout Register */
0327 #define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
0328 #define BRIDGE_PCI_CFG      0x0000CC    /* PCI Type 1 Config reg */
0329 #define BRIDGE_PCI_ERR_UPPER    0x0000D4    /* PCI error Upper Addr */
0330 #define BRIDGE_PCI_ERR_LOWER    0x0000DC    /* PCI error Lower Addr */
0331 
0332 #define BRIDGE_INT_STATUS   0x000104    /* Interrupt Status */
0333 #define BRIDGE_INT_ENABLE   0x00010C    /* Interrupt Enables */
0334 #define BRIDGE_INT_RST_STAT 0x000114    /* Reset Intr Status */
0335 #define BRIDGE_INT_MODE     0x00011C    /* Interrupt Mode */
0336 #define BRIDGE_INT_DEVICE   0x000124    /* Interrupt Device */
0337 #define BRIDGE_INT_HOST_ERR 0x00012C    /* Host Error Field */
0338 
0339 #define BRIDGE_INT_ADDR0    0x000134    /* Host Address Reg */
0340 #define BRIDGE_INT_ADDR_OFF 0x000008    /* Host Addr offset (1..7) */
0341 #define BRIDGE_INT_ADDR(x)  (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
0342 
0343 #define BRIDGE_DEVICE0      0x000204    /* Device 0 */
0344 #define BRIDGE_DEVICE_OFF   0x000008    /* Device offset (1..7) */
0345 #define BRIDGE_DEVICE(x)    (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
0346 
0347 #define BRIDGE_WR_REQ_BUF0  0x000244    /* Write Request Buffer 0 */
0348 #define BRIDGE_WR_REQ_BUF_OFF   0x000008    /* Buffer Offset (1..7) */
0349 #define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
0350 
0351 #define BRIDGE_EVEN_RESP    0x000284    /* Even Device Response Buf */
0352 #define BRIDGE_ODD_RESP     0x00028C    /* Odd Device Response Buf */
0353 
0354 #define BRIDGE_RESP_STATUS  0x000294    /* Read Response Status reg */
0355 #define BRIDGE_RESP_CLEAR   0x00029C    /* Read Response Clear reg */
0356 
0357 /* Byte offset macros for Bridge I/O space */
0358 
0359 #define BRIDGE_ATE_RAM      0x00010000  /* Internal Addr Xlat Ram */
0360 
0361 #define BRIDGE_TYPE0_CFG_DEV0   0x00020000  /* Type 0 Cfg, Device 0 */
0362 #define BRIDGE_TYPE0_CFG_SLOT_OFF   0x00001000  /* Type 0 Cfg Slot Offset (1..7) */
0363 #define BRIDGE_TYPE0_CFG_FUNC_OFF   0x00000100  /* Type 0 Cfg Func Offset (1..7) */
0364 #define BRIDGE_TYPE0_CFG_DEV(s)     (BRIDGE_TYPE0_CFG_DEV0+\
0365                      (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
0366 #define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\
0367                      (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
0368                      (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
0369 
0370 #define BRIDGE_TYPE1_CFG    0x00028000  /* Type 1 Cfg space */
0371 
0372 #define BRIDGE_PCI_IACK     0x00030000  /* PCI Interrupt Ack */
0373 #define BRIDGE_EXT_SSRAM    0x00080000  /* Extern SSRAM (ATE) */
0374 
0375 /* Byte offset macros for Bridge device IO spaces */
0376 
0377 #define BRIDGE_DEV_CNT      8   /* Up to 8 devices per bridge */
0378 #define BRIDGE_DEVIO0       0x00200000  /* Device IO 0 Addr */
0379 #define BRIDGE_DEVIO1       0x00400000  /* Device IO 1 Addr */
0380 #define BRIDGE_DEVIO2       0x00600000  /* Device IO 2 Addr */
0381 #define BRIDGE_DEVIO_OFF    0x00100000  /* Device IO Offset (3..7) */
0382 
0383 #define BRIDGE_DEVIO_2MB    0x00200000  /* Device IO Offset (0..1) */
0384 #define BRIDGE_DEVIO_1MB    0x00100000  /* Device IO Offset (2..7) */
0385 
0386 #define BRIDGE_DEVIO(x)     ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
0387 
0388 #define BRIDGE_EXTERNAL_FLASH   0x00C00000  /* External Flash PROMS */
0389 
0390 /* ========================================================================
0391  *    Bridge register bit field definitions
0392  */
0393 
0394 /* Widget part number of bridge */
0395 #define BRIDGE_WIDGET_PART_NUM      0xc002
0396 #define XBRIDGE_WIDGET_PART_NUM     0xd002
0397 
0398 /* Manufacturer of bridge */
0399 #define BRIDGE_WIDGET_MFGR_NUM      0x036
0400 #define XBRIDGE_WIDGET_MFGR_NUM     0x024
0401 
0402 /* Revision numbers for known Bridge revisions */
0403 #define BRIDGE_REV_A            0x1
0404 #define BRIDGE_REV_B            0x2
0405 #define BRIDGE_REV_C            0x3
0406 #define BRIDGE_REV_D            0x4
0407 
0408 /* Bridge widget status register bits definition */
0409 
0410 #define BRIDGE_STAT_LLP_REC_CNT     (0xFFu << 24)
0411 #define BRIDGE_STAT_LLP_TX_CNT      (0xFF << 16)
0412 #define BRIDGE_STAT_FLASH_SELECT    (0x1 << 6)
0413 #define BRIDGE_STAT_PCI_GIO_N       (0x1 << 5)
0414 #define BRIDGE_STAT_PENDING     (0x1F << 0)
0415 
0416 /* Bridge widget control register bits definition */
0417 #define BRIDGE_CTRL_FLASH_WR_EN     (0x1ul << 31)
0418 #define BRIDGE_CTRL_EN_CLK50        (0x1 << 30)
0419 #define BRIDGE_CTRL_EN_CLK40        (0x1 << 29)
0420 #define BRIDGE_CTRL_EN_CLK33        (0x1 << 28)
0421 #define BRIDGE_CTRL_RST(n)      ((n) << 24)
0422 #define BRIDGE_CTRL_RST_MASK        (BRIDGE_CTRL_RST(0xF))
0423 #define BRIDGE_CTRL_RST_PIN(x)      (BRIDGE_CTRL_RST(0x1 << (x)))
0424 #define BRIDGE_CTRL_IO_SWAP     (0x1 << 23)
0425 #define BRIDGE_CTRL_MEM_SWAP        (0x1 << 22)
0426 #define BRIDGE_CTRL_PAGE_SIZE       (0x1 << 21)
0427 #define BRIDGE_CTRL_SS_PAR_BAD      (0x1 << 20)
0428 #define BRIDGE_CTRL_SS_PAR_EN       (0x1 << 19)
0429 #define BRIDGE_CTRL_SSRAM_SIZE(n)   ((n) << 17)
0430 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
0431 #define BRIDGE_CTRL_SSRAM_512K      (BRIDGE_CTRL_SSRAM_SIZE(0x3))
0432 #define BRIDGE_CTRL_SSRAM_128K      (BRIDGE_CTRL_SSRAM_SIZE(0x2))
0433 #define BRIDGE_CTRL_SSRAM_64K       (BRIDGE_CTRL_SSRAM_SIZE(0x1))
0434 #define BRIDGE_CTRL_SSRAM_1K        (BRIDGE_CTRL_SSRAM_SIZE(0x0))
0435 #define BRIDGE_CTRL_F_BAD_PKT       (0x1 << 16)
0436 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
0437 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
0438 #define BRIDGE_CTRL_CLR_RLLP_CNT    (0x1 << 11)
0439 #define BRIDGE_CTRL_CLR_TLLP_CNT    (0x1 << 10)
0440 #define BRIDGE_CTRL_SYS_END     (0x1 << 9)
0441 #define BRIDGE_CTRL_MAX_TRANS(n)    ((n) << 4)
0442 #define BRIDGE_CTRL_MAX_TRANS_MASK  (BRIDGE_CTRL_MAX_TRANS(0x1f))
0443 #define BRIDGE_CTRL_WIDGET_ID(n)    ((n) << 0)
0444 #define BRIDGE_CTRL_WIDGET_ID_MASK  (BRIDGE_CTRL_WIDGET_ID(0xf))
0445 
0446 /* Bridge Response buffer Error Upper Register bit fields definition */
0447 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
0448 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
0449 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
0450 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
0451 #define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
0452 
0453 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
0454             (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
0455                 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
0456 
0457 #define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
0458             (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
0459                  BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
0460 
0461 /* Bridge direct mapping register bits definition */
0462 #define BRIDGE_DIRMAP_W_ID_SHFT     20
0463 #define BRIDGE_DIRMAP_W_ID      (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
0464 #define BRIDGE_DIRMAP_RMF_64        (0x1 << 18)
0465 #define BRIDGE_DIRMAP_ADD512        (0x1 << 17)
0466 #define BRIDGE_DIRMAP_OFF       (0x1ffff << 0)
0467 #define BRIDGE_DIRMAP_OFF_ADDRSHFT  (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
0468 
0469 /* Bridge Arbitration register bits definition */
0470 #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
0471 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
0472 #define BRIDGE_ARB_REQ_WAIT_EN(x)   ((x) << 8)
0473 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
0474 #define BRIDGE_ARB_FREEZE_GNT       (1 << 6)
0475 #define BRIDGE_ARB_HPRI_RING_B2     (1 << 5)
0476 #define BRIDGE_ARB_HPRI_RING_B1     (1 << 4)
0477 #define BRIDGE_ARB_HPRI_RING_B0     (1 << 3)
0478 #define BRIDGE_ARB_LPRI_RING_B2     (1 << 2)
0479 #define BRIDGE_ARB_LPRI_RING_B1     (1 << 1)
0480 #define BRIDGE_ARB_LPRI_RING_B0     (1 << 0)
0481 
0482 /* Bridge Bus time-out register bits definition */
0483 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
0484 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
0485 #define BRIDGE_BUS_GIO_TIMEOUT      (1 << 12)
0486 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
0487 #define BRIDGE_BUS_PCI_RETRY_MASK   BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
0488 
0489 /* Bridge interrupt status register bits definition */
0490 #define BRIDGE_ISR_MULTI_ERR        (0x1u << 31)
0491 #define BRIDGE_ISR_PMU_ESIZE_FAULT  (0x1 << 30)
0492 #define BRIDGE_ISR_UNEXP_RESP       (0x1 << 29)
0493 #define BRIDGE_ISR_BAD_XRESP_PKT    (0x1 << 28)
0494 #define BRIDGE_ISR_BAD_XREQ_PKT     (0x1 << 27)
0495 #define BRIDGE_ISR_RESP_XTLK_ERR    (0x1 << 26)
0496 #define BRIDGE_ISR_REQ_XTLK_ERR     (0x1 << 25)
0497 #define BRIDGE_ISR_INVLD_ADDR       (0x1 << 24)
0498 #define BRIDGE_ISR_UNSUPPORTED_XOP  (0x1 << 23)
0499 #define BRIDGE_ISR_XREQ_FIFO_OFLOW  (0x1 << 22)
0500 #define BRIDGE_ISR_LLP_REC_SNERR    (0x1 << 21)
0501 #define BRIDGE_ISR_LLP_REC_CBERR    (0x1 << 20)
0502 #define BRIDGE_ISR_LLP_RCTY     (0x1 << 19)
0503 #define BRIDGE_ISR_LLP_TX_RETRY     (0x1 << 18)
0504 #define BRIDGE_ISR_LLP_TCTY     (0x1 << 17)
0505 #define BRIDGE_ISR_SSRAM_PERR       (0x1 << 16)
0506 #define BRIDGE_ISR_PCI_ABORT        (0x1 << 15)
0507 #define BRIDGE_ISR_PCI_PARITY       (0x1 << 14)
0508 #define BRIDGE_ISR_PCI_SERR     (0x1 << 13)
0509 #define BRIDGE_ISR_PCI_PERR     (0x1 << 12)
0510 #define BRIDGE_ISR_PCI_MST_TIMEOUT  (0x1 << 11)
0511 #define BRIDGE_ISR_GIO_MST_TIMEOUT  BRIDGE_ISR_PCI_MST_TIMEOUT
0512 #define BRIDGE_ISR_PCI_RETRY_CNT    (0x1 << 10)
0513 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
0514 #define BRIDGE_ISR_GIO_B_ENBL_ERR   (0x1 << 8)
0515 #define BRIDGE_ISR_INT_MSK      (0xff << 0)
0516 #define BRIDGE_ISR_INT(x)       (0x1 << (x))
0517 
0518 #define BRIDGE_ISR_LINK_ERROR       \
0519         (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \
0520          BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|       \
0521          BRIDGE_ISR_LLP_TCTY)
0522 
0523 #define BRIDGE_ISR_PCIBUS_PIOERR    \
0524         (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
0525 
0526 #define BRIDGE_ISR_PCIBUS_ERROR     \
0527         (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|      \
0528          BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|      \
0529          BRIDGE_ISR_PCI_PARITY)
0530 
0531 #define BRIDGE_ISR_XTALK_ERROR      \
0532         (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
0533          BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|  \
0534          BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|  \
0535          BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|  \
0536          BRIDGE_ISR_UNEXP_RESP)
0537 
0538 #define BRIDGE_ISR_ERRORS       \
0539         (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|     \
0540          BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|      \
0541          BRIDGE_ISR_PMU_ESIZE_FAULT)
0542 
0543 /*
0544  * List of Errors which are fatal and kill the system
0545  */
0546 #define BRIDGE_ISR_ERROR_FATAL      \
0547         ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
0548          BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
0549 
0550 #define BRIDGE_ISR_ERROR_DUMP       \
0551         (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
0552          BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
0553 
0554 /* Bridge interrupt enable register bits definition */
0555 #define BRIDGE_IMR_UNEXP_RESP       BRIDGE_ISR_UNEXP_RESP
0556 #define BRIDGE_IMR_PMU_ESIZE_FAULT  BRIDGE_ISR_PMU_ESIZE_FAULT
0557 #define BRIDGE_IMR_BAD_XRESP_PKT    BRIDGE_ISR_BAD_XRESP_PKT
0558 #define BRIDGE_IMR_BAD_XREQ_PKT     BRIDGE_ISR_BAD_XREQ_PKT
0559 #define BRIDGE_IMR_RESP_XTLK_ERR    BRIDGE_ISR_RESP_XTLK_ERR
0560 #define BRIDGE_IMR_REQ_XTLK_ERR     BRIDGE_ISR_REQ_XTLK_ERR
0561 #define BRIDGE_IMR_INVLD_ADDR       BRIDGE_ISR_INVLD_ADDR
0562 #define BRIDGE_IMR_UNSUPPORTED_XOP  BRIDGE_ISR_UNSUPPORTED_XOP
0563 #define BRIDGE_IMR_XREQ_FIFO_OFLOW  BRIDGE_ISR_XREQ_FIFO_OFLOW
0564 #define BRIDGE_IMR_LLP_REC_SNERR    BRIDGE_ISR_LLP_REC_SNERR
0565 #define BRIDGE_IMR_LLP_REC_CBERR    BRIDGE_ISR_LLP_REC_CBERR
0566 #define BRIDGE_IMR_LLP_RCTY     BRIDGE_ISR_LLP_RCTY
0567 #define BRIDGE_IMR_LLP_TX_RETRY     BRIDGE_ISR_LLP_TX_RETRY
0568 #define BRIDGE_IMR_LLP_TCTY     BRIDGE_ISR_LLP_TCTY
0569 #define BRIDGE_IMR_SSRAM_PERR       BRIDGE_ISR_SSRAM_PERR
0570 #define BRIDGE_IMR_PCI_ABORT        BRIDGE_ISR_PCI_ABORT
0571 #define BRIDGE_IMR_PCI_PARITY       BRIDGE_ISR_PCI_PARITY
0572 #define BRIDGE_IMR_PCI_SERR     BRIDGE_ISR_PCI_SERR
0573 #define BRIDGE_IMR_PCI_PERR     BRIDGE_ISR_PCI_PERR
0574 #define BRIDGE_IMR_PCI_MST_TIMEOUT  BRIDGE_ISR_PCI_MST_TIMEOUT
0575 #define BRIDGE_IMR_GIO_MST_TIMEOUT  BRIDGE_ISR_GIO_MST_TIMEOUT
0576 #define BRIDGE_IMR_PCI_RETRY_CNT    BRIDGE_ISR_PCI_RETRY_CNT
0577 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
0578 #define BRIDGE_IMR_GIO_B_ENBL_ERR   BRIDGE_ISR_GIO_B_ENBL_ERR
0579 #define BRIDGE_IMR_INT_MSK      BRIDGE_ISR_INT_MSK
0580 #define BRIDGE_IMR_INT(x)       BRIDGE_ISR_INT(x)
0581 
0582 /* Bridge interrupt reset register bits definition */
0583 #define BRIDGE_IRR_MULTI_CLR        (0x1 << 6)
0584 #define BRIDGE_IRR_CRP_GRP_CLR      (0x1 << 5)
0585 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
0586 #define BRIDGE_IRR_REQ_DSP_GRP_CLR  (0x1 << 3)
0587 #define BRIDGE_IRR_LLP_GRP_CLR      (0x1 << 2)
0588 #define BRIDGE_IRR_SSRAM_GRP_CLR    (0x1 << 1)
0589 #define BRIDGE_IRR_PCI_GRP_CLR      (0x1 << 0)
0590 #define BRIDGE_IRR_GIO_GRP_CLR      (0x1 << 0)
0591 #define BRIDGE_IRR_ALL_CLR      0x7f
0592 
0593 #define BRIDGE_IRR_CRP_GRP      (BRIDGE_ISR_UNEXP_RESP | \
0594                      BRIDGE_ISR_XREQ_FIFO_OFLOW)
0595 #define BRIDGE_IRR_RESP_BUF_GRP     (BRIDGE_ISR_BAD_XRESP_PKT | \
0596                      BRIDGE_ISR_RESP_XTLK_ERR | \
0597                      BRIDGE_ISR_XREAD_REQ_TIMEOUT)
0598 #define BRIDGE_IRR_REQ_DSP_GRP      (BRIDGE_ISR_UNSUPPORTED_XOP | \
0599                      BRIDGE_ISR_BAD_XREQ_PKT | \
0600                      BRIDGE_ISR_REQ_XTLK_ERR | \
0601                      BRIDGE_ISR_INVLD_ADDR)
0602 #define BRIDGE_IRR_LLP_GRP      (BRIDGE_ISR_LLP_REC_SNERR | \
0603                      BRIDGE_ISR_LLP_REC_CBERR | \
0604                      BRIDGE_ISR_LLP_RCTY | \
0605                      BRIDGE_ISR_LLP_TX_RETRY | \
0606                      BRIDGE_ISR_LLP_TCTY)
0607 #define BRIDGE_IRR_SSRAM_GRP        (BRIDGE_ISR_SSRAM_PERR | \
0608                      BRIDGE_ISR_PMU_ESIZE_FAULT)
0609 #define BRIDGE_IRR_PCI_GRP      (BRIDGE_ISR_PCI_ABORT | \
0610                      BRIDGE_ISR_PCI_PARITY | \
0611                      BRIDGE_ISR_PCI_SERR | \
0612                      BRIDGE_ISR_PCI_PERR | \
0613                      BRIDGE_ISR_PCI_MST_TIMEOUT | \
0614                      BRIDGE_ISR_PCI_RETRY_CNT)
0615 
0616 #define BRIDGE_IRR_GIO_GRP      (BRIDGE_ISR_GIO_B_ENBL_ERR | \
0617                      BRIDGE_ISR_GIO_MST_TIMEOUT)
0618 
0619 /* Bridge INT_DEV register bits definition */
0620 #define BRIDGE_INT_DEV_SHFT(n)      ((n)*3)
0621 #define BRIDGE_INT_DEV_MASK(n)      (0x7 << BRIDGE_INT_DEV_SHFT(n))
0622 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
0623 
0624 /* Bridge interrupt(x) register bits definition */
0625 #define BRIDGE_INT_ADDR_HOST        0x0003FF00
0626 #define BRIDGE_INT_ADDR_FLD     0x000000FF
0627 
0628 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
0629 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
0630 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
0631 
0632 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
0633 
0634 /*
0635  * The NASID should be shifted by this amount and stored into the
0636  * interrupt(x) register.
0637  */
0638 #define BRIDGE_INT_ADDR_NASID_SHFT  8
0639 
0640 /*
0641  * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
0642  * memory.
0643  */
0644 #define BRIDGE_INT_ADDR_DEST_IO     (1 << 17)
0645 #define BRIDGE_INT_ADDR_DEST_MEM    0
0646 #define BRIDGE_INT_ADDR_MASK        (1 << 17)
0647 
0648 /* Bridge device(x) register bits definition */
0649 #define BRIDGE_DEV_ERR_LOCK_EN      0x10000000
0650 #define BRIDGE_DEV_PAGE_CHK_DIS     0x08000000
0651 #define BRIDGE_DEV_FORCE_PCI_PAR    0x04000000
0652 #define BRIDGE_DEV_VIRTUAL_EN       0x02000000
0653 #define BRIDGE_DEV_PMU_WRGA_EN      0x01000000
0654 #define BRIDGE_DEV_DIR_WRGA_EN      0x00800000
0655 #define BRIDGE_DEV_DEV_SIZE     0x00400000
0656 #define BRIDGE_DEV_RT           0x00200000
0657 #define BRIDGE_DEV_SWAP_PMU     0x00100000
0658 #define BRIDGE_DEV_SWAP_DIR     0x00080000
0659 #define BRIDGE_DEV_PREF         0x00040000
0660 #define BRIDGE_DEV_PRECISE      0x00020000
0661 #define BRIDGE_DEV_COH          0x00010000
0662 #define BRIDGE_DEV_BARRIER      0x00008000
0663 #define BRIDGE_DEV_GBR          0x00004000
0664 #define BRIDGE_DEV_DEV_SWAP     0x00002000
0665 #define BRIDGE_DEV_DEV_IO_MEM       0x00001000
0666 #define BRIDGE_DEV_OFF_MASK     0x00000fff
0667 #define BRIDGE_DEV_OFF_ADDR_SHFT    20
0668 
0669 #define BRIDGE_DEV_PMU_BITS     (BRIDGE_DEV_PMU_WRGA_EN     | \
0670                      BRIDGE_DEV_SWAP_PMU)
0671 #define BRIDGE_DEV_D32_BITS     (BRIDGE_DEV_DIR_WRGA_EN     | \
0672                      BRIDGE_DEV_SWAP_DIR        | \
0673                      BRIDGE_DEV_PREF        | \
0674                      BRIDGE_DEV_PRECISE     | \
0675                      BRIDGE_DEV_COH         | \
0676                      BRIDGE_DEV_BARRIER)
0677 #define BRIDGE_DEV_D64_BITS     (BRIDGE_DEV_DIR_WRGA_EN     | \
0678                      BRIDGE_DEV_SWAP_DIR        | \
0679                      BRIDGE_DEV_COH         | \
0680                      BRIDGE_DEV_BARRIER)
0681 
0682 /* Bridge Error Upper register bit field definition */
0683 #define BRIDGE_ERRUPPR_DEVMASTER    (0x1 << 20) /* Device was master */
0684 #define BRIDGE_ERRUPPR_PCIVDEV      (0x1 << 19) /* Virtual Req value */
0685 #define BRIDGE_ERRUPPR_DEVNUM_SHFT  (16)
0686 #define BRIDGE_ERRUPPR_DEVNUM_MASK  (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
0687 #define BRIDGE_ERRUPPR_DEVICE(err)  (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
0688 #define BRIDGE_ERRUPPR_ADDRMASK     (0xFFFF)
0689 
0690 /* Bridge interrupt mode register bits definition */
0691 #define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
0692 
0693 /* this should be written to the xbow's link_control(x) register */
0694 #define BRIDGE_CREDIT   3
0695 
0696 /* RRB assignment register */
0697 #define BRIDGE_RRB_EN   0x8 /* after shifting down */
0698 #define BRIDGE_RRB_DEV  0x7 /* after shifting down */
0699 #define BRIDGE_RRB_VDEV 0x4 /* after shifting down */
0700 #define BRIDGE_RRB_PDEV 0x3 /* after shifting down */
0701 
0702 /* RRB status register */
0703 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
0704 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
0705 
0706 /* RRB clear register */
0707 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
0708 
0709 /* xbox system controller declarations */
0710 #define XBOX_BRIDGE_WID     8
0711 #define FLASH_PROM1_BASE    0xE00000 /* To read the xbox sysctlr status */
0712 #define XBOX_RPS_EXISTS     1 << 6   /* RPS bit in status register */
0713 #define XBOX_RPS_FAIL       1 << 4   /* RPS status bit in register */
0714 
0715 /* ========================================================================
0716  */
0717 /*
0718  * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
0719  * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
0720  */
0721 /* XTALK addresses that map into Bridge Bus addr space */
0722 #define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
0723 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
0724 #define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
0725 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
0726 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
0727 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
0728 
0729 /* Ranges of PCI bus space that can be accessed via PIO from xtalk */
0730 #define BRIDGE_MIN_PIO_ADDR_MEM     0x00000000  /* 1G PCI memory space */
0731 #define BRIDGE_MAX_PIO_ADDR_MEM     0x3fffffff
0732 #define BRIDGE_MIN_PIO_ADDR_IO      0x00000000  /* 4G PCI IO space */
0733 #define BRIDGE_MAX_PIO_ADDR_IO      0xffffffff
0734 
0735 /* XTALK addresses that map into PCI addresses */
0736 #define BRIDGE_PCI_MEM32_BASE       BRIDGE_PIO32_XTALK_ALIAS_BASE
0737 #define BRIDGE_PCI_MEM32_LIMIT      BRIDGE_PIO32_XTALK_ALIAS_LIMIT
0738 #define BRIDGE_PCI_MEM64_BASE       BRIDGE_PIO64_XTALK_ALIAS_BASE
0739 #define BRIDGE_PCI_MEM64_LIMIT      BRIDGE_PIO64_XTALK_ALIAS_LIMIT
0740 #define BRIDGE_PCI_IO_BASE      BRIDGE_PCIIO_XTALK_ALIAS_BASE
0741 #define BRIDGE_PCI_IO_LIMIT     BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
0742 
0743 /*
0744  * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
0745  */
0746 /* Bridge Bus DMA addresses */
0747 #define BRIDGE_LOCAL_BASE       0
0748 #define BRIDGE_DMA_MAPPED_BASE      0x40000000
0749 #define BRIDGE_DMA_MAPPED_SIZE      0x40000000  /* 1G Bytes */
0750 #define BRIDGE_DMA_DIRECT_BASE      0x80000000
0751 #define BRIDGE_DMA_DIRECT_SIZE      0x80000000  /* 2G Bytes */
0752 
0753 #define PCI32_LOCAL_BASE        BRIDGE_LOCAL_BASE
0754 
0755 /* PCI addresses of regions decoded by Bridge for DMA */
0756 #define PCI32_MAPPED_BASE       BRIDGE_DMA_MAPPED_BASE
0757 #define PCI32_DIRECT_BASE       BRIDGE_DMA_DIRECT_BASE
0758 
0759 #define IS_PCI32_LOCAL(x)   ((ulong_t)(x) < PCI32_MAPPED_BASE)
0760 #define IS_PCI32_MAPPED(x)  ((ulong_t)(x) < PCI32_DIRECT_BASE && \
0761                     (ulong_t)(x) >= PCI32_MAPPED_BASE)
0762 #define IS_PCI32_DIRECT(x)  ((ulong_t)(x) >= PCI32_MAPPED_BASE)
0763 #define IS_PCI64(x)     ((ulong_t)(x) >= PCI64_BASE)
0764 
0765 /*
0766  * The GIO address space.
0767  */
0768 /* Xtalk to GIO PIO */
0769 #define BRIDGE_GIO_MEM32_BASE       BRIDGE_PIO32_XTALK_ALIAS_BASE
0770 #define BRIDGE_GIO_MEM32_LIMIT      BRIDGE_PIO32_XTALK_ALIAS_LIMIT
0771 
0772 #define GIO_LOCAL_BASE          BRIDGE_LOCAL_BASE
0773 
0774 /* GIO addresses of regions decoded by Bridge for DMA */
0775 #define GIO_MAPPED_BASE         BRIDGE_DMA_MAPPED_BASE
0776 #define GIO_DIRECT_BASE         BRIDGE_DMA_DIRECT_BASE
0777 
0778 #define IS_GIO_LOCAL(x)     ((ulong_t)(x) < GIO_MAPPED_BASE)
0779 #define IS_GIO_MAPPED(x)    ((ulong_t)(x) < GIO_DIRECT_BASE && \
0780                     (ulong_t)(x) >= GIO_MAPPED_BASE)
0781 #define IS_GIO_DIRECT(x)    ((ulong_t)(x) >= GIO_MAPPED_BASE)
0782 
0783 /* PCI to xtalk mapping */
0784 
0785 /* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
0786  * which xtalk address is accessed
0787  */
0788 #define BRIDGE_DIRECT_32_SEG_SIZE   BRIDGE_DMA_DIRECT_SIZE
0789 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)      \
0790     ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +    \
0791         ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
0792 
0793 /* 64-bit address attribute masks */
0794 #define PCI64_ATTR_TARG_MASK    0xf000000000000000
0795 #define PCI64_ATTR_TARG_SHFT    60
0796 #define PCI64_ATTR_PREF     0x0800000000000000
0797 #define PCI64_ATTR_PREC     0x0400000000000000
0798 #define PCI64_ATTR_VIRTUAL  0x0200000000000000
0799 #define PCI64_ATTR_BAR      0x0100000000000000
0800 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000
0801 #define PCI64_ATTR_RMF_SHFT 48
0802 
0803 struct bridge_controller {
0804     struct resource     busn;
0805     struct bridge_regs  *base;
0806     unsigned long       baddr;
0807     unsigned long       intr_addr;
0808     struct irq_domain   *domain;
0809     unsigned int        pci_int[8][2];
0810     unsigned int        int_mapping[8][2];
0811     u32         ioc3_sid[8];
0812     nasid_t         nasid;
0813 };
0814 
0815 #define BRIDGE_CONTROLLER(bus) \
0816     ((struct bridge_controller *)((bus)->sysdata))
0817 
0818 #define bridge_read(bc, reg)        __raw_readl(&bc->base->reg)
0819 #define bridge_write(bc, reg, val)  __raw_writel(val, &bc->base->reg)
0820 #define bridge_set(bc, reg, val)    \
0821     __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
0822 #define bridge_clr(bc, reg, val)    \
0823     __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
0824 
0825 #endif /* _ASM_PCI_BRIDGE_H */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!