asm/octeon/octeon.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2004-2008 Cavium Networks
0007  */
0008 #ifndef __ASM_OCTEON_OCTEON_H
0009 #define __ASM_OCTEON_OCTEON_H
0010
0011 #include <asm/octeon/cvmx.h>
0012 #include <asm/bitfield.h>
0013
0014 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
0015                         uint64_t alignment,
0016                         uint64_t min_addr,
0017                         uint64_t max_addr,
0018                         int do_locking);
0019 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
0020                   int do_locking);
0021 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
0022                     uint64_t min_addr, uint64_t max_addr,
0023                     int do_locking);
0024 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
0025                     char *name);
0026 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
0027                           uint64_t max_addr, uint64_t align,
0028                           char *name);
0029 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
0030                         char *name);
0031 extern int octeon_bootmem_free_named(char *name);
0032 extern void octeon_bootmem_lock(void);
0033 extern void octeon_bootmem_unlock(void);
0034
0035 extern int octeon_is_simulation(void);
0036 extern int octeon_is_pci_host(void);
0037 extern int octeon_usb_is_ref_clk(void);
0038 extern uint64_t octeon_get_clock_rate(void);
0039 extern u64 octeon_get_io_clock_rate(void);
0040 extern const char *octeon_board_type_string(void);
0041 extern const char *octeon_get_pci_interrupts(void);
0042 extern int octeon_get_southbridge_interrupt(void);
0043 extern int octeon_get_boot_coremask(void);
0044 extern int octeon_get_boot_num_arguments(void);
0045 extern const char *octeon_get_boot_argument(int arg);
0046 extern void octeon_hal_setup_reserved32(void);
0047 extern void octeon_user_io_init(void);
0048
0049 extern void octeon_init_cvmcount(void);
0050 extern void octeon_setup_delays(void);
0051 extern void octeon_io_clk_delay(unsigned long);
0052
0053 #define OCTEON_ARGV_MAX_ARGS    64
0054 #define OCTEON_SERIAL_LEN   20
0055
0056 struct octeon_boot_descriptor {
0057 #ifdef __BIG_ENDIAN_BITFIELD
0058     /* Start of block referenced by assembly code - do not change! */
0059     uint32_t desc_version;
0060     uint32_t desc_size;
0061     uint64_t stack_top;
0062     uint64_t heap_base;
0063     uint64_t heap_end;
0064     /* Only used by bootloader */
0065     uint64_t entry_point;
0066     uint64_t desc_vaddr;
0067     /* End of This block referenced by assembly code - do not change! */
0068     uint32_t exception_base_addr;
0069     uint32_t stack_size;
0070     uint32_t heap_size;
0071     /* Argc count for application. */
0072     uint32_t argc;
0073     uint32_t argv[OCTEON_ARGV_MAX_ARGS];
0074
0075 #define  BOOT_FLAG_INIT_CORE        (1 << 0)
0076 #define  OCTEON_BL_FLAG_DEBUG       (1 << 1)
0077 #define  OCTEON_BL_FLAG_NO_MAGIC    (1 << 2)
0078     /* If set, use uart1 for console */
0079 #define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
0080     /* If set, use PCI console */
0081 #define  OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
0082     /* Call exit on break on serial port */
0083 #define  OCTEON_BL_FLAG_BREAK       (1 << 5)
0084
0085     uint32_t flags;
0086     uint32_t core_mask;
0087     /* DRAM size in megabyes. */
0088     uint32_t dram_size;
0089     /* physical address of free memory descriptor block. */
0090     uint32_t phy_mem_desc_addr;
0091     /* used to pass flags from app to debugger. */
0092     uint32_t debugger_flags_base_addr;
0093     /* CPU clock speed, in hz. */
0094     uint32_t eclock_hz;
0095     /* DRAM clock speed, in hz. */
0096     uint32_t dclock_hz;
0097     /* SPI4 clock in hz. */
0098     uint32_t spi_clock_hz;
0099     uint16_t board_type;
0100     uint8_t board_rev_major;
0101     uint8_t board_rev_minor;
0102     uint16_t chip_type;
0103     uint8_t chip_rev_major;
0104     uint8_t chip_rev_minor;
0105     char board_serial_number[OCTEON_SERIAL_LEN];
0106     uint8_t mac_addr_base[6];
0107     uint8_t mac_addr_count;
0108     uint64_t cvmx_desc_vaddr;
0109 #else
0110     uint32_t desc_size;
0111     uint32_t desc_version;
0112     uint64_t stack_top;
0113     uint64_t heap_base;
0114     uint64_t heap_end;
0115     /* Only used by bootloader */
0116     uint64_t entry_point;
0117     uint64_t desc_vaddr;
0118     /* End of This block referenced by assembly code - do not change! */
0119     uint32_t stack_size;
0120     uint32_t exception_base_addr;
0121     uint32_t argc;
0122     uint32_t heap_size;
0123     /*
0124      * Argc count for application.
0125      * Warning low bit scrambled in little-endian.
0126      */
0127     uint32_t argv[OCTEON_ARGV_MAX_ARGS];
0128
0129 #define  BOOT_FLAG_INIT_CORE        (1 << 0)
0130 #define  OCTEON_BL_FLAG_DEBUG       (1 << 1)
0131 #define  OCTEON_BL_FLAG_NO_MAGIC    (1 << 2)
0132     /* If set, use uart1 for console */
0133 #define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
0134     /* If set, use PCI console */
0135 #define  OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
0136     /* Call exit on break on serial port */
0137 #define  OCTEON_BL_FLAG_BREAK       (1 << 5)
0138
0139     uint32_t core_mask;
0140     uint32_t flags;
0141     /* physical address of free memory descriptor block. */
0142     uint32_t phy_mem_desc_addr;
0143     /* DRAM size in megabyes. */
0144     uint32_t dram_size;
0145     /* CPU clock speed, in hz. */
0146     uint32_t eclock_hz;
0147     /* used to pass flags from app to debugger. */
0148     uint32_t debugger_flags_base_addr;
0149     /* SPI4 clock in hz. */
0150     uint32_t spi_clock_hz;
0151     /* DRAM clock speed, in hz. */
0152     uint32_t dclock_hz;
0153     uint8_t chip_rev_minor;
0154     uint8_t chip_rev_major;
0155     uint16_t chip_type;
0156     uint8_t board_rev_minor;
0157     uint8_t board_rev_major;
0158     uint16_t board_type;
0159
0160     uint64_t unused1[4]; /* Not even filled in by bootloader. */
0161
0162     uint64_t cvmx_desc_vaddr;
0163 #endif
0164 };
0165
0166 union octeon_cvmemctl {
0167     uint64_t u64;
0168     struct {
0169         /* RO 1 = BIST fail, 0 = BIST pass */
0170         __BITFIELD_FIELD(uint64_t tlbbist:1,
0171         /* RO 1 = BIST fail, 0 = BIST pass */
0172         __BITFIELD_FIELD(uint64_t l1cbist:1,
0173         /* RO 1 = BIST fail, 0 = BIST pass */
0174         __BITFIELD_FIELD(uint64_t l1dbist:1,
0175         /* RO 1 = BIST fail, 0 = BIST pass */
0176         __BITFIELD_FIELD(uint64_t dcmbist:1,
0177         /* RO 1 = BIST fail, 0 = BIST pass */
0178         __BITFIELD_FIELD(uint64_t ptgbist:1,
0179         /* RO 1 = BIST fail, 0 = BIST pass */
0180         __BITFIELD_FIELD(uint64_t wbfbist:1,
0181         /* Reserved */
0182         __BITFIELD_FIELD(uint64_t reserved:17,
0183         /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
0184          * This field selects between the TLB replacement policies:
0185          * bitmask LRU or NLU. Bitmask LRU maintains a mask of
0186          * recently used TLB entries and avoids them as new entries
0187          * are allocated. NLU simply guarantees that the next
0188          * allocation is not the last used TLB entry. */
0189         __BITFIELD_FIELD(uint64_t tlbnlu:1,
0190         /* OCTEON II - Selects the bit in the counter used for
0191          * releasing a PAUSE. This counter trips every 2(8+PAUSETIME)
0192          * cycles. If not already released, the cnMIPS II core will
0193          * always release a given PAUSE instruction within
0194          * 2(8+PAUSETIME). If the counter trip happens to line up,
0195          * the cnMIPS II core may release the PAUSE instantly. */
0196         __BITFIELD_FIELD(uint64_t pausetime:3,
0197         /* OCTEON II - This field is an extension of
0198          * CvmMemCtl[DIDTTO] */
0199         __BITFIELD_FIELD(uint64_t didtto2:1,
0200         /* R/W If set, marked write-buffer entries time out
0201          * the same as other entries; if clear, marked
0202          * write-buffer entries use the maximum timeout. */
0203         __BITFIELD_FIELD(uint64_t dismarkwblongto:1,
0204         /* R/W If set, a merged store does not clear the
0205          * write-buffer entry timeout state. */
0206         __BITFIELD_FIELD(uint64_t dismrgclrwbto:1,
0207         /* R/W Two bits that are the MSBs of the resultant
0208          * CVMSEG LM word location for an IOBDMA. The other 8
0209          * bits come from the SCRADDR field of the IOBDMA. */
0210         __BITFIELD_FIELD(uint64_t iobdmascrmsb:2,
0211         /* R/W If set, SYNCWS and SYNCS only order marked
0212          * stores; if clear, SYNCWS and SYNCS only order
0213          * unmarked stores. SYNCWSMARKED has no effect when
0214          * DISSYNCWS is set. */
0215         __BITFIELD_FIELD(uint64_t syncwsmarked:1,
0216         /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
0217          * SYNC. */
0218         __BITFIELD_FIELD(uint64_t dissyncws:1,
0219         /* R/W If set, no stall happens on write buffer
0220          * full. */
0221         __BITFIELD_FIELD(uint64_t diswbfst:1,
0222         /* R/W If set (and SX set), supervisor-level
0223          * loads/stores can use XKPHYS addresses with
0224          * VA<48>==0 */
0225         __BITFIELD_FIELD(uint64_t xkmemenas:1,
0226         /* R/W If set (and UX set), user-level loads/stores
0227          * can use XKPHYS addresses with VA<48>==0 */
0228         __BITFIELD_FIELD(uint64_t xkmemenau:1,
0229         /* R/W If set (and SX set), supervisor-level
0230          * loads/stores can use XKPHYS addresses with
0231          * VA<48>==1 */
0232         __BITFIELD_FIELD(uint64_t xkioenas:1,
0233         /* R/W If set (and UX set), user-level loads/stores
0234          * can use XKPHYS addresses with VA<48>==1 */
0235         __BITFIELD_FIELD(uint64_t xkioenau:1,
0236         /* R/W If set, all stores act as SYNCW (NOMERGE must
0237          * be set when this is set) RW, reset to 0. */
0238         __BITFIELD_FIELD(uint64_t allsyncw:1,
0239         /* R/W If set, no stores merge, and all stores reach
0240          * the coherent bus in order. */
0241         __BITFIELD_FIELD(uint64_t nomerge:1,
0242         /* R/W Selects the bit in the counter used for DID
0243          * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
0244          * 214. Actual time-out is between 1x and 2x this
0245          * interval. For example, with DIDTTO=3, expiration
0246          * interval is between 16K and 32K. */
0247         __BITFIELD_FIELD(uint64_t didtto:2,
0248         /* R/W If set, the (mem) CSR clock never turns off. */
0249         __BITFIELD_FIELD(uint64_t csrckalwys:1,
0250         /* R/W If set, mclk never turns off. */
0251         __BITFIELD_FIELD(uint64_t mclkalwys:1,
0252         /* R/W Selects the bit in the counter used for write
0253          * buffer flush time-outs (WBFLT+11) is the bit
0254          * position in an internal counter used to determine
0255          * expiration. The write buffer expires between 1x and
0256          * 2x this interval. For example, with WBFLT = 0, a
0257          * write buffer expires between 2K and 4K cycles after
0258          * the write buffer entry is allocated. */
0259         __BITFIELD_FIELD(uint64_t wbfltime:3,
0260         /* R/W If set, do not put Istream in the L2 cache. */
0261         __BITFIELD_FIELD(uint64_t istrnol2:1,
0262         /* R/W The write buffer threshold. */
0263         __BITFIELD_FIELD(uint64_t wbthresh:4,
0264         /* Reserved */
0265         __BITFIELD_FIELD(uint64_t reserved2:2,
0266         /* R/W If set, CVMSEG is available for loads/stores in
0267          * kernel/debug mode. */
0268         __BITFIELD_FIELD(uint64_t cvmsegenak:1,
0269         /* R/W If set, CVMSEG is available for loads/stores in
0270          * supervisor mode. */
0271         __BITFIELD_FIELD(uint64_t cvmsegenas:1,
0272         /* R/W If set, CVMSEG is available for loads/stores in
0273          * user mode. */
0274         __BITFIELD_FIELD(uint64_t cvmsegenau:1,
0275         /* R/W Size of local memory in cache blocks, 54 (6912
0276          * bytes) is max legal value. */
0277         __BITFIELD_FIELD(uint64_t lmemsz:6,
0278         ;)))))))))))))))))))))))))))))))))
0279     } s;
0280 };
0281
0282 extern void octeon_check_cpu_bist(void);
0283
0284 int octeon_prune_device_tree(void);
0285 extern const char __dtb_octeon_3xxx_begin;
0286 extern const char __dtb_octeon_68xx_begin;
0287
0288 /**
0289  * Write a 32bit value to the Octeon NPI register space
0290  *
0291  * @address: Address to write to
0292  * @val:     Value to write
0293  */
0294 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
0295 {
0296     cvmx_write64_uint32(address ^ 4, val);
0297     cvmx_read64_uint32(address ^ 4);
0298 }
0299
0300 #ifdef CONFIG_SMP
0301 void octeon_setup_smp(void);
0302 #else
0303 static inline void octeon_setup_smp(void) {}
0304 #endif
0305
0306 struct irq_domain;
0307 struct device_node;
0308 struct irq_data;
0309 struct irq_chip;
0310 void octeon_ciu3_mbox_send(int cpu, unsigned int mbox);
0311 int octeon_irq_ciu3_xlat(struct irq_domain *d,
0312              struct device_node *node,
0313              const u32 *intspec,
0314              unsigned int intsize,
0315              unsigned long *out_hwirq,
0316              unsigned int *out_type);
0317 void octeon_irq_ciu3_enable(struct irq_data *data);
0318 void octeon_irq_ciu3_disable(struct irq_data *data);
0319 void octeon_irq_ciu3_ack(struct irq_data *data);
0320 void octeon_irq_ciu3_mask(struct irq_data *data);
0321 void octeon_irq_ciu3_mask_ack(struct irq_data *data);
0322 int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
0323              irq_hw_number_t hw, struct irq_chip *chip);
0324
0325 /* Octeon multiplier save/restore routines from octeon_switch.S */
0326 void octeon_mult_save(void);
0327 void octeon_mult_restore(void);
0328 void octeon_mult_save_end(void);
0329 void octeon_mult_restore_end(void);
0330 void octeon_mult_save3(void);
0331 void octeon_mult_save3_end(void);
0332 void octeon_mult_save2(void);
0333 void octeon_mult_save2_end(void);
0334 void octeon_mult_restore3(void);
0335 void octeon_mult_restore3_end(void);
0336 void octeon_mult_restore2(void);
0337 void octeon_mult_restore2_end(void);
0338
0339 /**
0340  * Read a 32bit value from the Octeon NPI register space
0341  *
0342  * @address: Address to read
0343  * Returns The result
0344  */
0345 static inline uint32_t octeon_npi_read32(uint64_t address)
0346 {
0347     return cvmx_read64_uint32(address ^ 4);
0348 }
0349
0350 extern struct cvmx_bootinfo *octeon_bootinfo;
0351
0352 extern uint64_t octeon_bootloader_entry_addr;
0353
0354 extern void (*octeon_irq_setup_secondary)(void);
0355
0356 typedef void (*octeon_irq_ip4_handler_t)(void);
0357 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
0358
0359 extern void octeon_fixup_irqs(void);
0360
0361 extern struct semaphore octeon_bootbus_sem;
0362
0363 struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);
0364
0365 #endif /* __ASM_OCTEON_OCTEON_H */