asm/octeon/cvmx-uctlx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_UCTLX_DEFS_H__
0029 #define __CVMX_UCTLX_DEFS_H__
0030
0031 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
0032 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
0033 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
0034 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
0035 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
0036 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
0037 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
0038 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
0039 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
0040 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
0041 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
0042 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
0043 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
0044
0045 union cvmx_uctlx_bist_status {
0046     uint64_t u64;
0047     struct cvmx_uctlx_bist_status_s {
0048 #ifdef __BIG_ENDIAN_BITFIELD
0049         uint64_t reserved_6_63:58;
0050         uint64_t data_bis:1;
0051         uint64_t desc_bis:1;
0052         uint64_t erbm_bis:1;
0053         uint64_t orbm_bis:1;
0054         uint64_t wrbm_bis:1;
0055         uint64_t ppaf_bis:1;
0056 #else
0057         uint64_t ppaf_bis:1;
0058         uint64_t wrbm_bis:1;
0059         uint64_t orbm_bis:1;
0060         uint64_t erbm_bis:1;
0061         uint64_t desc_bis:1;
0062         uint64_t data_bis:1;
0063         uint64_t reserved_6_63:58;
0064 #endif
0065     } s;
0066 };
0067
0068 union cvmx_uctlx_clk_rst_ctl {
0069     uint64_t u64;
0070     struct cvmx_uctlx_clk_rst_ctl_s {
0071 #ifdef __BIG_ENDIAN_BITFIELD
0072         uint64_t reserved_25_63:39;
0073         uint64_t clear_bist:1;
0074         uint64_t start_bist:1;
0075         uint64_t ehci_sm:1;
0076         uint64_t ohci_clkcktrst:1;
0077         uint64_t ohci_sm:1;
0078         uint64_t ohci_susp_lgcy:1;
0079         uint64_t app_start_clk:1;
0080         uint64_t o_clkdiv_rst:1;
0081         uint64_t h_clkdiv_byp:1;
0082         uint64_t h_clkdiv_rst:1;
0083         uint64_t h_clkdiv_en:1;
0084         uint64_t o_clkdiv_en:1;
0085         uint64_t h_div:4;
0086         uint64_t p_refclk_sel:2;
0087         uint64_t p_refclk_div:2;
0088         uint64_t reserved_4_4:1;
0089         uint64_t p_com_on:1;
0090         uint64_t p_por:1;
0091         uint64_t p_prst:1;
0092         uint64_t hrst:1;
0093 #else
0094         uint64_t hrst:1;
0095         uint64_t p_prst:1;
0096         uint64_t p_por:1;
0097         uint64_t p_com_on:1;
0098         uint64_t reserved_4_4:1;
0099         uint64_t p_refclk_div:2;
0100         uint64_t p_refclk_sel:2;
0101         uint64_t h_div:4;
0102         uint64_t o_clkdiv_en:1;
0103         uint64_t h_clkdiv_en:1;
0104         uint64_t h_clkdiv_rst:1;
0105         uint64_t h_clkdiv_byp:1;
0106         uint64_t o_clkdiv_rst:1;
0107         uint64_t app_start_clk:1;
0108         uint64_t ohci_susp_lgcy:1;
0109         uint64_t ohci_sm:1;
0110         uint64_t ohci_clkcktrst:1;
0111         uint64_t ehci_sm:1;
0112         uint64_t start_bist:1;
0113         uint64_t clear_bist:1;
0114         uint64_t reserved_25_63:39;
0115 #endif
0116     } s;
0117 };
0118
0119 union cvmx_uctlx_ehci_ctl {
0120     uint64_t u64;
0121     struct cvmx_uctlx_ehci_ctl_s {
0122 #ifdef __BIG_ENDIAN_BITFIELD
0123         uint64_t reserved_20_63:44;
0124         uint64_t desc_rbm:1;
0125         uint64_t reg_nb:1;
0126         uint64_t l2c_dc:1;
0127         uint64_t l2c_bc:1;
0128         uint64_t l2c_0pag:1;
0129         uint64_t l2c_stt:1;
0130         uint64_t l2c_buff_emod:2;
0131         uint64_t l2c_desc_emod:2;
0132         uint64_t inv_reg_a2:1;
0133         uint64_t ehci_64b_addr_en:1;
0134         uint64_t l2c_addr_msb:8;
0135 #else
0136         uint64_t l2c_addr_msb:8;
0137         uint64_t ehci_64b_addr_en:1;
0138         uint64_t inv_reg_a2:1;
0139         uint64_t l2c_desc_emod:2;
0140         uint64_t l2c_buff_emod:2;
0141         uint64_t l2c_stt:1;
0142         uint64_t l2c_0pag:1;
0143         uint64_t l2c_bc:1;
0144         uint64_t l2c_dc:1;
0145         uint64_t reg_nb:1;
0146         uint64_t desc_rbm:1;
0147         uint64_t reserved_20_63:44;
0148 #endif
0149     } s;
0150 };
0151
0152 union cvmx_uctlx_ehci_fla {
0153     uint64_t u64;
0154     struct cvmx_uctlx_ehci_fla_s {
0155 #ifdef __BIG_ENDIAN_BITFIELD
0156         uint64_t reserved_6_63:58;
0157         uint64_t fla:6;
0158 #else
0159         uint64_t fla:6;
0160         uint64_t reserved_6_63:58;
0161 #endif
0162     } s;
0163 };
0164
0165 union cvmx_uctlx_erto_ctl {
0166     uint64_t u64;
0167     struct cvmx_uctlx_erto_ctl_s {
0168 #ifdef __BIG_ENDIAN_BITFIELD
0169         uint64_t reserved_32_63:32;
0170         uint64_t to_val:27;
0171         uint64_t reserved_0_4:5;
0172 #else
0173         uint64_t reserved_0_4:5;
0174         uint64_t to_val:27;
0175         uint64_t reserved_32_63:32;
0176 #endif
0177     } s;
0178 };
0179
0180 union cvmx_uctlx_if_ena {
0181     uint64_t u64;
0182     struct cvmx_uctlx_if_ena_s {
0183 #ifdef __BIG_ENDIAN_BITFIELD
0184         uint64_t reserved_1_63:63;
0185         uint64_t en:1;
0186 #else
0187         uint64_t en:1;
0188         uint64_t reserved_1_63:63;
0189 #endif
0190     } s;
0191 };
0192
0193 union cvmx_uctlx_int_ena {
0194     uint64_t u64;
0195     struct cvmx_uctlx_int_ena_s {
0196 #ifdef __BIG_ENDIAN_BITFIELD
0197         uint64_t reserved_8_63:56;
0198         uint64_t ec_ovf_e:1;
0199         uint64_t oc_ovf_e:1;
0200         uint64_t wb_pop_e:1;
0201         uint64_t wb_psh_f:1;
0202         uint64_t cf_psh_f:1;
0203         uint64_t or_psh_f:1;
0204         uint64_t er_psh_f:1;
0205         uint64_t pp_psh_f:1;
0206 #else
0207         uint64_t pp_psh_f:1;
0208         uint64_t er_psh_f:1;
0209         uint64_t or_psh_f:1;
0210         uint64_t cf_psh_f:1;
0211         uint64_t wb_psh_f:1;
0212         uint64_t wb_pop_e:1;
0213         uint64_t oc_ovf_e:1;
0214         uint64_t ec_ovf_e:1;
0215         uint64_t reserved_8_63:56;
0216 #endif
0217     } s;
0218 };
0219
0220 union cvmx_uctlx_int_reg {
0221     uint64_t u64;
0222     struct cvmx_uctlx_int_reg_s {
0223 #ifdef __BIG_ENDIAN_BITFIELD
0224         uint64_t reserved_8_63:56;
0225         uint64_t ec_ovf_e:1;
0226         uint64_t oc_ovf_e:1;
0227         uint64_t wb_pop_e:1;
0228         uint64_t wb_psh_f:1;
0229         uint64_t cf_psh_f:1;
0230         uint64_t or_psh_f:1;
0231         uint64_t er_psh_f:1;
0232         uint64_t pp_psh_f:1;
0233 #else
0234         uint64_t pp_psh_f:1;
0235         uint64_t er_psh_f:1;
0236         uint64_t or_psh_f:1;
0237         uint64_t cf_psh_f:1;
0238         uint64_t wb_psh_f:1;
0239         uint64_t wb_pop_e:1;
0240         uint64_t oc_ovf_e:1;
0241         uint64_t ec_ovf_e:1;
0242         uint64_t reserved_8_63:56;
0243 #endif
0244     } s;
0245 };
0246
0247 union cvmx_uctlx_ohci_ctl {
0248     uint64_t u64;
0249     struct cvmx_uctlx_ohci_ctl_s {
0250 #ifdef __BIG_ENDIAN_BITFIELD
0251         uint64_t reserved_19_63:45;
0252         uint64_t reg_nb:1;
0253         uint64_t l2c_dc:1;
0254         uint64_t l2c_bc:1;
0255         uint64_t l2c_0pag:1;
0256         uint64_t l2c_stt:1;
0257         uint64_t l2c_buff_emod:2;
0258         uint64_t l2c_desc_emod:2;
0259         uint64_t inv_reg_a2:1;
0260         uint64_t reserved_8_8:1;
0261         uint64_t l2c_addr_msb:8;
0262 #else
0263         uint64_t l2c_addr_msb:8;
0264         uint64_t reserved_8_8:1;
0265         uint64_t inv_reg_a2:1;
0266         uint64_t l2c_desc_emod:2;
0267         uint64_t l2c_buff_emod:2;
0268         uint64_t l2c_stt:1;
0269         uint64_t l2c_0pag:1;
0270         uint64_t l2c_bc:1;
0271         uint64_t l2c_dc:1;
0272         uint64_t reg_nb:1;
0273         uint64_t reserved_19_63:45;
0274 #endif
0275     } s;
0276 };
0277
0278 union cvmx_uctlx_orto_ctl {
0279     uint64_t u64;
0280     struct cvmx_uctlx_orto_ctl_s {
0281 #ifdef __BIG_ENDIAN_BITFIELD
0282         uint64_t reserved_32_63:32;
0283         uint64_t to_val:24;
0284         uint64_t reserved_0_7:8;
0285 #else
0286         uint64_t reserved_0_7:8;
0287         uint64_t to_val:24;
0288         uint64_t reserved_32_63:32;
0289 #endif
0290     } s;
0291 };
0292
0293 union cvmx_uctlx_ppaf_wm {
0294     uint64_t u64;
0295     struct cvmx_uctlx_ppaf_wm_s {
0296 #ifdef __BIG_ENDIAN_BITFIELD
0297         uint64_t reserved_5_63:59;
0298         uint64_t wm:5;
0299 #else
0300         uint64_t wm:5;
0301         uint64_t reserved_5_63:59;
0302 #endif
0303     } s;
0304 };
0305
0306 union cvmx_uctlx_uphy_ctl_status {
0307     uint64_t u64;
0308     struct cvmx_uctlx_uphy_ctl_status_s {
0309 #ifdef __BIG_ENDIAN_BITFIELD
0310         uint64_t reserved_10_63:54;
0311         uint64_t bist_done:1;
0312         uint64_t bist_err:1;
0313         uint64_t hsbist:1;
0314         uint64_t fsbist:1;
0315         uint64_t lsbist:1;
0316         uint64_t siddq:1;
0317         uint64_t vtest_en:1;
0318         uint64_t uphy_bist:1;
0319         uint64_t bist_en:1;
0320         uint64_t ate_reset:1;
0321 #else
0322         uint64_t ate_reset:1;
0323         uint64_t bist_en:1;
0324         uint64_t uphy_bist:1;
0325         uint64_t vtest_en:1;
0326         uint64_t siddq:1;
0327         uint64_t lsbist:1;
0328         uint64_t fsbist:1;
0329         uint64_t hsbist:1;
0330         uint64_t bist_err:1;
0331         uint64_t bist_done:1;
0332         uint64_t reserved_10_63:54;
0333 #endif
0334     } s;
0335 };
0336
0337 union cvmx_uctlx_uphy_portx_ctl_status {
0338     uint64_t u64;
0339     struct cvmx_uctlx_uphy_portx_ctl_status_s {
0340 #ifdef __BIG_ENDIAN_BITFIELD
0341         uint64_t reserved_43_63:21;
0342         uint64_t tdata_out:4;
0343         uint64_t txbiststuffenh:1;
0344         uint64_t txbiststuffen:1;
0345         uint64_t dmpulldown:1;
0346         uint64_t dppulldown:1;
0347         uint64_t vbusvldext:1;
0348         uint64_t portreset:1;
0349         uint64_t txhsvxtune:2;
0350         uint64_t txvreftune:4;
0351         uint64_t txrisetune:1;
0352         uint64_t txpreemphasistune:1;
0353         uint64_t txfslstune:4;
0354         uint64_t sqrxtune:3;
0355         uint64_t compdistune:3;
0356         uint64_t loop_en:1;
0357         uint64_t tclk:1;
0358         uint64_t tdata_sel:1;
0359         uint64_t taddr_in:4;
0360         uint64_t tdata_in:8;
0361 #else
0362         uint64_t tdata_in:8;
0363         uint64_t taddr_in:4;
0364         uint64_t tdata_sel:1;
0365         uint64_t tclk:1;
0366         uint64_t loop_en:1;
0367         uint64_t compdistune:3;
0368         uint64_t sqrxtune:3;
0369         uint64_t txfslstune:4;
0370         uint64_t txpreemphasistune:1;
0371         uint64_t txrisetune:1;
0372         uint64_t txvreftune:4;
0373         uint64_t txhsvxtune:2;
0374         uint64_t portreset:1;
0375         uint64_t vbusvldext:1;
0376         uint64_t dppulldown:1;
0377         uint64_t dmpulldown:1;
0378         uint64_t txbiststuffen:1;
0379         uint64_t txbiststuffenh:1;
0380         uint64_t tdata_out:4;
0381         uint64_t reserved_43_63:21;
0382 #endif
0383     } s;
0384 };
0385
0386 #endif