asm/octeon/cvmx-stxx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_STXX_DEFS_H__
0029 #define __CVMX_STXX_DEFS_H__
0030
0031 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
0032 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
0033 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
0034 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
0035 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
0036 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
0037 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
0038 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
0039 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
0040 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
0041 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
0042 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
0043 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
0044 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
0045 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
0046 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
0047
0048 void __cvmx_interrupt_stxx_int_msk_enable(int index);
0049
0050 union cvmx_stxx_arb_ctl {
0051     uint64_t u64;
0052     struct cvmx_stxx_arb_ctl_s {
0053 #ifdef __BIG_ENDIAN_BITFIELD
0054         uint64_t reserved_6_63:58;
0055         uint64_t mintrn:1;
0056         uint64_t reserved_4_4:1;
0057         uint64_t igntpa:1;
0058         uint64_t reserved_0_2:3;
0059 #else
0060         uint64_t reserved_0_2:3;
0061         uint64_t igntpa:1;
0062         uint64_t reserved_4_4:1;
0063         uint64_t mintrn:1;
0064         uint64_t reserved_6_63:58;
0065 #endif
0066     } s;
0067 };
0068
0069 union cvmx_stxx_bckprs_cnt {
0070     uint64_t u64;
0071     struct cvmx_stxx_bckprs_cnt_s {
0072 #ifdef __BIG_ENDIAN_BITFIELD
0073         uint64_t reserved_32_63:32;
0074         uint64_t cnt:32;
0075 #else
0076         uint64_t cnt:32;
0077         uint64_t reserved_32_63:32;
0078 #endif
0079     } s;
0080 };
0081
0082 union cvmx_stxx_com_ctl {
0083     uint64_t u64;
0084     struct cvmx_stxx_com_ctl_s {
0085 #ifdef __BIG_ENDIAN_BITFIELD
0086         uint64_t reserved_4_63:60;
0087         uint64_t st_en:1;
0088         uint64_t reserved_1_2:2;
0089         uint64_t inf_en:1;
0090 #else
0091         uint64_t inf_en:1;
0092         uint64_t reserved_1_2:2;
0093         uint64_t st_en:1;
0094         uint64_t reserved_4_63:60;
0095 #endif
0096     } s;
0097 };
0098
0099 union cvmx_stxx_dip_cnt {
0100     uint64_t u64;
0101     struct cvmx_stxx_dip_cnt_s {
0102 #ifdef __BIG_ENDIAN_BITFIELD
0103         uint64_t reserved_8_63:56;
0104         uint64_t frmmax:4;
0105         uint64_t dipmax:4;
0106 #else
0107         uint64_t dipmax:4;
0108         uint64_t frmmax:4;
0109         uint64_t reserved_8_63:56;
0110 #endif
0111     } s;
0112 };
0113
0114 union cvmx_stxx_ign_cal {
0115     uint64_t u64;
0116     struct cvmx_stxx_ign_cal_s {
0117 #ifdef __BIG_ENDIAN_BITFIELD
0118         uint64_t reserved_16_63:48;
0119         uint64_t igntpa:16;
0120 #else
0121         uint64_t igntpa:16;
0122         uint64_t reserved_16_63:48;
0123 #endif
0124     } s;
0125 };
0126
0127 union cvmx_stxx_int_msk {
0128     uint64_t u64;
0129     struct cvmx_stxx_int_msk_s {
0130 #ifdef __BIG_ENDIAN_BITFIELD
0131         uint64_t reserved_8_63:56;
0132         uint64_t frmerr:1;
0133         uint64_t unxfrm:1;
0134         uint64_t nosync:1;
0135         uint64_t diperr:1;
0136         uint64_t datovr:1;
0137         uint64_t ovrbst:1;
0138         uint64_t calpar1:1;
0139         uint64_t calpar0:1;
0140 #else
0141         uint64_t calpar0:1;
0142         uint64_t calpar1:1;
0143         uint64_t ovrbst:1;
0144         uint64_t datovr:1;
0145         uint64_t diperr:1;
0146         uint64_t nosync:1;
0147         uint64_t unxfrm:1;
0148         uint64_t frmerr:1;
0149         uint64_t reserved_8_63:56;
0150 #endif
0151     } s;
0152 };
0153
0154 union cvmx_stxx_int_reg {
0155     uint64_t u64;
0156     struct cvmx_stxx_int_reg_s {
0157 #ifdef __BIG_ENDIAN_BITFIELD
0158         uint64_t reserved_9_63:55;
0159         uint64_t syncerr:1;
0160         uint64_t frmerr:1;
0161         uint64_t unxfrm:1;
0162         uint64_t nosync:1;
0163         uint64_t diperr:1;
0164         uint64_t datovr:1;
0165         uint64_t ovrbst:1;
0166         uint64_t calpar1:1;
0167         uint64_t calpar0:1;
0168 #else
0169         uint64_t calpar0:1;
0170         uint64_t calpar1:1;
0171         uint64_t ovrbst:1;
0172         uint64_t datovr:1;
0173         uint64_t diperr:1;
0174         uint64_t nosync:1;
0175         uint64_t unxfrm:1;
0176         uint64_t frmerr:1;
0177         uint64_t syncerr:1;
0178         uint64_t reserved_9_63:55;
0179 #endif
0180     } s;
0181 };
0182
0183 union cvmx_stxx_int_sync {
0184     uint64_t u64;
0185     struct cvmx_stxx_int_sync_s {
0186 #ifdef __BIG_ENDIAN_BITFIELD
0187         uint64_t reserved_8_63:56;
0188         uint64_t frmerr:1;
0189         uint64_t unxfrm:1;
0190         uint64_t nosync:1;
0191         uint64_t diperr:1;
0192         uint64_t datovr:1;
0193         uint64_t ovrbst:1;
0194         uint64_t calpar1:1;
0195         uint64_t calpar0:1;
0196 #else
0197         uint64_t calpar0:1;
0198         uint64_t calpar1:1;
0199         uint64_t ovrbst:1;
0200         uint64_t datovr:1;
0201         uint64_t diperr:1;
0202         uint64_t nosync:1;
0203         uint64_t unxfrm:1;
0204         uint64_t frmerr:1;
0205         uint64_t reserved_8_63:56;
0206 #endif
0207     } s;
0208 };
0209
0210 union cvmx_stxx_min_bst {
0211     uint64_t u64;
0212     struct cvmx_stxx_min_bst_s {
0213 #ifdef __BIG_ENDIAN_BITFIELD
0214         uint64_t reserved_9_63:55;
0215         uint64_t minb:9;
0216 #else
0217         uint64_t minb:9;
0218         uint64_t reserved_9_63:55;
0219 #endif
0220     } s;
0221 };
0222
0223 union cvmx_stxx_spi4_calx {
0224     uint64_t u64;
0225     struct cvmx_stxx_spi4_calx_s {
0226 #ifdef __BIG_ENDIAN_BITFIELD
0227         uint64_t reserved_17_63:47;
0228         uint64_t oddpar:1;
0229         uint64_t prt3:4;
0230         uint64_t prt2:4;
0231         uint64_t prt1:4;
0232         uint64_t prt0:4;
0233 #else
0234         uint64_t prt0:4;
0235         uint64_t prt1:4;
0236         uint64_t prt2:4;
0237         uint64_t prt3:4;
0238         uint64_t oddpar:1;
0239         uint64_t reserved_17_63:47;
0240 #endif
0241     } s;
0242 };
0243
0244 union cvmx_stxx_spi4_dat {
0245     uint64_t u64;
0246     struct cvmx_stxx_spi4_dat_s {
0247 #ifdef __BIG_ENDIAN_BITFIELD
0248         uint64_t reserved_32_63:32;
0249         uint64_t alpha:16;
0250         uint64_t max_t:16;
0251 #else
0252         uint64_t max_t:16;
0253         uint64_t alpha:16;
0254         uint64_t reserved_32_63:32;
0255 #endif
0256     } s;
0257 };
0258
0259 union cvmx_stxx_spi4_stat {
0260     uint64_t u64;
0261     struct cvmx_stxx_spi4_stat_s {
0262 #ifdef __BIG_ENDIAN_BITFIELD
0263         uint64_t reserved_16_63:48;
0264         uint64_t m:8;
0265         uint64_t reserved_7_7:1;
0266         uint64_t len:7;
0267 #else
0268         uint64_t len:7;
0269         uint64_t reserved_7_7:1;
0270         uint64_t m:8;
0271         uint64_t reserved_16_63:48;
0272 #endif
0273     } s;
0274 };
0275
0276 union cvmx_stxx_stat_bytes_hi {
0277     uint64_t u64;
0278     struct cvmx_stxx_stat_bytes_hi_s {
0279 #ifdef __BIG_ENDIAN_BITFIELD
0280         uint64_t reserved_32_63:32;
0281         uint64_t cnt:32;
0282 #else
0283         uint64_t cnt:32;
0284         uint64_t reserved_32_63:32;
0285 #endif
0286     } s;
0287 };
0288
0289 union cvmx_stxx_stat_bytes_lo {
0290     uint64_t u64;
0291     struct cvmx_stxx_stat_bytes_lo_s {
0292 #ifdef __BIG_ENDIAN_BITFIELD
0293         uint64_t reserved_32_63:32;
0294         uint64_t cnt:32;
0295 #else
0296         uint64_t cnt:32;
0297         uint64_t reserved_32_63:32;
0298 #endif
0299     } s;
0300 };
0301
0302 union cvmx_stxx_stat_ctl {
0303     uint64_t u64;
0304     struct cvmx_stxx_stat_ctl_s {
0305 #ifdef __BIG_ENDIAN_BITFIELD
0306         uint64_t reserved_5_63:59;
0307         uint64_t clr:1;
0308         uint64_t bckprs:4;
0309 #else
0310         uint64_t bckprs:4;
0311         uint64_t clr:1;
0312         uint64_t reserved_5_63:59;
0313 #endif
0314     } s;
0315 };
0316
0317 union cvmx_stxx_stat_pkt_xmt {
0318     uint64_t u64;
0319     struct cvmx_stxx_stat_pkt_xmt_s {
0320 #ifdef __BIG_ENDIAN_BITFIELD
0321         uint64_t reserved_32_63:32;
0322         uint64_t cnt:32;
0323 #else
0324         uint64_t cnt:32;
0325         uint64_t reserved_32_63:32;
0326 #endif
0327     } s;
0328 };
0329
0330 #endif