asm/octeon/cvmx-srxx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_SRXX_DEFS_H__
0029 #define __CVMX_SRXX_DEFS_H__
0030
0031 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
0032 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
0033 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
0034 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
0035 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
0036 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
0037
0038 union cvmx_srxx_com_ctl {
0039     uint64_t u64;
0040     struct cvmx_srxx_com_ctl_s {
0041 #ifdef __BIG_ENDIAN_BITFIELD
0042         uint64_t reserved_8_63:56;
0043         uint64_t prts:4;
0044         uint64_t st_en:1;
0045         uint64_t reserved_1_2:2;
0046         uint64_t inf_en:1;
0047 #else
0048         uint64_t inf_en:1;
0049         uint64_t reserved_1_2:2;
0050         uint64_t st_en:1;
0051         uint64_t prts:4;
0052         uint64_t reserved_8_63:56;
0053 #endif
0054     } s;
0055 };
0056
0057 union cvmx_srxx_ign_rx_full {
0058     uint64_t u64;
0059     struct cvmx_srxx_ign_rx_full_s {
0060 #ifdef __BIG_ENDIAN_BITFIELD
0061         uint64_t reserved_16_63:48;
0062         uint64_t ignore:16;
0063 #else
0064         uint64_t ignore:16;
0065         uint64_t reserved_16_63:48;
0066 #endif
0067     } s;
0068 };
0069
0070 union cvmx_srxx_spi4_calx {
0071     uint64_t u64;
0072     struct cvmx_srxx_spi4_calx_s {
0073 #ifdef __BIG_ENDIAN_BITFIELD
0074         uint64_t reserved_17_63:47;
0075         uint64_t oddpar:1;
0076         uint64_t prt3:4;
0077         uint64_t prt2:4;
0078         uint64_t prt1:4;
0079         uint64_t prt0:4;
0080 #else
0081         uint64_t prt0:4;
0082         uint64_t prt1:4;
0083         uint64_t prt2:4;
0084         uint64_t prt3:4;
0085         uint64_t oddpar:1;
0086         uint64_t reserved_17_63:47;
0087 #endif
0088     } s;
0089 };
0090
0091 union cvmx_srxx_spi4_stat {
0092     uint64_t u64;
0093     struct cvmx_srxx_spi4_stat_s {
0094 #ifdef __BIG_ENDIAN_BITFIELD
0095         uint64_t reserved_16_63:48;
0096         uint64_t m:8;
0097         uint64_t reserved_7_7:1;
0098         uint64_t len:7;
0099 #else
0100         uint64_t len:7;
0101         uint64_t reserved_7_7:1;
0102         uint64_t m:8;
0103         uint64_t reserved_16_63:48;
0104 #endif
0105     } s;
0106 };
0107
0108 union cvmx_srxx_sw_tick_ctl {
0109     uint64_t u64;
0110     struct cvmx_srxx_sw_tick_ctl_s {
0111 #ifdef __BIG_ENDIAN_BITFIELD
0112         uint64_t reserved_14_63:50;
0113         uint64_t eop:1;
0114         uint64_t sop:1;
0115         uint64_t mod:4;
0116         uint64_t opc:4;
0117         uint64_t adr:4;
0118 #else
0119         uint64_t adr:4;
0120         uint64_t opc:4;
0121         uint64_t mod:4;
0122         uint64_t sop:1;
0123         uint64_t eop:1;
0124         uint64_t reserved_14_63:50;
0125 #endif
0126     } s;
0127 };
0128
0129 union cvmx_srxx_sw_tick_dat {
0130     uint64_t u64;
0131     struct cvmx_srxx_sw_tick_dat_s {
0132 #ifdef __BIG_ENDIAN_BITFIELD
0133         uint64_t dat:64;
0134 #else
0135         uint64_t dat:64;
0136 #endif
0137     } s;
0138 };
0139
0140 #endif