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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_SRIOX_DEFS_H__
0029 #define __CVMX_SRIOX_DEFS_H__
0030 
0031 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
0032 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
0033 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
0034 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
0035 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
0036 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
0037 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
0038 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
0039 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
0040 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
0041 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
0042 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
0043 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
0044 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
0045 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
0046 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
0047 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
0048 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
0049 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
0050 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
0051 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
0052 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
0053 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
0054 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
0055 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
0056 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0057 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0058 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0059 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0060 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0061 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
0062 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
0063 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
0064 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
0065 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
0066 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
0067 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
0068 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
0069 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
0070 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
0071 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
0072 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
0073 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
0074 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
0075 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
0076 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
0077 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
0078 
0079 union cvmx_sriox_acc_ctrl {
0080     uint64_t u64;
0081     struct cvmx_sriox_acc_ctrl_s {
0082 #ifdef __BIG_ENDIAN_BITFIELD
0083         uint64_t reserved_7_63:57;
0084         uint64_t deny_adr2:1;
0085         uint64_t deny_adr1:1;
0086         uint64_t deny_adr0:1;
0087         uint64_t reserved_3_3:1;
0088         uint64_t deny_bar2:1;
0089         uint64_t deny_bar1:1;
0090         uint64_t deny_bar0:1;
0091 #else
0092         uint64_t deny_bar0:1;
0093         uint64_t deny_bar1:1;
0094         uint64_t deny_bar2:1;
0095         uint64_t reserved_3_3:1;
0096         uint64_t deny_adr0:1;
0097         uint64_t deny_adr1:1;
0098         uint64_t deny_adr2:1;
0099         uint64_t reserved_7_63:57;
0100 #endif
0101     } s;
0102     struct cvmx_sriox_acc_ctrl_cn63xx {
0103 #ifdef __BIG_ENDIAN_BITFIELD
0104         uint64_t reserved_3_63:61;
0105         uint64_t deny_bar2:1;
0106         uint64_t deny_bar1:1;
0107         uint64_t deny_bar0:1;
0108 #else
0109         uint64_t deny_bar0:1;
0110         uint64_t deny_bar1:1;
0111         uint64_t deny_bar2:1;
0112         uint64_t reserved_3_63:61;
0113 #endif
0114     } cn63xx;
0115 };
0116 
0117 union cvmx_sriox_asmbly_id {
0118     uint64_t u64;
0119     struct cvmx_sriox_asmbly_id_s {
0120 #ifdef __BIG_ENDIAN_BITFIELD
0121         uint64_t reserved_32_63:32;
0122         uint64_t assy_id:16;
0123         uint64_t assy_ven:16;
0124 #else
0125         uint64_t assy_ven:16;
0126         uint64_t assy_id:16;
0127         uint64_t reserved_32_63:32;
0128 #endif
0129     } s;
0130 };
0131 
0132 union cvmx_sriox_asmbly_info {
0133     uint64_t u64;
0134     struct cvmx_sriox_asmbly_info_s {
0135 #ifdef __BIG_ENDIAN_BITFIELD
0136         uint64_t reserved_32_63:32;
0137         uint64_t assy_rev:16;
0138         uint64_t reserved_0_15:16;
0139 #else
0140         uint64_t reserved_0_15:16;
0141         uint64_t assy_rev:16;
0142         uint64_t reserved_32_63:32;
0143 #endif
0144     } s;
0145 };
0146 
0147 union cvmx_sriox_bell_resp_ctrl {
0148     uint64_t u64;
0149     struct cvmx_sriox_bell_resp_ctrl_s {
0150 #ifdef __BIG_ENDIAN_BITFIELD
0151         uint64_t reserved_6_63:58;
0152         uint64_t rp1_sid:1;
0153         uint64_t rp0_sid:2;
0154         uint64_t rp1_pid:1;
0155         uint64_t rp0_pid:2;
0156 #else
0157         uint64_t rp0_pid:2;
0158         uint64_t rp1_pid:1;
0159         uint64_t rp0_sid:2;
0160         uint64_t rp1_sid:1;
0161         uint64_t reserved_6_63:58;
0162 #endif
0163     } s;
0164 };
0165 
0166 union cvmx_sriox_bist_status {
0167     uint64_t u64;
0168     struct cvmx_sriox_bist_status_s {
0169 #ifdef __BIG_ENDIAN_BITFIELD
0170         uint64_t reserved_45_63:19;
0171         uint64_t lram:1;
0172         uint64_t mram:2;
0173         uint64_t cram:2;
0174         uint64_t bell:2;
0175         uint64_t otag:2;
0176         uint64_t itag:1;
0177         uint64_t ofree:1;
0178         uint64_t rtn:2;
0179         uint64_t obulk:4;
0180         uint64_t optrs:4;
0181         uint64_t oarb2:2;
0182         uint64_t rxbuf2:2;
0183         uint64_t oarb:2;
0184         uint64_t ispf:1;
0185         uint64_t ospf:1;
0186         uint64_t txbuf:2;
0187         uint64_t rxbuf:2;
0188         uint64_t imsg:5;
0189         uint64_t omsg:7;
0190 #else
0191         uint64_t omsg:7;
0192         uint64_t imsg:5;
0193         uint64_t rxbuf:2;
0194         uint64_t txbuf:2;
0195         uint64_t ospf:1;
0196         uint64_t ispf:1;
0197         uint64_t oarb:2;
0198         uint64_t rxbuf2:2;
0199         uint64_t oarb2:2;
0200         uint64_t optrs:4;
0201         uint64_t obulk:4;
0202         uint64_t rtn:2;
0203         uint64_t ofree:1;
0204         uint64_t itag:1;
0205         uint64_t otag:2;
0206         uint64_t bell:2;
0207         uint64_t cram:2;
0208         uint64_t mram:2;
0209         uint64_t lram:1;
0210         uint64_t reserved_45_63:19;
0211 #endif
0212     } s;
0213     struct cvmx_sriox_bist_status_cn63xx {
0214 #ifdef __BIG_ENDIAN_BITFIELD
0215         uint64_t reserved_44_63:20;
0216         uint64_t mram:2;
0217         uint64_t cram:2;
0218         uint64_t bell:2;
0219         uint64_t otag:2;
0220         uint64_t itag:1;
0221         uint64_t ofree:1;
0222         uint64_t rtn:2;
0223         uint64_t obulk:4;
0224         uint64_t optrs:4;
0225         uint64_t oarb2:2;
0226         uint64_t rxbuf2:2;
0227         uint64_t oarb:2;
0228         uint64_t ispf:1;
0229         uint64_t ospf:1;
0230         uint64_t txbuf:2;
0231         uint64_t rxbuf:2;
0232         uint64_t imsg:5;
0233         uint64_t omsg:7;
0234 #else
0235         uint64_t omsg:7;
0236         uint64_t imsg:5;
0237         uint64_t rxbuf:2;
0238         uint64_t txbuf:2;
0239         uint64_t ospf:1;
0240         uint64_t ispf:1;
0241         uint64_t oarb:2;
0242         uint64_t rxbuf2:2;
0243         uint64_t oarb2:2;
0244         uint64_t optrs:4;
0245         uint64_t obulk:4;
0246         uint64_t rtn:2;
0247         uint64_t ofree:1;
0248         uint64_t itag:1;
0249         uint64_t otag:2;
0250         uint64_t bell:2;
0251         uint64_t cram:2;
0252         uint64_t mram:2;
0253         uint64_t reserved_44_63:20;
0254 #endif
0255     } cn63xx;
0256     struct cvmx_sriox_bist_status_cn63xxp1 {
0257 #ifdef __BIG_ENDIAN_BITFIELD
0258         uint64_t reserved_44_63:20;
0259         uint64_t mram:2;
0260         uint64_t cram:2;
0261         uint64_t bell:2;
0262         uint64_t otag:2;
0263         uint64_t itag:1;
0264         uint64_t ofree:1;
0265         uint64_t rtn:2;
0266         uint64_t obulk:4;
0267         uint64_t optrs:4;
0268         uint64_t reserved_20_23:4;
0269         uint64_t oarb:2;
0270         uint64_t ispf:1;
0271         uint64_t ospf:1;
0272         uint64_t txbuf:2;
0273         uint64_t rxbuf:2;
0274         uint64_t imsg:5;
0275         uint64_t omsg:7;
0276 #else
0277         uint64_t omsg:7;
0278         uint64_t imsg:5;
0279         uint64_t rxbuf:2;
0280         uint64_t txbuf:2;
0281         uint64_t ospf:1;
0282         uint64_t ispf:1;
0283         uint64_t oarb:2;
0284         uint64_t reserved_20_23:4;
0285         uint64_t optrs:4;
0286         uint64_t obulk:4;
0287         uint64_t rtn:2;
0288         uint64_t ofree:1;
0289         uint64_t itag:1;
0290         uint64_t otag:2;
0291         uint64_t bell:2;
0292         uint64_t cram:2;
0293         uint64_t mram:2;
0294         uint64_t reserved_44_63:20;
0295 #endif
0296     } cn63xxp1;
0297 };
0298 
0299 union cvmx_sriox_imsg_ctrl {
0300     uint64_t u64;
0301     struct cvmx_sriox_imsg_ctrl_s {
0302 #ifdef __BIG_ENDIAN_BITFIELD
0303         uint64_t reserved_32_63:32;
0304         uint64_t to_mode:1;
0305         uint64_t reserved_30_30:1;
0306         uint64_t rsp_thr:6;
0307         uint64_t reserved_22_23:2;
0308         uint64_t rp1_sid:1;
0309         uint64_t rp0_sid:2;
0310         uint64_t rp1_pid:1;
0311         uint64_t rp0_pid:2;
0312         uint64_t reserved_15_15:1;
0313         uint64_t prt_sel:3;
0314         uint64_t lttr:4;
0315         uint64_t prio:4;
0316         uint64_t mbox:4;
0317 #else
0318         uint64_t mbox:4;
0319         uint64_t prio:4;
0320         uint64_t lttr:4;
0321         uint64_t prt_sel:3;
0322         uint64_t reserved_15_15:1;
0323         uint64_t rp0_pid:2;
0324         uint64_t rp1_pid:1;
0325         uint64_t rp0_sid:2;
0326         uint64_t rp1_sid:1;
0327         uint64_t reserved_22_23:2;
0328         uint64_t rsp_thr:6;
0329         uint64_t reserved_30_30:1;
0330         uint64_t to_mode:1;
0331         uint64_t reserved_32_63:32;
0332 #endif
0333     } s;
0334 };
0335 
0336 union cvmx_sriox_imsg_inst_hdrx {
0337     uint64_t u64;
0338     struct cvmx_sriox_imsg_inst_hdrx_s {
0339 #ifdef __BIG_ENDIAN_BITFIELD
0340         uint64_t r:1;
0341         uint64_t reserved_58_62:5;
0342         uint64_t pm:2;
0343         uint64_t reserved_55_55:1;
0344         uint64_t sl:7;
0345         uint64_t reserved_46_47:2;
0346         uint64_t nqos:1;
0347         uint64_t ngrp:1;
0348         uint64_t ntt:1;
0349         uint64_t ntag:1;
0350         uint64_t reserved_35_41:7;
0351         uint64_t rs:1;
0352         uint64_t tt:2;
0353         uint64_t tag:32;
0354 #else
0355         uint64_t tag:32;
0356         uint64_t tt:2;
0357         uint64_t rs:1;
0358         uint64_t reserved_35_41:7;
0359         uint64_t ntag:1;
0360         uint64_t ntt:1;
0361         uint64_t ngrp:1;
0362         uint64_t nqos:1;
0363         uint64_t reserved_46_47:2;
0364         uint64_t sl:7;
0365         uint64_t reserved_55_55:1;
0366         uint64_t pm:2;
0367         uint64_t reserved_58_62:5;
0368         uint64_t r:1;
0369 #endif
0370     } s;
0371 };
0372 
0373 union cvmx_sriox_imsg_qos_grpx {
0374     uint64_t u64;
0375     struct cvmx_sriox_imsg_qos_grpx_s {
0376 #ifdef __BIG_ENDIAN_BITFIELD
0377         uint64_t reserved_63_63:1;
0378         uint64_t qos7:3;
0379         uint64_t grp7:4;
0380         uint64_t reserved_55_55:1;
0381         uint64_t qos6:3;
0382         uint64_t grp6:4;
0383         uint64_t reserved_47_47:1;
0384         uint64_t qos5:3;
0385         uint64_t grp5:4;
0386         uint64_t reserved_39_39:1;
0387         uint64_t qos4:3;
0388         uint64_t grp4:4;
0389         uint64_t reserved_31_31:1;
0390         uint64_t qos3:3;
0391         uint64_t grp3:4;
0392         uint64_t reserved_23_23:1;
0393         uint64_t qos2:3;
0394         uint64_t grp2:4;
0395         uint64_t reserved_15_15:1;
0396         uint64_t qos1:3;
0397         uint64_t grp1:4;
0398         uint64_t reserved_7_7:1;
0399         uint64_t qos0:3;
0400         uint64_t grp0:4;
0401 #else
0402         uint64_t grp0:4;
0403         uint64_t qos0:3;
0404         uint64_t reserved_7_7:1;
0405         uint64_t grp1:4;
0406         uint64_t qos1:3;
0407         uint64_t reserved_15_15:1;
0408         uint64_t grp2:4;
0409         uint64_t qos2:3;
0410         uint64_t reserved_23_23:1;
0411         uint64_t grp3:4;
0412         uint64_t qos3:3;
0413         uint64_t reserved_31_31:1;
0414         uint64_t grp4:4;
0415         uint64_t qos4:3;
0416         uint64_t reserved_39_39:1;
0417         uint64_t grp5:4;
0418         uint64_t qos5:3;
0419         uint64_t reserved_47_47:1;
0420         uint64_t grp6:4;
0421         uint64_t qos6:3;
0422         uint64_t reserved_55_55:1;
0423         uint64_t grp7:4;
0424         uint64_t qos7:3;
0425         uint64_t reserved_63_63:1;
0426 #endif
0427     } s;
0428 };
0429 
0430 union cvmx_sriox_imsg_statusx {
0431     uint64_t u64;
0432     struct cvmx_sriox_imsg_statusx_s {
0433 #ifdef __BIG_ENDIAN_BITFIELD
0434         uint64_t val1:1;
0435         uint64_t err1:1;
0436         uint64_t toe1:1;
0437         uint64_t toc1:1;
0438         uint64_t prt1:1;
0439         uint64_t reserved_58_58:1;
0440         uint64_t tt1:1;
0441         uint64_t dis1:1;
0442         uint64_t seg1:4;
0443         uint64_t mbox1:2;
0444         uint64_t lttr1:2;
0445         uint64_t sid1:16;
0446         uint64_t val0:1;
0447         uint64_t err0:1;
0448         uint64_t toe0:1;
0449         uint64_t toc0:1;
0450         uint64_t prt0:1;
0451         uint64_t reserved_26_26:1;
0452         uint64_t tt0:1;
0453         uint64_t dis0:1;
0454         uint64_t seg0:4;
0455         uint64_t mbox0:2;
0456         uint64_t lttr0:2;
0457         uint64_t sid0:16;
0458 #else
0459         uint64_t sid0:16;
0460         uint64_t lttr0:2;
0461         uint64_t mbox0:2;
0462         uint64_t seg0:4;
0463         uint64_t dis0:1;
0464         uint64_t tt0:1;
0465         uint64_t reserved_26_26:1;
0466         uint64_t prt0:1;
0467         uint64_t toc0:1;
0468         uint64_t toe0:1;
0469         uint64_t err0:1;
0470         uint64_t val0:1;
0471         uint64_t sid1:16;
0472         uint64_t lttr1:2;
0473         uint64_t mbox1:2;
0474         uint64_t seg1:4;
0475         uint64_t dis1:1;
0476         uint64_t tt1:1;
0477         uint64_t reserved_58_58:1;
0478         uint64_t prt1:1;
0479         uint64_t toc1:1;
0480         uint64_t toe1:1;
0481         uint64_t err1:1;
0482         uint64_t val1:1;
0483 #endif
0484     } s;
0485 };
0486 
0487 union cvmx_sriox_imsg_vport_thr {
0488     uint64_t u64;
0489     struct cvmx_sriox_imsg_vport_thr_s {
0490 #ifdef __BIG_ENDIAN_BITFIELD
0491         uint64_t reserved_54_63:10;
0492         uint64_t max_tot:6;
0493         uint64_t reserved_46_47:2;
0494         uint64_t max_s1:6;
0495         uint64_t reserved_38_39:2;
0496         uint64_t max_s0:6;
0497         uint64_t sp_vport:1;
0498         uint64_t reserved_20_30:11;
0499         uint64_t buf_thr:4;
0500         uint64_t reserved_14_15:2;
0501         uint64_t max_p1:6;
0502         uint64_t reserved_6_7:2;
0503         uint64_t max_p0:6;
0504 #else
0505         uint64_t max_p0:6;
0506         uint64_t reserved_6_7:2;
0507         uint64_t max_p1:6;
0508         uint64_t reserved_14_15:2;
0509         uint64_t buf_thr:4;
0510         uint64_t reserved_20_30:11;
0511         uint64_t sp_vport:1;
0512         uint64_t max_s0:6;
0513         uint64_t reserved_38_39:2;
0514         uint64_t max_s1:6;
0515         uint64_t reserved_46_47:2;
0516         uint64_t max_tot:6;
0517         uint64_t reserved_54_63:10;
0518 #endif
0519     } s;
0520 };
0521 
0522 union cvmx_sriox_imsg_vport_thr2 {
0523     uint64_t u64;
0524     struct cvmx_sriox_imsg_vport_thr2_s {
0525 #ifdef __BIG_ENDIAN_BITFIELD
0526         uint64_t reserved_46_63:18;
0527         uint64_t max_s3:6;
0528         uint64_t reserved_38_39:2;
0529         uint64_t max_s2:6;
0530         uint64_t reserved_0_31:32;
0531 #else
0532         uint64_t reserved_0_31:32;
0533         uint64_t max_s2:6;
0534         uint64_t reserved_38_39:2;
0535         uint64_t max_s3:6;
0536         uint64_t reserved_46_63:18;
0537 #endif
0538     } s;
0539 };
0540 
0541 union cvmx_sriox_int2_enable {
0542     uint64_t u64;
0543     struct cvmx_sriox_int2_enable_s {
0544 #ifdef __BIG_ENDIAN_BITFIELD
0545         uint64_t reserved_1_63:63;
0546         uint64_t pko_rst:1;
0547 #else
0548         uint64_t pko_rst:1;
0549         uint64_t reserved_1_63:63;
0550 #endif
0551     } s;
0552 };
0553 
0554 union cvmx_sriox_int2_reg {
0555     uint64_t u64;
0556     struct cvmx_sriox_int2_reg_s {
0557 #ifdef __BIG_ENDIAN_BITFIELD
0558         uint64_t reserved_32_63:32;
0559         uint64_t int_sum:1;
0560         uint64_t reserved_1_30:30;
0561         uint64_t pko_rst:1;
0562 #else
0563         uint64_t pko_rst:1;
0564         uint64_t reserved_1_30:30;
0565         uint64_t int_sum:1;
0566         uint64_t reserved_32_63:32;
0567 #endif
0568     } s;
0569 };
0570 
0571 union cvmx_sriox_int_enable {
0572     uint64_t u64;
0573     struct cvmx_sriox_int_enable_s {
0574 #ifdef __BIG_ENDIAN_BITFIELD
0575         uint64_t reserved_27_63:37;
0576         uint64_t zero_pkt:1;
0577         uint64_t ttl_tout:1;
0578         uint64_t fail:1;
0579         uint64_t degrade:1;
0580         uint64_t mac_buf:1;
0581         uint64_t f_error:1;
0582         uint64_t rtry_err:1;
0583         uint64_t pko_err:1;
0584         uint64_t omsg_err:1;
0585         uint64_t omsg1:1;
0586         uint64_t omsg0:1;
0587         uint64_t link_up:1;
0588         uint64_t link_dwn:1;
0589         uint64_t phy_erb:1;
0590         uint64_t log_erb:1;
0591         uint64_t soft_rx:1;
0592         uint64_t soft_tx:1;
0593         uint64_t mce_rx:1;
0594         uint64_t mce_tx:1;
0595         uint64_t wr_done:1;
0596         uint64_t sli_err:1;
0597         uint64_t deny_wr:1;
0598         uint64_t bar_err:1;
0599         uint64_t maint_op:1;
0600         uint64_t rxbell:1;
0601         uint64_t bell_err:1;
0602         uint64_t txbell:1;
0603 #else
0604         uint64_t txbell:1;
0605         uint64_t bell_err:1;
0606         uint64_t rxbell:1;
0607         uint64_t maint_op:1;
0608         uint64_t bar_err:1;
0609         uint64_t deny_wr:1;
0610         uint64_t sli_err:1;
0611         uint64_t wr_done:1;
0612         uint64_t mce_tx:1;
0613         uint64_t mce_rx:1;
0614         uint64_t soft_tx:1;
0615         uint64_t soft_rx:1;
0616         uint64_t log_erb:1;
0617         uint64_t phy_erb:1;
0618         uint64_t link_dwn:1;
0619         uint64_t link_up:1;
0620         uint64_t omsg0:1;
0621         uint64_t omsg1:1;
0622         uint64_t omsg_err:1;
0623         uint64_t pko_err:1;
0624         uint64_t rtry_err:1;
0625         uint64_t f_error:1;
0626         uint64_t mac_buf:1;
0627         uint64_t degrade:1;
0628         uint64_t fail:1;
0629         uint64_t ttl_tout:1;
0630         uint64_t zero_pkt:1;
0631         uint64_t reserved_27_63:37;
0632 #endif
0633     } s;
0634     struct cvmx_sriox_int_enable_cn63xxp1 {
0635 #ifdef __BIG_ENDIAN_BITFIELD
0636         uint64_t reserved_22_63:42;
0637         uint64_t f_error:1;
0638         uint64_t rtry_err:1;
0639         uint64_t pko_err:1;
0640         uint64_t omsg_err:1;
0641         uint64_t omsg1:1;
0642         uint64_t omsg0:1;
0643         uint64_t link_up:1;
0644         uint64_t link_dwn:1;
0645         uint64_t phy_erb:1;
0646         uint64_t log_erb:1;
0647         uint64_t soft_rx:1;
0648         uint64_t soft_tx:1;
0649         uint64_t mce_rx:1;
0650         uint64_t mce_tx:1;
0651         uint64_t wr_done:1;
0652         uint64_t sli_err:1;
0653         uint64_t deny_wr:1;
0654         uint64_t bar_err:1;
0655         uint64_t maint_op:1;
0656         uint64_t rxbell:1;
0657         uint64_t bell_err:1;
0658         uint64_t txbell:1;
0659 #else
0660         uint64_t txbell:1;
0661         uint64_t bell_err:1;
0662         uint64_t rxbell:1;
0663         uint64_t maint_op:1;
0664         uint64_t bar_err:1;
0665         uint64_t deny_wr:1;
0666         uint64_t sli_err:1;
0667         uint64_t wr_done:1;
0668         uint64_t mce_tx:1;
0669         uint64_t mce_rx:1;
0670         uint64_t soft_tx:1;
0671         uint64_t soft_rx:1;
0672         uint64_t log_erb:1;
0673         uint64_t phy_erb:1;
0674         uint64_t link_dwn:1;
0675         uint64_t link_up:1;
0676         uint64_t omsg0:1;
0677         uint64_t omsg1:1;
0678         uint64_t omsg_err:1;
0679         uint64_t pko_err:1;
0680         uint64_t rtry_err:1;
0681         uint64_t f_error:1;
0682         uint64_t reserved_22_63:42;
0683 #endif
0684     } cn63xxp1;
0685 };
0686 
0687 union cvmx_sriox_int_info0 {
0688     uint64_t u64;
0689     struct cvmx_sriox_int_info0_s {
0690 #ifdef __BIG_ENDIAN_BITFIELD
0691         uint64_t cmd:4;
0692         uint64_t type:4;
0693         uint64_t tag:8;
0694         uint64_t reserved_42_47:6;
0695         uint64_t length:10;
0696         uint64_t status:3;
0697         uint64_t reserved_16_28:13;
0698         uint64_t be0:8;
0699         uint64_t be1:8;
0700 #else
0701         uint64_t be1:8;
0702         uint64_t be0:8;
0703         uint64_t reserved_16_28:13;
0704         uint64_t status:3;
0705         uint64_t length:10;
0706         uint64_t reserved_42_47:6;
0707         uint64_t tag:8;
0708         uint64_t type:4;
0709         uint64_t cmd:4;
0710 #endif
0711     } s;
0712 };
0713 
0714 union cvmx_sriox_int_info1 {
0715     uint64_t u64;
0716     struct cvmx_sriox_int_info1_s {
0717 #ifdef __BIG_ENDIAN_BITFIELD
0718         uint64_t info1:64;
0719 #else
0720         uint64_t info1:64;
0721 #endif
0722     } s;
0723 };
0724 
0725 union cvmx_sriox_int_info2 {
0726     uint64_t u64;
0727     struct cvmx_sriox_int_info2_s {
0728 #ifdef __BIG_ENDIAN_BITFIELD
0729         uint64_t prio:2;
0730         uint64_t tt:1;
0731         uint64_t sis:1;
0732         uint64_t ssize:4;
0733         uint64_t did:16;
0734         uint64_t xmbox:4;
0735         uint64_t mbox:2;
0736         uint64_t letter:2;
0737         uint64_t rsrvd:30;
0738         uint64_t lns:1;
0739         uint64_t intr:1;
0740 #else
0741         uint64_t intr:1;
0742         uint64_t lns:1;
0743         uint64_t rsrvd:30;
0744         uint64_t letter:2;
0745         uint64_t mbox:2;
0746         uint64_t xmbox:4;
0747         uint64_t did:16;
0748         uint64_t ssize:4;
0749         uint64_t sis:1;
0750         uint64_t tt:1;
0751         uint64_t prio:2;
0752 #endif
0753     } s;
0754 };
0755 
0756 union cvmx_sriox_int_info3 {
0757     uint64_t u64;
0758     struct cvmx_sriox_int_info3_s {
0759 #ifdef __BIG_ENDIAN_BITFIELD
0760         uint64_t prio:2;
0761         uint64_t tt:2;
0762         uint64_t type:4;
0763         uint64_t other:48;
0764         uint64_t reserved_0_7:8;
0765 #else
0766         uint64_t reserved_0_7:8;
0767         uint64_t other:48;
0768         uint64_t type:4;
0769         uint64_t tt:2;
0770         uint64_t prio:2;
0771 #endif
0772     } s;
0773 };
0774 
0775 union cvmx_sriox_int_reg {
0776     uint64_t u64;
0777     struct cvmx_sriox_int_reg_s {
0778 #ifdef __BIG_ENDIAN_BITFIELD
0779         uint64_t reserved_32_63:32;
0780         uint64_t int2_sum:1;
0781         uint64_t reserved_27_30:4;
0782         uint64_t zero_pkt:1;
0783         uint64_t ttl_tout:1;
0784         uint64_t fail:1;
0785         uint64_t degrad:1;
0786         uint64_t mac_buf:1;
0787         uint64_t f_error:1;
0788         uint64_t rtry_err:1;
0789         uint64_t pko_err:1;
0790         uint64_t omsg_err:1;
0791         uint64_t omsg1:1;
0792         uint64_t omsg0:1;
0793         uint64_t link_up:1;
0794         uint64_t link_dwn:1;
0795         uint64_t phy_erb:1;
0796         uint64_t log_erb:1;
0797         uint64_t soft_rx:1;
0798         uint64_t soft_tx:1;
0799         uint64_t mce_rx:1;
0800         uint64_t mce_tx:1;
0801         uint64_t wr_done:1;
0802         uint64_t sli_err:1;
0803         uint64_t deny_wr:1;
0804         uint64_t bar_err:1;
0805         uint64_t maint_op:1;
0806         uint64_t rxbell:1;
0807         uint64_t bell_err:1;
0808         uint64_t txbell:1;
0809 #else
0810         uint64_t txbell:1;
0811         uint64_t bell_err:1;
0812         uint64_t rxbell:1;
0813         uint64_t maint_op:1;
0814         uint64_t bar_err:1;
0815         uint64_t deny_wr:1;
0816         uint64_t sli_err:1;
0817         uint64_t wr_done:1;
0818         uint64_t mce_tx:1;
0819         uint64_t mce_rx:1;
0820         uint64_t soft_tx:1;
0821         uint64_t soft_rx:1;
0822         uint64_t log_erb:1;
0823         uint64_t phy_erb:1;
0824         uint64_t link_dwn:1;
0825         uint64_t link_up:1;
0826         uint64_t omsg0:1;
0827         uint64_t omsg1:1;
0828         uint64_t omsg_err:1;
0829         uint64_t pko_err:1;
0830         uint64_t rtry_err:1;
0831         uint64_t f_error:1;
0832         uint64_t mac_buf:1;
0833         uint64_t degrad:1;
0834         uint64_t fail:1;
0835         uint64_t ttl_tout:1;
0836         uint64_t zero_pkt:1;
0837         uint64_t reserved_27_30:4;
0838         uint64_t int2_sum:1;
0839         uint64_t reserved_32_63:32;
0840 #endif
0841     } s;
0842     struct cvmx_sriox_int_reg_cn63xxp1 {
0843 #ifdef __BIG_ENDIAN_BITFIELD
0844         uint64_t reserved_22_63:42;
0845         uint64_t f_error:1;
0846         uint64_t rtry_err:1;
0847         uint64_t pko_err:1;
0848         uint64_t omsg_err:1;
0849         uint64_t omsg1:1;
0850         uint64_t omsg0:1;
0851         uint64_t link_up:1;
0852         uint64_t link_dwn:1;
0853         uint64_t phy_erb:1;
0854         uint64_t log_erb:1;
0855         uint64_t soft_rx:1;
0856         uint64_t soft_tx:1;
0857         uint64_t mce_rx:1;
0858         uint64_t mce_tx:1;
0859         uint64_t wr_done:1;
0860         uint64_t sli_err:1;
0861         uint64_t deny_wr:1;
0862         uint64_t bar_err:1;
0863         uint64_t maint_op:1;
0864         uint64_t rxbell:1;
0865         uint64_t bell_err:1;
0866         uint64_t txbell:1;
0867 #else
0868         uint64_t txbell:1;
0869         uint64_t bell_err:1;
0870         uint64_t rxbell:1;
0871         uint64_t maint_op:1;
0872         uint64_t bar_err:1;
0873         uint64_t deny_wr:1;
0874         uint64_t sli_err:1;
0875         uint64_t wr_done:1;
0876         uint64_t mce_tx:1;
0877         uint64_t mce_rx:1;
0878         uint64_t soft_tx:1;
0879         uint64_t soft_rx:1;
0880         uint64_t log_erb:1;
0881         uint64_t phy_erb:1;
0882         uint64_t link_dwn:1;
0883         uint64_t link_up:1;
0884         uint64_t omsg0:1;
0885         uint64_t omsg1:1;
0886         uint64_t omsg_err:1;
0887         uint64_t pko_err:1;
0888         uint64_t rtry_err:1;
0889         uint64_t f_error:1;
0890         uint64_t reserved_22_63:42;
0891 #endif
0892     } cn63xxp1;
0893 };
0894 
0895 union cvmx_sriox_ip_feature {
0896     uint64_t u64;
0897     struct cvmx_sriox_ip_feature_s {
0898 #ifdef __BIG_ENDIAN_BITFIELD
0899         uint64_t ops:32;
0900         uint64_t reserved_15_31:17;
0901         uint64_t no_vmin:1;
0902         uint64_t a66:1;
0903         uint64_t a50:1;
0904         uint64_t reserved_11_11:1;
0905         uint64_t tx_flow:1;
0906         uint64_t pt_width:2;
0907         uint64_t tx_pol:4;
0908         uint64_t rx_pol:4;
0909 #else
0910         uint64_t rx_pol:4;
0911         uint64_t tx_pol:4;
0912         uint64_t pt_width:2;
0913         uint64_t tx_flow:1;
0914         uint64_t reserved_11_11:1;
0915         uint64_t a50:1;
0916         uint64_t a66:1;
0917         uint64_t no_vmin:1;
0918         uint64_t reserved_15_31:17;
0919         uint64_t ops:32;
0920 #endif
0921     } s;
0922     struct cvmx_sriox_ip_feature_cn63xx {
0923 #ifdef __BIG_ENDIAN_BITFIELD
0924         uint64_t ops:32;
0925         uint64_t reserved_14_31:18;
0926         uint64_t a66:1;
0927         uint64_t a50:1;
0928         uint64_t reserved_11_11:1;
0929         uint64_t tx_flow:1;
0930         uint64_t pt_width:2;
0931         uint64_t tx_pol:4;
0932         uint64_t rx_pol:4;
0933 #else
0934         uint64_t rx_pol:4;
0935         uint64_t tx_pol:4;
0936         uint64_t pt_width:2;
0937         uint64_t tx_flow:1;
0938         uint64_t reserved_11_11:1;
0939         uint64_t a50:1;
0940         uint64_t a66:1;
0941         uint64_t reserved_14_31:18;
0942         uint64_t ops:32;
0943 #endif
0944     } cn63xx;
0945 };
0946 
0947 union cvmx_sriox_mac_buffers {
0948     uint64_t u64;
0949     struct cvmx_sriox_mac_buffers_s {
0950 #ifdef __BIG_ENDIAN_BITFIELD
0951         uint64_t reserved_56_63:8;
0952         uint64_t tx_enb:8;
0953         uint64_t reserved_44_47:4;
0954         uint64_t tx_inuse:4;
0955         uint64_t tx_stat:8;
0956         uint64_t reserved_24_31:8;
0957         uint64_t rx_enb:8;
0958         uint64_t reserved_12_15:4;
0959         uint64_t rx_inuse:4;
0960         uint64_t rx_stat:8;
0961 #else
0962         uint64_t rx_stat:8;
0963         uint64_t rx_inuse:4;
0964         uint64_t reserved_12_15:4;
0965         uint64_t rx_enb:8;
0966         uint64_t reserved_24_31:8;
0967         uint64_t tx_stat:8;
0968         uint64_t tx_inuse:4;
0969         uint64_t reserved_44_47:4;
0970         uint64_t tx_enb:8;
0971         uint64_t reserved_56_63:8;
0972 #endif
0973     } s;
0974 };
0975 
0976 union cvmx_sriox_maint_op {
0977     uint64_t u64;
0978     struct cvmx_sriox_maint_op_s {
0979 #ifdef __BIG_ENDIAN_BITFIELD
0980         uint64_t wr_data:32;
0981         uint64_t reserved_27_31:5;
0982         uint64_t fail:1;
0983         uint64_t pending:1;
0984         uint64_t op:1;
0985         uint64_t addr:24;
0986 #else
0987         uint64_t addr:24;
0988         uint64_t op:1;
0989         uint64_t pending:1;
0990         uint64_t fail:1;
0991         uint64_t reserved_27_31:5;
0992         uint64_t wr_data:32;
0993 #endif
0994     } s;
0995 };
0996 
0997 union cvmx_sriox_maint_rd_data {
0998     uint64_t u64;
0999     struct cvmx_sriox_maint_rd_data_s {
1000 #ifdef __BIG_ENDIAN_BITFIELD
1001         uint64_t reserved_33_63:31;
1002         uint64_t valid:1;
1003         uint64_t rd_data:32;
1004 #else
1005         uint64_t rd_data:32;
1006         uint64_t valid:1;
1007         uint64_t reserved_33_63:31;
1008 #endif
1009     } s;
1010 };
1011 
1012 union cvmx_sriox_mce_tx_ctl {
1013     uint64_t u64;
1014     struct cvmx_sriox_mce_tx_ctl_s {
1015 #ifdef __BIG_ENDIAN_BITFIELD
1016         uint64_t reserved_1_63:63;
1017         uint64_t mce:1;
1018 #else
1019         uint64_t mce:1;
1020         uint64_t reserved_1_63:63;
1021 #endif
1022     } s;
1023 };
1024 
1025 union cvmx_sriox_mem_op_ctrl {
1026     uint64_t u64;
1027     struct cvmx_sriox_mem_op_ctrl_s {
1028 #ifdef __BIG_ENDIAN_BITFIELD
1029         uint64_t reserved_10_63:54;
1030         uint64_t rr_ro:1;
1031         uint64_t w_ro:1;
1032         uint64_t reserved_6_7:2;
1033         uint64_t rp1_sid:1;
1034         uint64_t rp0_sid:2;
1035         uint64_t rp1_pid:1;
1036         uint64_t rp0_pid:2;
1037 #else
1038         uint64_t rp0_pid:2;
1039         uint64_t rp1_pid:1;
1040         uint64_t rp0_sid:2;
1041         uint64_t rp1_sid:1;
1042         uint64_t reserved_6_7:2;
1043         uint64_t w_ro:1;
1044         uint64_t rr_ro:1;
1045         uint64_t reserved_10_63:54;
1046 #endif
1047     } s;
1048 };
1049 
1050 union cvmx_sriox_omsg_ctrlx {
1051     uint64_t u64;
1052     struct cvmx_sriox_omsg_ctrlx_s {
1053 #ifdef __BIG_ENDIAN_BITFIELD
1054         uint64_t testmode:1;
1055         uint64_t reserved_37_62:26;
1056         uint64_t silo_max:5;
1057         uint64_t rtry_thr:16;
1058         uint64_t rtry_en:1;
1059         uint64_t reserved_11_14:4;
1060         uint64_t idm_tt:1;
1061         uint64_t idm_sis:1;
1062         uint64_t idm_did:1;
1063         uint64_t lttr_sp:4;
1064         uint64_t lttr_mp:4;
1065 #else
1066         uint64_t lttr_mp:4;
1067         uint64_t lttr_sp:4;
1068         uint64_t idm_did:1;
1069         uint64_t idm_sis:1;
1070         uint64_t idm_tt:1;
1071         uint64_t reserved_11_14:4;
1072         uint64_t rtry_en:1;
1073         uint64_t rtry_thr:16;
1074         uint64_t silo_max:5;
1075         uint64_t reserved_37_62:26;
1076         uint64_t testmode:1;
1077 #endif
1078     } s;
1079     struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
1080 #ifdef __BIG_ENDIAN_BITFIELD
1081         uint64_t testmode:1;
1082         uint64_t reserved_32_62:31;
1083         uint64_t rtry_thr:16;
1084         uint64_t rtry_en:1;
1085         uint64_t reserved_11_14:4;
1086         uint64_t idm_tt:1;
1087         uint64_t idm_sis:1;
1088         uint64_t idm_did:1;
1089         uint64_t lttr_sp:4;
1090         uint64_t lttr_mp:4;
1091 #else
1092         uint64_t lttr_mp:4;
1093         uint64_t lttr_sp:4;
1094         uint64_t idm_did:1;
1095         uint64_t idm_sis:1;
1096         uint64_t idm_tt:1;
1097         uint64_t reserved_11_14:4;
1098         uint64_t rtry_en:1;
1099         uint64_t rtry_thr:16;
1100         uint64_t reserved_32_62:31;
1101         uint64_t testmode:1;
1102 #endif
1103     } cn63xxp1;
1104 };
1105 
1106 union cvmx_sriox_omsg_done_countsx {
1107     uint64_t u64;
1108     struct cvmx_sriox_omsg_done_countsx_s {
1109 #ifdef __BIG_ENDIAN_BITFIELD
1110         uint64_t reserved_32_63:32;
1111         uint64_t bad:16;
1112         uint64_t good:16;
1113 #else
1114         uint64_t good:16;
1115         uint64_t bad:16;
1116         uint64_t reserved_32_63:32;
1117 #endif
1118     } s;
1119 };
1120 
1121 union cvmx_sriox_omsg_fmp_mrx {
1122     uint64_t u64;
1123     struct cvmx_sriox_omsg_fmp_mrx_s {
1124 #ifdef __BIG_ENDIAN_BITFIELD
1125         uint64_t reserved_15_63:49;
1126         uint64_t ctlr_sp:1;
1127         uint64_t ctlr_fmp:1;
1128         uint64_t ctlr_nmp:1;
1129         uint64_t id_sp:1;
1130         uint64_t id_fmp:1;
1131         uint64_t id_nmp:1;
1132         uint64_t id_psd:1;
1133         uint64_t mbox_sp:1;
1134         uint64_t mbox_fmp:1;
1135         uint64_t mbox_nmp:1;
1136         uint64_t mbox_psd:1;
1137         uint64_t all_sp:1;
1138         uint64_t all_fmp:1;
1139         uint64_t all_nmp:1;
1140         uint64_t all_psd:1;
1141 #else
1142         uint64_t all_psd:1;
1143         uint64_t all_nmp:1;
1144         uint64_t all_fmp:1;
1145         uint64_t all_sp:1;
1146         uint64_t mbox_psd:1;
1147         uint64_t mbox_nmp:1;
1148         uint64_t mbox_fmp:1;
1149         uint64_t mbox_sp:1;
1150         uint64_t id_psd:1;
1151         uint64_t id_nmp:1;
1152         uint64_t id_fmp:1;
1153         uint64_t id_sp:1;
1154         uint64_t ctlr_nmp:1;
1155         uint64_t ctlr_fmp:1;
1156         uint64_t ctlr_sp:1;
1157         uint64_t reserved_15_63:49;
1158 #endif
1159     } s;
1160 };
1161 
1162 union cvmx_sriox_omsg_nmp_mrx {
1163     uint64_t u64;
1164     struct cvmx_sriox_omsg_nmp_mrx_s {
1165 #ifdef __BIG_ENDIAN_BITFIELD
1166         uint64_t reserved_15_63:49;
1167         uint64_t ctlr_sp:1;
1168         uint64_t ctlr_fmp:1;
1169         uint64_t ctlr_nmp:1;
1170         uint64_t id_sp:1;
1171         uint64_t id_fmp:1;
1172         uint64_t id_nmp:1;
1173         uint64_t reserved_8_8:1;
1174         uint64_t mbox_sp:1;
1175         uint64_t mbox_fmp:1;
1176         uint64_t mbox_nmp:1;
1177         uint64_t reserved_4_4:1;
1178         uint64_t all_sp:1;
1179         uint64_t all_fmp:1;
1180         uint64_t all_nmp:1;
1181         uint64_t reserved_0_0:1;
1182 #else
1183         uint64_t reserved_0_0:1;
1184         uint64_t all_nmp:1;
1185         uint64_t all_fmp:1;
1186         uint64_t all_sp:1;
1187         uint64_t reserved_4_4:1;
1188         uint64_t mbox_nmp:1;
1189         uint64_t mbox_fmp:1;
1190         uint64_t mbox_sp:1;
1191         uint64_t reserved_8_8:1;
1192         uint64_t id_nmp:1;
1193         uint64_t id_fmp:1;
1194         uint64_t id_sp:1;
1195         uint64_t ctlr_nmp:1;
1196         uint64_t ctlr_fmp:1;
1197         uint64_t ctlr_sp:1;
1198         uint64_t reserved_15_63:49;
1199 #endif
1200     } s;
1201 };
1202 
1203 union cvmx_sriox_omsg_portx {
1204     uint64_t u64;
1205     struct cvmx_sriox_omsg_portx_s {
1206 #ifdef __BIG_ENDIAN_BITFIELD
1207         uint64_t reserved_32_63:32;
1208         uint64_t enable:1;
1209         uint64_t reserved_3_30:28;
1210         uint64_t port:3;
1211 #else
1212         uint64_t port:3;
1213         uint64_t reserved_3_30:28;
1214         uint64_t enable:1;
1215         uint64_t reserved_32_63:32;
1216 #endif
1217     } s;
1218     struct cvmx_sriox_omsg_portx_cn63xx {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220         uint64_t reserved_32_63:32;
1221         uint64_t enable:1;
1222         uint64_t reserved_2_30:29;
1223         uint64_t port:2;
1224 #else
1225         uint64_t port:2;
1226         uint64_t reserved_2_30:29;
1227         uint64_t enable:1;
1228         uint64_t reserved_32_63:32;
1229 #endif
1230     } cn63xx;
1231 };
1232 
1233 union cvmx_sriox_omsg_silo_thr {
1234     uint64_t u64;
1235     struct cvmx_sriox_omsg_silo_thr_s {
1236 #ifdef __BIG_ENDIAN_BITFIELD
1237         uint64_t reserved_5_63:59;
1238         uint64_t tot_silo:5;
1239 #else
1240         uint64_t tot_silo:5;
1241         uint64_t reserved_5_63:59;
1242 #endif
1243     } s;
1244 };
1245 
1246 union cvmx_sriox_omsg_sp_mrx {
1247     uint64_t u64;
1248     struct cvmx_sriox_omsg_sp_mrx_s {
1249 #ifdef __BIG_ENDIAN_BITFIELD
1250         uint64_t reserved_16_63:48;
1251         uint64_t xmbox_sp:1;
1252         uint64_t ctlr_sp:1;
1253         uint64_t ctlr_fmp:1;
1254         uint64_t ctlr_nmp:1;
1255         uint64_t id_sp:1;
1256         uint64_t id_fmp:1;
1257         uint64_t id_nmp:1;
1258         uint64_t id_psd:1;
1259         uint64_t mbox_sp:1;
1260         uint64_t mbox_fmp:1;
1261         uint64_t mbox_nmp:1;
1262         uint64_t mbox_psd:1;
1263         uint64_t all_sp:1;
1264         uint64_t all_fmp:1;
1265         uint64_t all_nmp:1;
1266         uint64_t all_psd:1;
1267 #else
1268         uint64_t all_psd:1;
1269         uint64_t all_nmp:1;
1270         uint64_t all_fmp:1;
1271         uint64_t all_sp:1;
1272         uint64_t mbox_psd:1;
1273         uint64_t mbox_nmp:1;
1274         uint64_t mbox_fmp:1;
1275         uint64_t mbox_sp:1;
1276         uint64_t id_psd:1;
1277         uint64_t id_nmp:1;
1278         uint64_t id_fmp:1;
1279         uint64_t id_sp:1;
1280         uint64_t ctlr_nmp:1;
1281         uint64_t ctlr_fmp:1;
1282         uint64_t ctlr_sp:1;
1283         uint64_t xmbox_sp:1;
1284         uint64_t reserved_16_63:48;
1285 #endif
1286     } s;
1287 };
1288 
1289 union cvmx_sriox_priox_in_use {
1290     uint64_t u64;
1291     struct cvmx_sriox_priox_in_use_s {
1292 #ifdef __BIG_ENDIAN_BITFIELD
1293         uint64_t reserved_32_63:32;
1294         uint64_t end_cnt:16;
1295         uint64_t start_cnt:16;
1296 #else
1297         uint64_t start_cnt:16;
1298         uint64_t end_cnt:16;
1299         uint64_t reserved_32_63:32;
1300 #endif
1301     } s;
1302 };
1303 
1304 union cvmx_sriox_rx_bell {
1305     uint64_t u64;
1306     struct cvmx_sriox_rx_bell_s {
1307 #ifdef __BIG_ENDIAN_BITFIELD
1308         uint64_t reserved_48_63:16;
1309         uint64_t data:16;
1310         uint64_t src_id:16;
1311         uint64_t count:8;
1312         uint64_t reserved_5_7:3;
1313         uint64_t dest_id:1;
1314         uint64_t id16:1;
1315         uint64_t reserved_2_2:1;
1316         uint64_t priority:2;
1317 #else
1318         uint64_t priority:2;
1319         uint64_t reserved_2_2:1;
1320         uint64_t id16:1;
1321         uint64_t dest_id:1;
1322         uint64_t reserved_5_7:3;
1323         uint64_t count:8;
1324         uint64_t src_id:16;
1325         uint64_t data:16;
1326         uint64_t reserved_48_63:16;
1327 #endif
1328     } s;
1329 };
1330 
1331 union cvmx_sriox_rx_bell_seq {
1332     uint64_t u64;
1333     struct cvmx_sriox_rx_bell_seq_s {
1334 #ifdef __BIG_ENDIAN_BITFIELD
1335         uint64_t reserved_40_63:24;
1336         uint64_t count:8;
1337         uint64_t seq:32;
1338 #else
1339         uint64_t seq:32;
1340         uint64_t count:8;
1341         uint64_t reserved_40_63:24;
1342 #endif
1343     } s;
1344 };
1345 
1346 union cvmx_sriox_rx_status {
1347     uint64_t u64;
1348     struct cvmx_sriox_rx_status_s {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1350         uint64_t rtn_pr3:8;
1351         uint64_t rtn_pr2:8;
1352         uint64_t rtn_pr1:8;
1353         uint64_t reserved_28_39:12;
1354         uint64_t mbox:4;
1355         uint64_t comp:8;
1356         uint64_t reserved_13_15:3;
1357         uint64_t n_post:5;
1358         uint64_t post:8;
1359 #else
1360         uint64_t post:8;
1361         uint64_t n_post:5;
1362         uint64_t reserved_13_15:3;
1363         uint64_t comp:8;
1364         uint64_t mbox:4;
1365         uint64_t reserved_28_39:12;
1366         uint64_t rtn_pr1:8;
1367         uint64_t rtn_pr2:8;
1368         uint64_t rtn_pr3:8;
1369 #endif
1370     } s;
1371 };
1372 
1373 union cvmx_sriox_s2m_typex {
1374     uint64_t u64;
1375     struct cvmx_sriox_s2m_typex_s {
1376 #ifdef __BIG_ENDIAN_BITFIELD
1377         uint64_t reserved_19_63:45;
1378         uint64_t wr_op:3;
1379         uint64_t reserved_15_15:1;
1380         uint64_t rd_op:3;
1381         uint64_t wr_prior:2;
1382         uint64_t rd_prior:2;
1383         uint64_t reserved_6_7:2;
1384         uint64_t src_id:1;
1385         uint64_t id16:1;
1386         uint64_t reserved_2_3:2;
1387         uint64_t iaow_sel:2;
1388 #else
1389         uint64_t iaow_sel:2;
1390         uint64_t reserved_2_3:2;
1391         uint64_t id16:1;
1392         uint64_t src_id:1;
1393         uint64_t reserved_6_7:2;
1394         uint64_t rd_prior:2;
1395         uint64_t wr_prior:2;
1396         uint64_t rd_op:3;
1397         uint64_t reserved_15_15:1;
1398         uint64_t wr_op:3;
1399         uint64_t reserved_19_63:45;
1400 #endif
1401     } s;
1402 };
1403 
1404 union cvmx_sriox_seq {
1405     uint64_t u64;
1406     struct cvmx_sriox_seq_s {
1407 #ifdef __BIG_ENDIAN_BITFIELD
1408         uint64_t reserved_32_63:32;
1409         uint64_t seq:32;
1410 #else
1411         uint64_t seq:32;
1412         uint64_t reserved_32_63:32;
1413 #endif
1414     } s;
1415 };
1416 
1417 union cvmx_sriox_status_reg {
1418     uint64_t u64;
1419     struct cvmx_sriox_status_reg_s {
1420 #ifdef __BIG_ENDIAN_BITFIELD
1421         uint64_t reserved_2_63:62;
1422         uint64_t access:1;
1423         uint64_t srio:1;
1424 #else
1425         uint64_t srio:1;
1426         uint64_t access:1;
1427         uint64_t reserved_2_63:62;
1428 #endif
1429     } s;
1430 };
1431 
1432 union cvmx_sriox_tag_ctrl {
1433     uint64_t u64;
1434     struct cvmx_sriox_tag_ctrl_s {
1435 #ifdef __BIG_ENDIAN_BITFIELD
1436         uint64_t reserved_17_63:47;
1437         uint64_t o_clr:1;
1438         uint64_t reserved_13_15:3;
1439         uint64_t otag:5;
1440         uint64_t reserved_5_7:3;
1441         uint64_t itag:5;
1442 #else
1443         uint64_t itag:5;
1444         uint64_t reserved_5_7:3;
1445         uint64_t otag:5;
1446         uint64_t reserved_13_15:3;
1447         uint64_t o_clr:1;
1448         uint64_t reserved_17_63:47;
1449 #endif
1450     } s;
1451 };
1452 
1453 union cvmx_sriox_tlp_credits {
1454     uint64_t u64;
1455     struct cvmx_sriox_tlp_credits_s {
1456 #ifdef __BIG_ENDIAN_BITFIELD
1457         uint64_t reserved_28_63:36;
1458         uint64_t mbox:4;
1459         uint64_t comp:8;
1460         uint64_t reserved_13_15:3;
1461         uint64_t n_post:5;
1462         uint64_t post:8;
1463 #else
1464         uint64_t post:8;
1465         uint64_t n_post:5;
1466         uint64_t reserved_13_15:3;
1467         uint64_t comp:8;
1468         uint64_t mbox:4;
1469         uint64_t reserved_28_63:36;
1470 #endif
1471     } s;
1472 };
1473 
1474 union cvmx_sriox_tx_bell {
1475     uint64_t u64;
1476     struct cvmx_sriox_tx_bell_s {
1477 #ifdef __BIG_ENDIAN_BITFIELD
1478         uint64_t reserved_48_63:16;
1479         uint64_t data:16;
1480         uint64_t dest_id:16;
1481         uint64_t reserved_9_15:7;
1482         uint64_t pending:1;
1483         uint64_t reserved_5_7:3;
1484         uint64_t src_id:1;
1485         uint64_t id16:1;
1486         uint64_t reserved_2_2:1;
1487         uint64_t priority:2;
1488 #else
1489         uint64_t priority:2;
1490         uint64_t reserved_2_2:1;
1491         uint64_t id16:1;
1492         uint64_t src_id:1;
1493         uint64_t reserved_5_7:3;
1494         uint64_t pending:1;
1495         uint64_t reserved_9_15:7;
1496         uint64_t dest_id:16;
1497         uint64_t data:16;
1498         uint64_t reserved_48_63:16;
1499 #endif
1500     } s;
1501 };
1502 
1503 union cvmx_sriox_tx_bell_info {
1504     uint64_t u64;
1505     struct cvmx_sriox_tx_bell_info_s {
1506 #ifdef __BIG_ENDIAN_BITFIELD
1507         uint64_t reserved_48_63:16;
1508         uint64_t data:16;
1509         uint64_t dest_id:16;
1510         uint64_t reserved_8_15:8;
1511         uint64_t timeout:1;
1512         uint64_t error:1;
1513         uint64_t retry:1;
1514         uint64_t src_id:1;
1515         uint64_t id16:1;
1516         uint64_t reserved_2_2:1;
1517         uint64_t priority:2;
1518 #else
1519         uint64_t priority:2;
1520         uint64_t reserved_2_2:1;
1521         uint64_t id16:1;
1522         uint64_t src_id:1;
1523         uint64_t retry:1;
1524         uint64_t error:1;
1525         uint64_t timeout:1;
1526         uint64_t reserved_8_15:8;
1527         uint64_t dest_id:16;
1528         uint64_t data:16;
1529         uint64_t reserved_48_63:16;
1530 #endif
1531     } s;
1532 };
1533 
1534 union cvmx_sriox_tx_ctrl {
1535     uint64_t u64;
1536     struct cvmx_sriox_tx_ctrl_s {
1537 #ifdef __BIG_ENDIAN_BITFIELD
1538         uint64_t reserved_53_63:11;
1539         uint64_t tag_th2:5;
1540         uint64_t reserved_45_47:3;
1541         uint64_t tag_th1:5;
1542         uint64_t reserved_37_39:3;
1543         uint64_t tag_th0:5;
1544         uint64_t reserved_20_31:12;
1545         uint64_t tx_th2:4;
1546         uint64_t reserved_12_15:4;
1547         uint64_t tx_th1:4;
1548         uint64_t reserved_4_7:4;
1549         uint64_t tx_th0:4;
1550 #else
1551         uint64_t tx_th0:4;
1552         uint64_t reserved_4_7:4;
1553         uint64_t tx_th1:4;
1554         uint64_t reserved_12_15:4;
1555         uint64_t tx_th2:4;
1556         uint64_t reserved_20_31:12;
1557         uint64_t tag_th0:5;
1558         uint64_t reserved_37_39:3;
1559         uint64_t tag_th1:5;
1560         uint64_t reserved_45_47:3;
1561         uint64_t tag_th2:5;
1562         uint64_t reserved_53_63:11;
1563 #endif
1564     } s;
1565 };
1566 
1567 union cvmx_sriox_tx_emphasis {
1568     uint64_t u64;
1569     struct cvmx_sriox_tx_emphasis_s {
1570 #ifdef __BIG_ENDIAN_BITFIELD
1571         uint64_t reserved_4_63:60;
1572         uint64_t emph:4;
1573 #else
1574         uint64_t emph:4;
1575         uint64_t reserved_4_63:60;
1576 #endif
1577     } s;
1578 };
1579 
1580 union cvmx_sriox_tx_status {
1581     uint64_t u64;
1582     struct cvmx_sriox_tx_status_s {
1583 #ifdef __BIG_ENDIAN_BITFIELD
1584         uint64_t reserved_32_63:32;
1585         uint64_t s2m_pr3:8;
1586         uint64_t s2m_pr2:8;
1587         uint64_t s2m_pr1:8;
1588         uint64_t s2m_pr0:8;
1589 #else
1590         uint64_t s2m_pr0:8;
1591         uint64_t s2m_pr1:8;
1592         uint64_t s2m_pr2:8;
1593         uint64_t s2m_pr3:8;
1594         uint64_t reserved_32_63:32;
1595 #endif
1596     } s;
1597 };
1598 
1599 union cvmx_sriox_wr_done_counts {
1600     uint64_t u64;
1601     struct cvmx_sriox_wr_done_counts_s {
1602 #ifdef __BIG_ENDIAN_BITFIELD
1603         uint64_t reserved_32_63:32;
1604         uint64_t bad:16;
1605         uint64_t good:16;
1606 #else
1607         uint64_t good:16;
1608         uint64_t bad:16;
1609         uint64_t reserved_32_63:32;
1610 #endif
1611     } s;
1612 };
1613 
1614 #endif
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