asm/octeon/cvmx-spxx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_SPXX_DEFS_H__
0029 #define __CVMX_SPXX_DEFS_H__
0030
0031 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull)
0032 #define CVMX_SPXX_BIST_STAT(block_id) (CVMX_ADD_IO_SEG(0x00011800900007F8ull) + ((block_id) & 1) * 0x8000000ull)
0033 #define CVMX_SPXX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000348ull) + ((block_id) & 1) * 0x8000000ull)
0034 #define CVMX_SPXX_CLK_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000350ull) + ((block_id) & 1) * 0x8000000ull)
0035 #define CVMX_SPXX_DBG_DESKEW_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000368ull) + ((block_id) & 1) * 0x8000000ull)
0036 #define CVMX_SPXX_DBG_DESKEW_STATE(block_id) (CVMX_ADD_IO_SEG(0x0001180090000370ull) + ((block_id) & 1) * 0x8000000ull)
0037 #define CVMX_SPXX_DRV_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000358ull) + ((block_id) & 1) * 0x8000000ull)
0038 #define CVMX_SPXX_ERR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000320ull) + ((block_id) & 1) * 0x8000000ull)
0039 #define CVMX_SPXX_INT_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000318ull) + ((block_id) & 1) * 0x8000000ull)
0040 #define CVMX_SPXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180090000308ull) + ((block_id) & 1) * 0x8000000ull)
0041 #define CVMX_SPXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000300ull) + ((block_id) & 1) * 0x8000000ull)
0042 #define CVMX_SPXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000310ull) + ((block_id) & 1) * 0x8000000ull)
0043 #define CVMX_SPXX_TPA_ACC(block_id) (CVMX_ADD_IO_SEG(0x0001180090000338ull) + ((block_id) & 1) * 0x8000000ull)
0044 #define CVMX_SPXX_TPA_MAX(block_id) (CVMX_ADD_IO_SEG(0x0001180090000330ull) + ((block_id) & 1) * 0x8000000ull)
0045 #define CVMX_SPXX_TPA_SEL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000328ull) + ((block_id) & 1) * 0x8000000ull)
0046 #define CVMX_SPXX_TRN4_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000360ull) + ((block_id) & 1) * 0x8000000ull)
0047
0048 void __cvmx_interrupt_spxx_int_msk_enable(int index);
0049
0050 union cvmx_spxx_bckprs_cnt {
0051     uint64_t u64;
0052     struct cvmx_spxx_bckprs_cnt_s {
0053 #ifdef __BIG_ENDIAN_BITFIELD
0054         uint64_t reserved_32_63:32;
0055         uint64_t cnt:32;
0056 #else
0057         uint64_t cnt:32;
0058         uint64_t reserved_32_63:32;
0059 #endif
0060     } s;
0061 };
0062
0063 union cvmx_spxx_bist_stat {
0064     uint64_t u64;
0065     struct cvmx_spxx_bist_stat_s {
0066 #ifdef __BIG_ENDIAN_BITFIELD
0067         uint64_t reserved_3_63:61;
0068         uint64_t stat2:1;
0069         uint64_t stat1:1;
0070         uint64_t stat0:1;
0071 #else
0072         uint64_t stat0:1;
0073         uint64_t stat1:1;
0074         uint64_t stat2:1;
0075         uint64_t reserved_3_63:61;
0076 #endif
0077     } s;
0078 };
0079
0080 union cvmx_spxx_clk_ctl {
0081     uint64_t u64;
0082     struct cvmx_spxx_clk_ctl_s {
0083 #ifdef __BIG_ENDIAN_BITFIELD
0084         uint64_t reserved_17_63:47;
0085         uint64_t seetrn:1;
0086         uint64_t reserved_12_15:4;
0087         uint64_t clkdly:5;
0088         uint64_t runbist:1;
0089         uint64_t statdrv:1;
0090         uint64_t statrcv:1;
0091         uint64_t sndtrn:1;
0092         uint64_t drptrn:1;
0093         uint64_t rcvtrn:1;
0094         uint64_t srxdlck:1;
0095 #else
0096         uint64_t srxdlck:1;
0097         uint64_t rcvtrn:1;
0098         uint64_t drptrn:1;
0099         uint64_t sndtrn:1;
0100         uint64_t statrcv:1;
0101         uint64_t statdrv:1;
0102         uint64_t runbist:1;
0103         uint64_t clkdly:5;
0104         uint64_t reserved_12_15:4;
0105         uint64_t seetrn:1;
0106         uint64_t reserved_17_63:47;
0107 #endif
0108     } s;
0109 };
0110
0111 union cvmx_spxx_clk_stat {
0112     uint64_t u64;
0113     struct cvmx_spxx_clk_stat_s {
0114 #ifdef __BIG_ENDIAN_BITFIELD
0115         uint64_t reserved_11_63:53;
0116         uint64_t stxcal:1;
0117         uint64_t reserved_9_9:1;
0118         uint64_t srxtrn:1;
0119         uint64_t s4clk1:1;
0120         uint64_t s4clk0:1;
0121         uint64_t d4clk1:1;
0122         uint64_t d4clk0:1;
0123         uint64_t reserved_0_3:4;
0124 #else
0125         uint64_t reserved_0_3:4;
0126         uint64_t d4clk0:1;
0127         uint64_t d4clk1:1;
0128         uint64_t s4clk0:1;
0129         uint64_t s4clk1:1;
0130         uint64_t srxtrn:1;
0131         uint64_t reserved_9_9:1;
0132         uint64_t stxcal:1;
0133         uint64_t reserved_11_63:53;
0134 #endif
0135     } s;
0136 };
0137
0138 union cvmx_spxx_dbg_deskew_ctl {
0139     uint64_t u64;
0140     struct cvmx_spxx_dbg_deskew_ctl_s {
0141 #ifdef __BIG_ENDIAN_BITFIELD
0142         uint64_t reserved_30_63:34;
0143         uint64_t fallnop:1;
0144         uint64_t fall8:1;
0145         uint64_t reserved_26_27:2;
0146         uint64_t sstep_go:1;
0147         uint64_t sstep:1;
0148         uint64_t reserved_22_23:2;
0149         uint64_t clrdly:1;
0150         uint64_t dec:1;
0151         uint64_t inc:1;
0152         uint64_t mux:1;
0153         uint64_t offset:5;
0154         uint64_t bitsel:5;
0155         uint64_t offdly:6;
0156         uint64_t dllfrc:1;
0157         uint64_t dlldis:1;
0158 #else
0159         uint64_t dlldis:1;
0160         uint64_t dllfrc:1;
0161         uint64_t offdly:6;
0162         uint64_t bitsel:5;
0163         uint64_t offset:5;
0164         uint64_t mux:1;
0165         uint64_t inc:1;
0166         uint64_t dec:1;
0167         uint64_t clrdly:1;
0168         uint64_t reserved_22_23:2;
0169         uint64_t sstep:1;
0170         uint64_t sstep_go:1;
0171         uint64_t reserved_26_27:2;
0172         uint64_t fall8:1;
0173         uint64_t fallnop:1;
0174         uint64_t reserved_30_63:34;
0175 #endif
0176     } s;
0177 };
0178
0179 union cvmx_spxx_dbg_deskew_state {
0180     uint64_t u64;
0181     struct cvmx_spxx_dbg_deskew_state_s {
0182 #ifdef __BIG_ENDIAN_BITFIELD
0183         uint64_t reserved_9_63:55;
0184         uint64_t testres:1;
0185         uint64_t unxterm:1;
0186         uint64_t muxsel:2;
0187         uint64_t offset:5;
0188 #else
0189         uint64_t offset:5;
0190         uint64_t muxsel:2;
0191         uint64_t unxterm:1;
0192         uint64_t testres:1;
0193         uint64_t reserved_9_63:55;
0194 #endif
0195     } s;
0196 };
0197
0198 union cvmx_spxx_drv_ctl {
0199     uint64_t u64;
0200     struct cvmx_spxx_drv_ctl_s {
0201 #ifdef __BIG_ENDIAN_BITFIELD
0202         uint64_t reserved_0_63:64;
0203 #else
0204         uint64_t reserved_0_63:64;
0205 #endif
0206     } s;
0207     struct cvmx_spxx_drv_ctl_cn38xx {
0208 #ifdef __BIG_ENDIAN_BITFIELD
0209         uint64_t reserved_16_63:48;
0210         uint64_t stx4ncmp:4;
0211         uint64_t stx4pcmp:4;
0212         uint64_t srx4cmp:8;
0213 #else
0214         uint64_t srx4cmp:8;
0215         uint64_t stx4pcmp:4;
0216         uint64_t stx4ncmp:4;
0217         uint64_t reserved_16_63:48;
0218 #endif
0219     } cn38xx;
0220     struct cvmx_spxx_drv_ctl_cn58xx {
0221 #ifdef __BIG_ENDIAN_BITFIELD
0222         uint64_t reserved_24_63:40;
0223         uint64_t stx4ncmp:4;
0224         uint64_t stx4pcmp:4;
0225         uint64_t reserved_10_15:6;
0226         uint64_t srx4cmp:10;
0227 #else
0228         uint64_t srx4cmp:10;
0229         uint64_t reserved_10_15:6;
0230         uint64_t stx4pcmp:4;
0231         uint64_t stx4ncmp:4;
0232         uint64_t reserved_24_63:40;
0233 #endif
0234     } cn58xx;
0235 };
0236
0237 union cvmx_spxx_err_ctl {
0238     uint64_t u64;
0239     struct cvmx_spxx_err_ctl_s {
0240 #ifdef __BIG_ENDIAN_BITFIELD
0241         uint64_t reserved_9_63:55;
0242         uint64_t prtnxa:1;
0243         uint64_t dipcls:1;
0244         uint64_t dippay:1;
0245         uint64_t reserved_4_5:2;
0246         uint64_t errcnt:4;
0247 #else
0248         uint64_t errcnt:4;
0249         uint64_t reserved_4_5:2;
0250         uint64_t dippay:1;
0251         uint64_t dipcls:1;
0252         uint64_t prtnxa:1;
0253         uint64_t reserved_9_63:55;
0254 #endif
0255     } s;
0256 };
0257
0258 union cvmx_spxx_int_dat {
0259     uint64_t u64;
0260     struct cvmx_spxx_int_dat_s {
0261 #ifdef __BIG_ENDIAN_BITFIELD
0262         uint64_t reserved_32_63:32;
0263         uint64_t mul:1;
0264         uint64_t reserved_14_30:17;
0265         uint64_t calbnk:2;
0266         uint64_t rsvop:4;
0267         uint64_t prt:8;
0268 #else
0269         uint64_t prt:8;
0270         uint64_t rsvop:4;
0271         uint64_t calbnk:2;
0272         uint64_t reserved_14_30:17;
0273         uint64_t mul:1;
0274         uint64_t reserved_32_63:32;
0275 #endif
0276     } s;
0277 };
0278
0279 union cvmx_spxx_int_msk {
0280     uint64_t u64;
0281     struct cvmx_spxx_int_msk_s {
0282 #ifdef __BIG_ENDIAN_BITFIELD
0283         uint64_t reserved_12_63:52;
0284         uint64_t calerr:1;
0285         uint64_t syncerr:1;
0286         uint64_t diperr:1;
0287         uint64_t tpaovr:1;
0288         uint64_t rsverr:1;
0289         uint64_t drwnng:1;
0290         uint64_t clserr:1;
0291         uint64_t spiovr:1;
0292         uint64_t reserved_2_3:2;
0293         uint64_t abnorm:1;
0294         uint64_t prtnxa:1;
0295 #else
0296         uint64_t prtnxa:1;
0297         uint64_t abnorm:1;
0298         uint64_t reserved_2_3:2;
0299         uint64_t spiovr:1;
0300         uint64_t clserr:1;
0301         uint64_t drwnng:1;
0302         uint64_t rsverr:1;
0303         uint64_t tpaovr:1;
0304         uint64_t diperr:1;
0305         uint64_t syncerr:1;
0306         uint64_t calerr:1;
0307         uint64_t reserved_12_63:52;
0308 #endif
0309     } s;
0310 };
0311
0312 union cvmx_spxx_int_reg {
0313     uint64_t u64;
0314     struct cvmx_spxx_int_reg_s {
0315 #ifdef __BIG_ENDIAN_BITFIELD
0316         uint64_t reserved_32_63:32;
0317         uint64_t spf:1;
0318         uint64_t reserved_12_30:19;
0319         uint64_t calerr:1;
0320         uint64_t syncerr:1;
0321         uint64_t diperr:1;
0322         uint64_t tpaovr:1;
0323         uint64_t rsverr:1;
0324         uint64_t drwnng:1;
0325         uint64_t clserr:1;
0326         uint64_t spiovr:1;
0327         uint64_t reserved_2_3:2;
0328         uint64_t abnorm:1;
0329         uint64_t prtnxa:1;
0330 #else
0331         uint64_t prtnxa:1;
0332         uint64_t abnorm:1;
0333         uint64_t reserved_2_3:2;
0334         uint64_t spiovr:1;
0335         uint64_t clserr:1;
0336         uint64_t drwnng:1;
0337         uint64_t rsverr:1;
0338         uint64_t tpaovr:1;
0339         uint64_t diperr:1;
0340         uint64_t syncerr:1;
0341         uint64_t calerr:1;
0342         uint64_t reserved_12_30:19;
0343         uint64_t spf:1;
0344         uint64_t reserved_32_63:32;
0345 #endif
0346     } s;
0347 };
0348
0349 union cvmx_spxx_int_sync {
0350     uint64_t u64;
0351     struct cvmx_spxx_int_sync_s {
0352 #ifdef __BIG_ENDIAN_BITFIELD
0353         uint64_t reserved_12_63:52;
0354         uint64_t calerr:1;
0355         uint64_t syncerr:1;
0356         uint64_t diperr:1;
0357         uint64_t tpaovr:1;
0358         uint64_t rsverr:1;
0359         uint64_t drwnng:1;
0360         uint64_t clserr:1;
0361         uint64_t spiovr:1;
0362         uint64_t reserved_2_3:2;
0363         uint64_t abnorm:1;
0364         uint64_t prtnxa:1;
0365 #else
0366         uint64_t prtnxa:1;
0367         uint64_t abnorm:1;
0368         uint64_t reserved_2_3:2;
0369         uint64_t spiovr:1;
0370         uint64_t clserr:1;
0371         uint64_t drwnng:1;
0372         uint64_t rsverr:1;
0373         uint64_t tpaovr:1;
0374         uint64_t diperr:1;
0375         uint64_t syncerr:1;
0376         uint64_t calerr:1;
0377         uint64_t reserved_12_63:52;
0378 #endif
0379     } s;
0380 };
0381
0382 union cvmx_spxx_tpa_acc {
0383     uint64_t u64;
0384     struct cvmx_spxx_tpa_acc_s {
0385 #ifdef __BIG_ENDIAN_BITFIELD
0386         uint64_t reserved_32_63:32;
0387         uint64_t cnt:32;
0388 #else
0389         uint64_t cnt:32;
0390         uint64_t reserved_32_63:32;
0391 #endif
0392     } s;
0393 };
0394
0395 union cvmx_spxx_tpa_max {
0396     uint64_t u64;
0397     struct cvmx_spxx_tpa_max_s {
0398 #ifdef __BIG_ENDIAN_BITFIELD
0399         uint64_t reserved_32_63:32;
0400         uint64_t max:32;
0401 #else
0402         uint64_t max:32;
0403         uint64_t reserved_32_63:32;
0404 #endif
0405     } s;
0406 };
0407
0408 union cvmx_spxx_tpa_sel {
0409     uint64_t u64;
0410     struct cvmx_spxx_tpa_sel_s {
0411 #ifdef __BIG_ENDIAN_BITFIELD
0412         uint64_t reserved_4_63:60;
0413         uint64_t prtsel:4;
0414 #else
0415         uint64_t prtsel:4;
0416         uint64_t reserved_4_63:60;
0417 #endif
0418     } s;
0419 };
0420
0421 union cvmx_spxx_trn4_ctl {
0422     uint64_t u64;
0423     struct cvmx_spxx_trn4_ctl_s {
0424 #ifdef __BIG_ENDIAN_BITFIELD
0425         uint64_t reserved_13_63:51;
0426         uint64_t trntest:1;
0427         uint64_t jitter:3;
0428         uint64_t clr_boot:1;
0429         uint64_t set_boot:1;
0430         uint64_t maxdist:5;
0431         uint64_t macro_en:1;
0432         uint64_t mux_en:1;
0433 #else
0434         uint64_t mux_en:1;
0435         uint64_t macro_en:1;
0436         uint64_t maxdist:5;
0437         uint64_t set_boot:1;
0438         uint64_t clr_boot:1;
0439         uint64_t jitter:3;
0440         uint64_t trntest:1;
0441         uint64_t reserved_13_63:51;
0442 #endif
0443     } s;
0444 };
0445
0446 #endif