asm/octeon/cvmx-sli-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2017 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_SLI_DEFS_H__
0029 #define __CVMX_SLI_DEFS_H__
0030
0031 #include <uapi/asm/bitfield.h>
0032
0033 #define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
0034 static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
0035 {
0036     switch (cvmx_get_octeon_family()) {
0037     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0038     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0039     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0040     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0041     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0042     case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
0043         return 0x0000000000003CB0ull;
0044     case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
0045     case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
0046     case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
0047         if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
0048             return 0x0000000000003CB0ull;
0049         fallthrough;
0050     default:
0051         return 0x0000000000023CB0ull;
0052     }
0053 }
0054
0055
0056 union cvmx_sli_ctl_portx {
0057     uint64_t u64;
0058     struct cvmx_sli_ctl_portx_s {
0059         __BITFIELD_FIELD(uint64_t reserved_22_63:42,
0060         __BITFIELD_FIELD(uint64_t intd:1,
0061         __BITFIELD_FIELD(uint64_t intc:1,
0062         __BITFIELD_FIELD(uint64_t intb:1,
0063         __BITFIELD_FIELD(uint64_t inta:1,
0064         __BITFIELD_FIELD(uint64_t dis_port:1,
0065         __BITFIELD_FIELD(uint64_t waitl_com:1,
0066         __BITFIELD_FIELD(uint64_t intd_map:2,
0067         __BITFIELD_FIELD(uint64_t intc_map:2,
0068         __BITFIELD_FIELD(uint64_t intb_map:2,
0069         __BITFIELD_FIELD(uint64_t inta_map:2,
0070         __BITFIELD_FIELD(uint64_t ctlp_ro:1,
0071         __BITFIELD_FIELD(uint64_t reserved_6_6:1,
0072         __BITFIELD_FIELD(uint64_t ptlp_ro:1,
0073         __BITFIELD_FIELD(uint64_t reserved_1_4:4,
0074         __BITFIELD_FIELD(uint64_t wait_com:1,
0075         ;))))))))))))))))
0076     } s;
0077 };
0078
0079 union cvmx_sli_mem_access_ctl {
0080     uint64_t u64;
0081     struct cvmx_sli_mem_access_ctl_s {
0082         __BITFIELD_FIELD(uint64_t reserved_14_63:50,
0083         __BITFIELD_FIELD(uint64_t max_word:4,
0084         __BITFIELD_FIELD(uint64_t timer:10,
0085         ;)))
0086     } s;
0087 };
0088
0089 union cvmx_sli_s2m_portx_ctl {
0090     uint64_t u64;
0091     struct cvmx_sli_s2m_portx_ctl_s {
0092         __BITFIELD_FIELD(uint64_t reserved_5_63:59,
0093         __BITFIELD_FIELD(uint64_t wind_d:1,
0094         __BITFIELD_FIELD(uint64_t bar0_d:1,
0095         __BITFIELD_FIELD(uint64_t mrrs:3,
0096         ;))))
0097     } s;
0098 };
0099
0100 union cvmx_sli_mem_access_subidx {
0101     uint64_t u64;
0102     struct cvmx_sli_mem_access_subidx_s {
0103         __BITFIELD_FIELD(uint64_t reserved_43_63:21,
0104         __BITFIELD_FIELD(uint64_t zero:1,
0105         __BITFIELD_FIELD(uint64_t port:3,
0106         __BITFIELD_FIELD(uint64_t nmerge:1,
0107         __BITFIELD_FIELD(uint64_t esr:2,
0108         __BITFIELD_FIELD(uint64_t esw:2,
0109         __BITFIELD_FIELD(uint64_t wtype:2,
0110         __BITFIELD_FIELD(uint64_t rtype:2,
0111         __BITFIELD_FIELD(uint64_t ba:30,
0112         ;)))))))))
0113     } s;
0114     struct cvmx_sli_mem_access_subidx_cn68xx {
0115         __BITFIELD_FIELD(uint64_t reserved_43_63:21,
0116         __BITFIELD_FIELD(uint64_t zero:1,
0117         __BITFIELD_FIELD(uint64_t port:3,
0118         __BITFIELD_FIELD(uint64_t nmerge:1,
0119         __BITFIELD_FIELD(uint64_t esr:2,
0120         __BITFIELD_FIELD(uint64_t esw:2,
0121         __BITFIELD_FIELD(uint64_t wtype:2,
0122         __BITFIELD_FIELD(uint64_t rtype:2,
0123         __BITFIELD_FIELD(uint64_t ba:28,
0124         __BITFIELD_FIELD(uint64_t reserved_0_1:2,
0125         ;))))))))))
0126     } cn68xx;
0127 };
0128
0129 #endif