asm/octeon/cvmx-rst-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Inc.
0003  *
0004  * Contact: support@cavium.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2014 Cavium Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Inc. for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_RST_DEFS_H__
0029 #define __CVMX_RST_DEFS_H__
0030
0031 #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
0032 #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
0033 #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
0034 #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
0035 #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
0036 #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
0037 #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
0038 #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
0039 #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
0040 #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
0041 #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
0042 #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
0043
0044 union cvmx_rst_boot {
0045     uint64_t u64;
0046     struct cvmx_rst_boot_s {
0047 #ifdef __BIG_ENDIAN_BITFIELD
0048         uint64_t chipkill:1;
0049         uint64_t jtcsrdis:1;
0050         uint64_t ejtagdis:1;
0051         uint64_t romen:1;
0052         uint64_t ckill_ppdis:1;
0053         uint64_t jt_tstmode:1;
0054         uint64_t vrm_err:1;
0055         uint64_t reserved_37_56:20;
0056         uint64_t c_mul:7;
0057         uint64_t pnr_mul:6;
0058         uint64_t reserved_21_23:3;
0059         uint64_t lboot_oci:3;
0060         uint64_t lboot_ext:6;
0061         uint64_t lboot:10;
0062         uint64_t rboot:1;
0063         uint64_t rboot_pin:1;
0064 #else
0065         uint64_t rboot_pin:1;
0066         uint64_t rboot:1;
0067         uint64_t lboot:10;
0068         uint64_t lboot_ext:6;
0069         uint64_t lboot_oci:3;
0070         uint64_t reserved_21_23:3;
0071         uint64_t pnr_mul:6;
0072         uint64_t c_mul:7;
0073         uint64_t reserved_37_56:20;
0074         uint64_t vrm_err:1;
0075         uint64_t jt_tstmode:1;
0076         uint64_t ckill_ppdis:1;
0077         uint64_t romen:1;
0078         uint64_t ejtagdis:1;
0079         uint64_t jtcsrdis:1;
0080         uint64_t chipkill:1;
0081 #endif
0082     } s;
0083 };
0084
0085 union cvmx_rst_cfg {
0086     uint64_t u64;
0087     struct cvmx_rst_cfg_s {
0088 #ifdef __BIG_ENDIAN_BITFIELD
0089         uint64_t bist_delay:58;
0090         uint64_t reserved_3_5:3;
0091         uint64_t cntl_clr_bist:1;
0092         uint64_t warm_clr_bist:1;
0093         uint64_t soft_clr_bist:1;
0094 #else
0095         uint64_t soft_clr_bist:1;
0096         uint64_t warm_clr_bist:1;
0097         uint64_t cntl_clr_bist:1;
0098         uint64_t reserved_3_5:3;
0099         uint64_t bist_delay:58;
0100 #endif
0101     } s;
0102 };
0103
0104 union cvmx_rst_ckill {
0105     uint64_t u64;
0106     struct cvmx_rst_ckill_s {
0107 #ifdef __BIG_ENDIAN_BITFIELD
0108         uint64_t reserved_47_63:17;
0109         uint64_t timer:47;
0110 #else
0111         uint64_t timer:47;
0112         uint64_t reserved_47_63:17;
0113 #endif
0114     } s;
0115 };
0116
0117 union cvmx_rst_ctlx {
0118     uint64_t u64;
0119     struct cvmx_rst_ctlx_s {
0120 #ifdef __BIG_ENDIAN_BITFIELD
0121         uint64_t reserved_10_63:54;
0122         uint64_t prst_link:1;
0123         uint64_t rst_done:1;
0124         uint64_t rst_link:1;
0125         uint64_t host_mode:1;
0126         uint64_t reserved_4_5:2;
0127         uint64_t rst_drv:1;
0128         uint64_t rst_rcv:1;
0129         uint64_t rst_chip:1;
0130         uint64_t rst_val:1;
0131 #else
0132         uint64_t rst_val:1;
0133         uint64_t rst_chip:1;
0134         uint64_t rst_rcv:1;
0135         uint64_t rst_drv:1;
0136         uint64_t reserved_4_5:2;
0137         uint64_t host_mode:1;
0138         uint64_t rst_link:1;
0139         uint64_t rst_done:1;
0140         uint64_t prst_link:1;
0141         uint64_t reserved_10_63:54;
0142 #endif
0143     } s;
0144 };
0145
0146 union cvmx_rst_delay {
0147     uint64_t u64;
0148     struct cvmx_rst_delay_s {
0149 #ifdef __BIG_ENDIAN_BITFIELD
0150         uint64_t reserved_32_63:32;
0151         uint64_t warm_rst_dly:16;
0152         uint64_t soft_rst_dly:16;
0153 #else
0154         uint64_t soft_rst_dly:16;
0155         uint64_t warm_rst_dly:16;
0156         uint64_t reserved_32_63:32;
0157 #endif
0158     } s;
0159 };
0160
0161 union cvmx_rst_eco {
0162     uint64_t u64;
0163     struct cvmx_rst_eco_s {
0164 #ifdef __BIG_ENDIAN_BITFIELD
0165         uint64_t reserved_32_63:32;
0166         uint64_t eco_rw:32;
0167 #else
0168         uint64_t eco_rw:32;
0169         uint64_t reserved_32_63:32;
0170 #endif
0171     } s;
0172 };
0173
0174 union cvmx_rst_int {
0175     uint64_t u64;
0176     struct cvmx_rst_int_s {
0177 #ifdef __BIG_ENDIAN_BITFIELD
0178         uint64_t reserved_12_63:52;
0179         uint64_t perst:4;
0180         uint64_t reserved_4_7:4;
0181         uint64_t rst_link:4;
0182 #else
0183         uint64_t rst_link:4;
0184         uint64_t reserved_4_7:4;
0185         uint64_t perst:4;
0186         uint64_t reserved_12_63:52;
0187 #endif
0188     } s;
0189     struct cvmx_rst_int_cn70xx {
0190 #ifdef __BIG_ENDIAN_BITFIELD
0191         uint64_t reserved_11_63:53;
0192         uint64_t perst:3;
0193         uint64_t reserved_3_7:5;
0194         uint64_t rst_link:3;
0195 #else
0196         uint64_t rst_link:3;
0197         uint64_t reserved_3_7:5;
0198         uint64_t perst:3;
0199         uint64_t reserved_11_63:53;
0200 #endif
0201     } cn70xx;
0202 };
0203
0204 union cvmx_rst_ocx {
0205     uint64_t u64;
0206     struct cvmx_rst_ocx_s {
0207 #ifdef __BIG_ENDIAN_BITFIELD
0208         uint64_t reserved_3_63:61;
0209         uint64_t rst_link:3;
0210 #else
0211         uint64_t rst_link:3;
0212         uint64_t reserved_3_63:61;
0213 #endif
0214     } s;
0215 };
0216
0217 union cvmx_rst_power_dbg {
0218     uint64_t u64;
0219     struct cvmx_rst_power_dbg_s {
0220 #ifdef __BIG_ENDIAN_BITFIELD
0221         uint64_t reserved_3_63:61;
0222         uint64_t str:3;
0223 #else
0224         uint64_t str:3;
0225         uint64_t reserved_3_63:61;
0226 #endif
0227     } s;
0228 };
0229
0230 union cvmx_rst_pp_power {
0231     uint64_t u64;
0232     struct cvmx_rst_pp_power_s {
0233 #ifdef __BIG_ENDIAN_BITFIELD
0234         uint64_t reserved_48_63:16;
0235         uint64_t gate:48;
0236 #else
0237         uint64_t gate:48;
0238         uint64_t reserved_48_63:16;
0239 #endif
0240     } s;
0241     struct cvmx_rst_pp_power_cn70xx {
0242 #ifdef __BIG_ENDIAN_BITFIELD
0243         uint64_t reserved_4_63:60;
0244         uint64_t gate:4;
0245 #else
0246         uint64_t gate:4;
0247         uint64_t reserved_4_63:60;
0248 #endif
0249     } cn70xx;
0250 };
0251
0252 union cvmx_rst_soft_prstx {
0253     uint64_t u64;
0254     struct cvmx_rst_soft_prstx_s {
0255 #ifdef __BIG_ENDIAN_BITFIELD
0256         uint64_t reserved_1_63:63;
0257         uint64_t soft_prst:1;
0258 #else
0259         uint64_t soft_prst:1;
0260         uint64_t reserved_1_63:63;
0261 #endif
0262     } s;
0263 };
0264
0265 union cvmx_rst_soft_rst {
0266     uint64_t u64;
0267     struct cvmx_rst_soft_rst_s {
0268 #ifdef __BIG_ENDIAN_BITFIELD
0269         uint64_t reserved_1_63:63;
0270         uint64_t soft_rst:1;
0271 #else
0272         uint64_t soft_rst:1;
0273         uint64_t reserved_1_63:63;
0274 #endif
0275     } s;
0276 };
0277
0278 #endif