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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_POW_DEFS_H__
0029 #define __CVMX_POW_DEFS_H__
0030 
0031 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
0032 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
0033 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
0034 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
0035 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
0036 #define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
0037 #define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
0038 #define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
0039 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
0040 #define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
0041 #define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
0042 #define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
0043 #define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
0044 #define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
0045 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
0046 #define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
0047 #define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
0048 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
0049 #define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
0050 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
0051 #define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
0052 #define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
0053 #define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
0054 
0055 #define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
0056 #define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
0057 #define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
0058 #define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
0059 #define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
0060 
0061 union cvmx_pow_bist_stat {
0062     uint64_t u64;
0063     struct cvmx_pow_bist_stat_s {
0064 #ifdef __BIG_ENDIAN_BITFIELD
0065         uint64_t reserved_32_63:32;
0066         uint64_t pp:16;
0067         uint64_t reserved_0_15:16;
0068 #else
0069         uint64_t reserved_0_15:16;
0070         uint64_t pp:16;
0071         uint64_t reserved_32_63:32;
0072 #endif
0073     } s;
0074     struct cvmx_pow_bist_stat_cn30xx {
0075 #ifdef __BIG_ENDIAN_BITFIELD
0076         uint64_t reserved_17_63:47;
0077         uint64_t pp:1;
0078         uint64_t reserved_9_15:7;
0079         uint64_t cam:1;
0080         uint64_t nbt1:1;
0081         uint64_t nbt0:1;
0082         uint64_t index:1;
0083         uint64_t fidx:1;
0084         uint64_t nbr1:1;
0085         uint64_t nbr0:1;
0086         uint64_t pend:1;
0087         uint64_t adr:1;
0088 #else
0089         uint64_t adr:1;
0090         uint64_t pend:1;
0091         uint64_t nbr0:1;
0092         uint64_t nbr1:1;
0093         uint64_t fidx:1;
0094         uint64_t index:1;
0095         uint64_t nbt0:1;
0096         uint64_t nbt1:1;
0097         uint64_t cam:1;
0098         uint64_t reserved_9_15:7;
0099         uint64_t pp:1;
0100         uint64_t reserved_17_63:47;
0101 #endif
0102     } cn30xx;
0103     struct cvmx_pow_bist_stat_cn31xx {
0104 #ifdef __BIG_ENDIAN_BITFIELD
0105         uint64_t reserved_18_63:46;
0106         uint64_t pp:2;
0107         uint64_t reserved_9_15:7;
0108         uint64_t cam:1;
0109         uint64_t nbt1:1;
0110         uint64_t nbt0:1;
0111         uint64_t index:1;
0112         uint64_t fidx:1;
0113         uint64_t nbr1:1;
0114         uint64_t nbr0:1;
0115         uint64_t pend:1;
0116         uint64_t adr:1;
0117 #else
0118         uint64_t adr:1;
0119         uint64_t pend:1;
0120         uint64_t nbr0:1;
0121         uint64_t nbr1:1;
0122         uint64_t fidx:1;
0123         uint64_t index:1;
0124         uint64_t nbt0:1;
0125         uint64_t nbt1:1;
0126         uint64_t cam:1;
0127         uint64_t reserved_9_15:7;
0128         uint64_t pp:2;
0129         uint64_t reserved_18_63:46;
0130 #endif
0131     } cn31xx;
0132     struct cvmx_pow_bist_stat_cn38xx {
0133 #ifdef __BIG_ENDIAN_BITFIELD
0134         uint64_t reserved_32_63:32;
0135         uint64_t pp:16;
0136         uint64_t reserved_10_15:6;
0137         uint64_t cam:1;
0138         uint64_t nbt:1;
0139         uint64_t index:1;
0140         uint64_t fidx:1;
0141         uint64_t nbr1:1;
0142         uint64_t nbr0:1;
0143         uint64_t pend1:1;
0144         uint64_t pend0:1;
0145         uint64_t adr1:1;
0146         uint64_t adr0:1;
0147 #else
0148         uint64_t adr0:1;
0149         uint64_t adr1:1;
0150         uint64_t pend0:1;
0151         uint64_t pend1:1;
0152         uint64_t nbr0:1;
0153         uint64_t nbr1:1;
0154         uint64_t fidx:1;
0155         uint64_t index:1;
0156         uint64_t nbt:1;
0157         uint64_t cam:1;
0158         uint64_t reserved_10_15:6;
0159         uint64_t pp:16;
0160         uint64_t reserved_32_63:32;
0161 #endif
0162     } cn38xx;
0163     struct cvmx_pow_bist_stat_cn52xx {
0164 #ifdef __BIG_ENDIAN_BITFIELD
0165         uint64_t reserved_20_63:44;
0166         uint64_t pp:4;
0167         uint64_t reserved_9_15:7;
0168         uint64_t cam:1;
0169         uint64_t nbt1:1;
0170         uint64_t nbt0:1;
0171         uint64_t index:1;
0172         uint64_t fidx:1;
0173         uint64_t nbr1:1;
0174         uint64_t nbr0:1;
0175         uint64_t pend:1;
0176         uint64_t adr:1;
0177 #else
0178         uint64_t adr:1;
0179         uint64_t pend:1;
0180         uint64_t nbr0:1;
0181         uint64_t nbr1:1;
0182         uint64_t fidx:1;
0183         uint64_t index:1;
0184         uint64_t nbt0:1;
0185         uint64_t nbt1:1;
0186         uint64_t cam:1;
0187         uint64_t reserved_9_15:7;
0188         uint64_t pp:4;
0189         uint64_t reserved_20_63:44;
0190 #endif
0191     } cn52xx;
0192     struct cvmx_pow_bist_stat_cn56xx {
0193 #ifdef __BIG_ENDIAN_BITFIELD
0194         uint64_t reserved_28_63:36;
0195         uint64_t pp:12;
0196         uint64_t reserved_10_15:6;
0197         uint64_t cam:1;
0198         uint64_t nbt:1;
0199         uint64_t index:1;
0200         uint64_t fidx:1;
0201         uint64_t nbr1:1;
0202         uint64_t nbr0:1;
0203         uint64_t pend1:1;
0204         uint64_t pend0:1;
0205         uint64_t adr1:1;
0206         uint64_t adr0:1;
0207 #else
0208         uint64_t adr0:1;
0209         uint64_t adr1:1;
0210         uint64_t pend0:1;
0211         uint64_t pend1:1;
0212         uint64_t nbr0:1;
0213         uint64_t nbr1:1;
0214         uint64_t fidx:1;
0215         uint64_t index:1;
0216         uint64_t nbt:1;
0217         uint64_t cam:1;
0218         uint64_t reserved_10_15:6;
0219         uint64_t pp:12;
0220         uint64_t reserved_28_63:36;
0221 #endif
0222     } cn56xx;
0223     struct cvmx_pow_bist_stat_cn61xx {
0224 #ifdef __BIG_ENDIAN_BITFIELD
0225         uint64_t reserved_20_63:44;
0226         uint64_t pp:4;
0227         uint64_t reserved_12_15:4;
0228         uint64_t cam:1;
0229         uint64_t nbr:3;
0230         uint64_t nbt:4;
0231         uint64_t index:1;
0232         uint64_t fidx:1;
0233         uint64_t pend:1;
0234         uint64_t adr:1;
0235 #else
0236         uint64_t adr:1;
0237         uint64_t pend:1;
0238         uint64_t fidx:1;
0239         uint64_t index:1;
0240         uint64_t nbt:4;
0241         uint64_t nbr:3;
0242         uint64_t cam:1;
0243         uint64_t reserved_12_15:4;
0244         uint64_t pp:4;
0245         uint64_t reserved_20_63:44;
0246 #endif
0247     } cn61xx;
0248     struct cvmx_pow_bist_stat_cn63xx {
0249 #ifdef __BIG_ENDIAN_BITFIELD
0250         uint64_t reserved_22_63:42;
0251         uint64_t pp:6;
0252         uint64_t reserved_12_15:4;
0253         uint64_t cam:1;
0254         uint64_t nbr:3;
0255         uint64_t nbt:4;
0256         uint64_t index:1;
0257         uint64_t fidx:1;
0258         uint64_t pend:1;
0259         uint64_t adr:1;
0260 #else
0261         uint64_t adr:1;
0262         uint64_t pend:1;
0263         uint64_t fidx:1;
0264         uint64_t index:1;
0265         uint64_t nbt:4;
0266         uint64_t nbr:3;
0267         uint64_t cam:1;
0268         uint64_t reserved_12_15:4;
0269         uint64_t pp:6;
0270         uint64_t reserved_22_63:42;
0271 #endif
0272     } cn63xx;
0273     struct cvmx_pow_bist_stat_cn66xx {
0274 #ifdef __BIG_ENDIAN_BITFIELD
0275         uint64_t reserved_26_63:38;
0276         uint64_t pp:10;
0277         uint64_t reserved_12_15:4;
0278         uint64_t cam:1;
0279         uint64_t nbr:3;
0280         uint64_t nbt:4;
0281         uint64_t index:1;
0282         uint64_t fidx:1;
0283         uint64_t pend:1;
0284         uint64_t adr:1;
0285 #else
0286         uint64_t adr:1;
0287         uint64_t pend:1;
0288         uint64_t fidx:1;
0289         uint64_t index:1;
0290         uint64_t nbt:4;
0291         uint64_t nbr:3;
0292         uint64_t cam:1;
0293         uint64_t reserved_12_15:4;
0294         uint64_t pp:10;
0295         uint64_t reserved_26_63:38;
0296 #endif
0297     } cn66xx;
0298 };
0299 
0300 union cvmx_pow_ds_pc {
0301     uint64_t u64;
0302     struct cvmx_pow_ds_pc_s {
0303 #ifdef __BIG_ENDIAN_BITFIELD
0304         uint64_t reserved_32_63:32;
0305         uint64_t ds_pc:32;
0306 #else
0307         uint64_t ds_pc:32;
0308         uint64_t reserved_32_63:32;
0309 #endif
0310     } s;
0311 };
0312 
0313 union cvmx_pow_ecc_err {
0314     uint64_t u64;
0315     struct cvmx_pow_ecc_err_s {
0316 #ifdef __BIG_ENDIAN_BITFIELD
0317         uint64_t reserved_45_63:19;
0318         uint64_t iop_ie:13;
0319         uint64_t reserved_29_31:3;
0320         uint64_t iop:13;
0321         uint64_t reserved_14_15:2;
0322         uint64_t rpe_ie:1;
0323         uint64_t rpe:1;
0324         uint64_t reserved_9_11:3;
0325         uint64_t syn:5;
0326         uint64_t dbe_ie:1;
0327         uint64_t sbe_ie:1;
0328         uint64_t dbe:1;
0329         uint64_t sbe:1;
0330 #else
0331         uint64_t sbe:1;
0332         uint64_t dbe:1;
0333         uint64_t sbe_ie:1;
0334         uint64_t dbe_ie:1;
0335         uint64_t syn:5;
0336         uint64_t reserved_9_11:3;
0337         uint64_t rpe:1;
0338         uint64_t rpe_ie:1;
0339         uint64_t reserved_14_15:2;
0340         uint64_t iop:13;
0341         uint64_t reserved_29_31:3;
0342         uint64_t iop_ie:13;
0343         uint64_t reserved_45_63:19;
0344 #endif
0345     } s;
0346     struct cvmx_pow_ecc_err_cn31xx {
0347 #ifdef __BIG_ENDIAN_BITFIELD
0348         uint64_t reserved_14_63:50;
0349         uint64_t rpe_ie:1;
0350         uint64_t rpe:1;
0351         uint64_t reserved_9_11:3;
0352         uint64_t syn:5;
0353         uint64_t dbe_ie:1;
0354         uint64_t sbe_ie:1;
0355         uint64_t dbe:1;
0356         uint64_t sbe:1;
0357 #else
0358         uint64_t sbe:1;
0359         uint64_t dbe:1;
0360         uint64_t sbe_ie:1;
0361         uint64_t dbe_ie:1;
0362         uint64_t syn:5;
0363         uint64_t reserved_9_11:3;
0364         uint64_t rpe:1;
0365         uint64_t rpe_ie:1;
0366         uint64_t reserved_14_63:50;
0367 #endif
0368     } cn31xx;
0369 };
0370 
0371 union cvmx_pow_int_ctl {
0372     uint64_t u64;
0373     struct cvmx_pow_int_ctl_s {
0374 #ifdef __BIG_ENDIAN_BITFIELD
0375         uint64_t reserved_6_63:58;
0376         uint64_t pfr_dis:1;
0377         uint64_t nbr_thr:5;
0378 #else
0379         uint64_t nbr_thr:5;
0380         uint64_t pfr_dis:1;
0381         uint64_t reserved_6_63:58;
0382 #endif
0383     } s;
0384 };
0385 
0386 union cvmx_pow_iq_cntx {
0387     uint64_t u64;
0388     struct cvmx_pow_iq_cntx_s {
0389 #ifdef __BIG_ENDIAN_BITFIELD
0390         uint64_t reserved_32_63:32;
0391         uint64_t iq_cnt:32;
0392 #else
0393         uint64_t iq_cnt:32;
0394         uint64_t reserved_32_63:32;
0395 #endif
0396     } s;
0397 };
0398 
0399 union cvmx_pow_iq_com_cnt {
0400     uint64_t u64;
0401     struct cvmx_pow_iq_com_cnt_s {
0402 #ifdef __BIG_ENDIAN_BITFIELD
0403         uint64_t reserved_32_63:32;
0404         uint64_t iq_cnt:32;
0405 #else
0406         uint64_t iq_cnt:32;
0407         uint64_t reserved_32_63:32;
0408 #endif
0409     } s;
0410 };
0411 
0412 union cvmx_pow_iq_int {
0413     uint64_t u64;
0414     struct cvmx_pow_iq_int_s {
0415 #ifdef __BIG_ENDIAN_BITFIELD
0416         uint64_t reserved_8_63:56;
0417         uint64_t iq_int:8;
0418 #else
0419         uint64_t iq_int:8;
0420         uint64_t reserved_8_63:56;
0421 #endif
0422     } s;
0423 };
0424 
0425 union cvmx_pow_iq_int_en {
0426     uint64_t u64;
0427     struct cvmx_pow_iq_int_en_s {
0428 #ifdef __BIG_ENDIAN_BITFIELD
0429         uint64_t reserved_8_63:56;
0430         uint64_t int_en:8;
0431 #else
0432         uint64_t int_en:8;
0433         uint64_t reserved_8_63:56;
0434 #endif
0435     } s;
0436 };
0437 
0438 union cvmx_pow_iq_thrx {
0439     uint64_t u64;
0440     struct cvmx_pow_iq_thrx_s {
0441 #ifdef __BIG_ENDIAN_BITFIELD
0442         uint64_t reserved_32_63:32;
0443         uint64_t iq_thr:32;
0444 #else
0445         uint64_t iq_thr:32;
0446         uint64_t reserved_32_63:32;
0447 #endif
0448     } s;
0449 };
0450 
0451 union cvmx_pow_nos_cnt {
0452     uint64_t u64;
0453     struct cvmx_pow_nos_cnt_s {
0454 #ifdef __BIG_ENDIAN_BITFIELD
0455         uint64_t reserved_12_63:52;
0456         uint64_t nos_cnt:12;
0457 #else
0458         uint64_t nos_cnt:12;
0459         uint64_t reserved_12_63:52;
0460 #endif
0461     } s;
0462     struct cvmx_pow_nos_cnt_cn30xx {
0463 #ifdef __BIG_ENDIAN_BITFIELD
0464         uint64_t reserved_7_63:57;
0465         uint64_t nos_cnt:7;
0466 #else
0467         uint64_t nos_cnt:7;
0468         uint64_t reserved_7_63:57;
0469 #endif
0470     } cn30xx;
0471     struct cvmx_pow_nos_cnt_cn31xx {
0472 #ifdef __BIG_ENDIAN_BITFIELD
0473         uint64_t reserved_9_63:55;
0474         uint64_t nos_cnt:9;
0475 #else
0476         uint64_t nos_cnt:9;
0477         uint64_t reserved_9_63:55;
0478 #endif
0479     } cn31xx;
0480     struct cvmx_pow_nos_cnt_cn52xx {
0481 #ifdef __BIG_ENDIAN_BITFIELD
0482         uint64_t reserved_10_63:54;
0483         uint64_t nos_cnt:10;
0484 #else
0485         uint64_t nos_cnt:10;
0486         uint64_t reserved_10_63:54;
0487 #endif
0488     } cn52xx;
0489     struct cvmx_pow_nos_cnt_cn63xx {
0490 #ifdef __BIG_ENDIAN_BITFIELD
0491         uint64_t reserved_11_63:53;
0492         uint64_t nos_cnt:11;
0493 #else
0494         uint64_t nos_cnt:11;
0495         uint64_t reserved_11_63:53;
0496 #endif
0497     } cn63xx;
0498 };
0499 
0500 union cvmx_pow_nw_tim {
0501     uint64_t u64;
0502     struct cvmx_pow_nw_tim_s {
0503 #ifdef __BIG_ENDIAN_BITFIELD
0504         uint64_t reserved_10_63:54;
0505         uint64_t nw_tim:10;
0506 #else
0507         uint64_t nw_tim:10;
0508         uint64_t reserved_10_63:54;
0509 #endif
0510     } s;
0511 };
0512 
0513 union cvmx_pow_pf_rst_msk {
0514     uint64_t u64;
0515     struct cvmx_pow_pf_rst_msk_s {
0516 #ifdef __BIG_ENDIAN_BITFIELD
0517         uint64_t reserved_8_63:56;
0518         uint64_t rst_msk:8;
0519 #else
0520         uint64_t rst_msk:8;
0521         uint64_t reserved_8_63:56;
0522 #endif
0523     } s;
0524 };
0525 
0526 union cvmx_pow_pp_grp_mskx {
0527     uint64_t u64;
0528     struct cvmx_pow_pp_grp_mskx_s {
0529 #ifdef __BIG_ENDIAN_BITFIELD
0530         uint64_t reserved_48_63:16;
0531         uint64_t qos7_pri:4;
0532         uint64_t qos6_pri:4;
0533         uint64_t qos5_pri:4;
0534         uint64_t qos4_pri:4;
0535         uint64_t qos3_pri:4;
0536         uint64_t qos2_pri:4;
0537         uint64_t qos1_pri:4;
0538         uint64_t qos0_pri:4;
0539         uint64_t grp_msk:16;
0540 #else
0541         uint64_t grp_msk:16;
0542         uint64_t qos0_pri:4;
0543         uint64_t qos1_pri:4;
0544         uint64_t qos2_pri:4;
0545         uint64_t qos3_pri:4;
0546         uint64_t qos4_pri:4;
0547         uint64_t qos5_pri:4;
0548         uint64_t qos6_pri:4;
0549         uint64_t qos7_pri:4;
0550         uint64_t reserved_48_63:16;
0551 #endif
0552     } s;
0553     struct cvmx_pow_pp_grp_mskx_cn30xx {
0554 #ifdef __BIG_ENDIAN_BITFIELD
0555         uint64_t reserved_16_63:48;
0556         uint64_t grp_msk:16;
0557 #else
0558         uint64_t grp_msk:16;
0559         uint64_t reserved_16_63:48;
0560 #endif
0561     } cn30xx;
0562 };
0563 
0564 union cvmx_pow_qos_rndx {
0565     uint64_t u64;
0566     struct cvmx_pow_qos_rndx_s {
0567 #ifdef __BIG_ENDIAN_BITFIELD
0568         uint64_t reserved_32_63:32;
0569         uint64_t rnd_p3:8;
0570         uint64_t rnd_p2:8;
0571         uint64_t rnd_p1:8;
0572         uint64_t rnd:8;
0573 #else
0574         uint64_t rnd:8;
0575         uint64_t rnd_p1:8;
0576         uint64_t rnd_p2:8;
0577         uint64_t rnd_p3:8;
0578         uint64_t reserved_32_63:32;
0579 #endif
0580     } s;
0581 };
0582 
0583 union cvmx_pow_qos_thrx {
0584     uint64_t u64;
0585     struct cvmx_pow_qos_thrx_s {
0586 #ifdef __BIG_ENDIAN_BITFIELD
0587         uint64_t reserved_60_63:4;
0588         uint64_t des_cnt:12;
0589         uint64_t buf_cnt:12;
0590         uint64_t free_cnt:12;
0591         uint64_t reserved_23_23:1;
0592         uint64_t max_thr:11;
0593         uint64_t reserved_11_11:1;
0594         uint64_t min_thr:11;
0595 #else
0596         uint64_t min_thr:11;
0597         uint64_t reserved_11_11:1;
0598         uint64_t max_thr:11;
0599         uint64_t reserved_23_23:1;
0600         uint64_t free_cnt:12;
0601         uint64_t buf_cnt:12;
0602         uint64_t des_cnt:12;
0603         uint64_t reserved_60_63:4;
0604 #endif
0605     } s;
0606     struct cvmx_pow_qos_thrx_cn30xx {
0607 #ifdef __BIG_ENDIAN_BITFIELD
0608         uint64_t reserved_55_63:9;
0609         uint64_t des_cnt:7;
0610         uint64_t reserved_43_47:5;
0611         uint64_t buf_cnt:7;
0612         uint64_t reserved_31_35:5;
0613         uint64_t free_cnt:7;
0614         uint64_t reserved_18_23:6;
0615         uint64_t max_thr:6;
0616         uint64_t reserved_6_11:6;
0617         uint64_t min_thr:6;
0618 #else
0619         uint64_t min_thr:6;
0620         uint64_t reserved_6_11:6;
0621         uint64_t max_thr:6;
0622         uint64_t reserved_18_23:6;
0623         uint64_t free_cnt:7;
0624         uint64_t reserved_31_35:5;
0625         uint64_t buf_cnt:7;
0626         uint64_t reserved_43_47:5;
0627         uint64_t des_cnt:7;
0628         uint64_t reserved_55_63:9;
0629 #endif
0630     } cn30xx;
0631     struct cvmx_pow_qos_thrx_cn31xx {
0632 #ifdef __BIG_ENDIAN_BITFIELD
0633         uint64_t reserved_57_63:7;
0634         uint64_t des_cnt:9;
0635         uint64_t reserved_45_47:3;
0636         uint64_t buf_cnt:9;
0637         uint64_t reserved_33_35:3;
0638         uint64_t free_cnt:9;
0639         uint64_t reserved_20_23:4;
0640         uint64_t max_thr:8;
0641         uint64_t reserved_8_11:4;
0642         uint64_t min_thr:8;
0643 #else
0644         uint64_t min_thr:8;
0645         uint64_t reserved_8_11:4;
0646         uint64_t max_thr:8;
0647         uint64_t reserved_20_23:4;
0648         uint64_t free_cnt:9;
0649         uint64_t reserved_33_35:3;
0650         uint64_t buf_cnt:9;
0651         uint64_t reserved_45_47:3;
0652         uint64_t des_cnt:9;
0653         uint64_t reserved_57_63:7;
0654 #endif
0655     } cn31xx;
0656     struct cvmx_pow_qos_thrx_cn52xx {
0657 #ifdef __BIG_ENDIAN_BITFIELD
0658         uint64_t reserved_58_63:6;
0659         uint64_t des_cnt:10;
0660         uint64_t reserved_46_47:2;
0661         uint64_t buf_cnt:10;
0662         uint64_t reserved_34_35:2;
0663         uint64_t free_cnt:10;
0664         uint64_t reserved_21_23:3;
0665         uint64_t max_thr:9;
0666         uint64_t reserved_9_11:3;
0667         uint64_t min_thr:9;
0668 #else
0669         uint64_t min_thr:9;
0670         uint64_t reserved_9_11:3;
0671         uint64_t max_thr:9;
0672         uint64_t reserved_21_23:3;
0673         uint64_t free_cnt:10;
0674         uint64_t reserved_34_35:2;
0675         uint64_t buf_cnt:10;
0676         uint64_t reserved_46_47:2;
0677         uint64_t des_cnt:10;
0678         uint64_t reserved_58_63:6;
0679 #endif
0680     } cn52xx;
0681     struct cvmx_pow_qos_thrx_cn63xx {
0682 #ifdef __BIG_ENDIAN_BITFIELD
0683         uint64_t reserved_59_63:5;
0684         uint64_t des_cnt:11;
0685         uint64_t reserved_47_47:1;
0686         uint64_t buf_cnt:11;
0687         uint64_t reserved_35_35:1;
0688         uint64_t free_cnt:11;
0689         uint64_t reserved_22_23:2;
0690         uint64_t max_thr:10;
0691         uint64_t reserved_10_11:2;
0692         uint64_t min_thr:10;
0693 #else
0694         uint64_t min_thr:10;
0695         uint64_t reserved_10_11:2;
0696         uint64_t max_thr:10;
0697         uint64_t reserved_22_23:2;
0698         uint64_t free_cnt:11;
0699         uint64_t reserved_35_35:1;
0700         uint64_t buf_cnt:11;
0701         uint64_t reserved_47_47:1;
0702         uint64_t des_cnt:11;
0703         uint64_t reserved_59_63:5;
0704 #endif
0705     } cn63xx;
0706 };
0707 
0708 union cvmx_pow_ts_pc {
0709     uint64_t u64;
0710     struct cvmx_pow_ts_pc_s {
0711 #ifdef __BIG_ENDIAN_BITFIELD
0712         uint64_t reserved_32_63:32;
0713         uint64_t ts_pc:32;
0714 #else
0715         uint64_t ts_pc:32;
0716         uint64_t reserved_32_63:32;
0717 #endif
0718     } s;
0719 };
0720 
0721 union cvmx_pow_wa_com_pc {
0722     uint64_t u64;
0723     struct cvmx_pow_wa_com_pc_s {
0724 #ifdef __BIG_ENDIAN_BITFIELD
0725         uint64_t reserved_32_63:32;
0726         uint64_t wa_pc:32;
0727 #else
0728         uint64_t wa_pc:32;
0729         uint64_t reserved_32_63:32;
0730 #endif
0731     } s;
0732 };
0733 
0734 union cvmx_pow_wa_pcx {
0735     uint64_t u64;
0736     struct cvmx_pow_wa_pcx_s {
0737 #ifdef __BIG_ENDIAN_BITFIELD
0738         uint64_t reserved_32_63:32;
0739         uint64_t wa_pc:32;
0740 #else
0741         uint64_t wa_pc:32;
0742         uint64_t reserved_32_63:32;
0743 #endif
0744     } s;
0745 };
0746 
0747 union cvmx_pow_wq_int {
0748     uint64_t u64;
0749     struct cvmx_pow_wq_int_s {
0750 #ifdef __BIG_ENDIAN_BITFIELD
0751         uint64_t reserved_32_63:32;
0752         uint64_t iq_dis:16;
0753         uint64_t wq_int:16;
0754 #else
0755         uint64_t wq_int:16;
0756         uint64_t iq_dis:16;
0757         uint64_t reserved_32_63:32;
0758 #endif
0759     } s;
0760 };
0761 
0762 union cvmx_pow_wq_int_cntx {
0763     uint64_t u64;
0764     struct cvmx_pow_wq_int_cntx_s {
0765 #ifdef __BIG_ENDIAN_BITFIELD
0766         uint64_t reserved_28_63:36;
0767         uint64_t tc_cnt:4;
0768         uint64_t ds_cnt:12;
0769         uint64_t iq_cnt:12;
0770 #else
0771         uint64_t iq_cnt:12;
0772         uint64_t ds_cnt:12;
0773         uint64_t tc_cnt:4;
0774         uint64_t reserved_28_63:36;
0775 #endif
0776     } s;
0777     struct cvmx_pow_wq_int_cntx_cn30xx {
0778 #ifdef __BIG_ENDIAN_BITFIELD
0779         uint64_t reserved_28_63:36;
0780         uint64_t tc_cnt:4;
0781         uint64_t reserved_19_23:5;
0782         uint64_t ds_cnt:7;
0783         uint64_t reserved_7_11:5;
0784         uint64_t iq_cnt:7;
0785 #else
0786         uint64_t iq_cnt:7;
0787         uint64_t reserved_7_11:5;
0788         uint64_t ds_cnt:7;
0789         uint64_t reserved_19_23:5;
0790         uint64_t tc_cnt:4;
0791         uint64_t reserved_28_63:36;
0792 #endif
0793     } cn30xx;
0794     struct cvmx_pow_wq_int_cntx_cn31xx {
0795 #ifdef __BIG_ENDIAN_BITFIELD
0796         uint64_t reserved_28_63:36;
0797         uint64_t tc_cnt:4;
0798         uint64_t reserved_21_23:3;
0799         uint64_t ds_cnt:9;
0800         uint64_t reserved_9_11:3;
0801         uint64_t iq_cnt:9;
0802 #else
0803         uint64_t iq_cnt:9;
0804         uint64_t reserved_9_11:3;
0805         uint64_t ds_cnt:9;
0806         uint64_t reserved_21_23:3;
0807         uint64_t tc_cnt:4;
0808         uint64_t reserved_28_63:36;
0809 #endif
0810     } cn31xx;
0811     struct cvmx_pow_wq_int_cntx_cn52xx {
0812 #ifdef __BIG_ENDIAN_BITFIELD
0813         uint64_t reserved_28_63:36;
0814         uint64_t tc_cnt:4;
0815         uint64_t reserved_22_23:2;
0816         uint64_t ds_cnt:10;
0817         uint64_t reserved_10_11:2;
0818         uint64_t iq_cnt:10;
0819 #else
0820         uint64_t iq_cnt:10;
0821         uint64_t reserved_10_11:2;
0822         uint64_t ds_cnt:10;
0823         uint64_t reserved_22_23:2;
0824         uint64_t tc_cnt:4;
0825         uint64_t reserved_28_63:36;
0826 #endif
0827     } cn52xx;
0828     struct cvmx_pow_wq_int_cntx_cn63xx {
0829 #ifdef __BIG_ENDIAN_BITFIELD
0830         uint64_t reserved_28_63:36;
0831         uint64_t tc_cnt:4;
0832         uint64_t reserved_23_23:1;
0833         uint64_t ds_cnt:11;
0834         uint64_t reserved_11_11:1;
0835         uint64_t iq_cnt:11;
0836 #else
0837         uint64_t iq_cnt:11;
0838         uint64_t reserved_11_11:1;
0839         uint64_t ds_cnt:11;
0840         uint64_t reserved_23_23:1;
0841         uint64_t tc_cnt:4;
0842         uint64_t reserved_28_63:36;
0843 #endif
0844     } cn63xx;
0845 };
0846 
0847 union cvmx_pow_wq_int_pc {
0848     uint64_t u64;
0849     struct cvmx_pow_wq_int_pc_s {
0850 #ifdef __BIG_ENDIAN_BITFIELD
0851         uint64_t reserved_60_63:4;
0852         uint64_t pc:28;
0853         uint64_t reserved_28_31:4;
0854         uint64_t pc_thr:20;
0855         uint64_t reserved_0_7:8;
0856 #else
0857         uint64_t reserved_0_7:8;
0858         uint64_t pc_thr:20;
0859         uint64_t reserved_28_31:4;
0860         uint64_t pc:28;
0861         uint64_t reserved_60_63:4;
0862 #endif
0863     } s;
0864 };
0865 
0866 union cvmx_pow_wq_int_thrx {
0867     uint64_t u64;
0868     struct cvmx_pow_wq_int_thrx_s {
0869 #ifdef __BIG_ENDIAN_BITFIELD
0870         uint64_t reserved_29_63:35;
0871         uint64_t tc_en:1;
0872         uint64_t tc_thr:4;
0873         uint64_t reserved_23_23:1;
0874         uint64_t ds_thr:11;
0875         uint64_t reserved_11_11:1;
0876         uint64_t iq_thr:11;
0877 #else
0878         uint64_t iq_thr:11;
0879         uint64_t reserved_11_11:1;
0880         uint64_t ds_thr:11;
0881         uint64_t reserved_23_23:1;
0882         uint64_t tc_thr:4;
0883         uint64_t tc_en:1;
0884         uint64_t reserved_29_63:35;
0885 #endif
0886     } s;
0887     struct cvmx_pow_wq_int_thrx_cn30xx {
0888 #ifdef __BIG_ENDIAN_BITFIELD
0889         uint64_t reserved_29_63:35;
0890         uint64_t tc_en:1;
0891         uint64_t tc_thr:4;
0892         uint64_t reserved_18_23:6;
0893         uint64_t ds_thr:6;
0894         uint64_t reserved_6_11:6;
0895         uint64_t iq_thr:6;
0896 #else
0897         uint64_t iq_thr:6;
0898         uint64_t reserved_6_11:6;
0899         uint64_t ds_thr:6;
0900         uint64_t reserved_18_23:6;
0901         uint64_t tc_thr:4;
0902         uint64_t tc_en:1;
0903         uint64_t reserved_29_63:35;
0904 #endif
0905     } cn30xx;
0906     struct cvmx_pow_wq_int_thrx_cn31xx {
0907 #ifdef __BIG_ENDIAN_BITFIELD
0908         uint64_t reserved_29_63:35;
0909         uint64_t tc_en:1;
0910         uint64_t tc_thr:4;
0911         uint64_t reserved_20_23:4;
0912         uint64_t ds_thr:8;
0913         uint64_t reserved_8_11:4;
0914         uint64_t iq_thr:8;
0915 #else
0916         uint64_t iq_thr:8;
0917         uint64_t reserved_8_11:4;
0918         uint64_t ds_thr:8;
0919         uint64_t reserved_20_23:4;
0920         uint64_t tc_thr:4;
0921         uint64_t tc_en:1;
0922         uint64_t reserved_29_63:35;
0923 #endif
0924     } cn31xx;
0925     struct cvmx_pow_wq_int_thrx_cn52xx {
0926 #ifdef __BIG_ENDIAN_BITFIELD
0927         uint64_t reserved_29_63:35;
0928         uint64_t tc_en:1;
0929         uint64_t tc_thr:4;
0930         uint64_t reserved_21_23:3;
0931         uint64_t ds_thr:9;
0932         uint64_t reserved_9_11:3;
0933         uint64_t iq_thr:9;
0934 #else
0935         uint64_t iq_thr:9;
0936         uint64_t reserved_9_11:3;
0937         uint64_t ds_thr:9;
0938         uint64_t reserved_21_23:3;
0939         uint64_t tc_thr:4;
0940         uint64_t tc_en:1;
0941         uint64_t reserved_29_63:35;
0942 #endif
0943     } cn52xx;
0944     struct cvmx_pow_wq_int_thrx_cn63xx {
0945 #ifdef __BIG_ENDIAN_BITFIELD
0946         uint64_t reserved_29_63:35;
0947         uint64_t tc_en:1;
0948         uint64_t tc_thr:4;
0949         uint64_t reserved_22_23:2;
0950         uint64_t ds_thr:10;
0951         uint64_t reserved_10_11:2;
0952         uint64_t iq_thr:10;
0953 #else
0954         uint64_t iq_thr:10;
0955         uint64_t reserved_10_11:2;
0956         uint64_t ds_thr:10;
0957         uint64_t reserved_22_23:2;
0958         uint64_t tc_thr:4;
0959         uint64_t tc_en:1;
0960         uint64_t reserved_29_63:35;
0961 #endif
0962     } cn63xx;
0963 };
0964 
0965 union cvmx_pow_ws_pcx {
0966     uint64_t u64;
0967     struct cvmx_pow_ws_pcx_s {
0968 #ifdef __BIG_ENDIAN_BITFIELD
0969         uint64_t reserved_32_63:32;
0970         uint64_t ws_pc:32;
0971 #else
0972         uint64_t ws_pc:32;
0973         uint64_t reserved_32_63:32;
0974 #endif
0975     } s;
0976 };
0977 
0978 union cvmx_sso_wq_int_thrx {
0979     uint64_t u64;
0980     struct {
0981 #ifdef __BIG_ENDIAN_BITFIELD
0982         uint64_t reserved_33_63:31;
0983         uint64_t tc_en:1;
0984         uint64_t tc_thr:4;
0985         uint64_t reserved_26_27:2;
0986         uint64_t ds_thr:12;
0987         uint64_t reserved_12_13:2;
0988         uint64_t iq_thr:12;
0989 #else
0990         uint64_t iq_thr:12;
0991         uint64_t reserved_12_13:2;
0992         uint64_t ds_thr:12;
0993         uint64_t reserved_26_27:2;
0994         uint64_t tc_thr:4;
0995         uint64_t tc_en:1;
0996         uint64_t reserved_33_63:31;
0997 #endif
0998     } s;
0999 };
1000 
1001 #endif
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