asm/octeon/cvmx-pko-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_PKO_DEFS_H__
0029 #define __CVMX_PKO_DEFS_H__
0030
0031 #define CVMX_PKO_MEM_COUNT0 (CVMX_ADD_IO_SEG(0x0001180050001080ull))
0032 #define CVMX_PKO_MEM_COUNT1 (CVMX_ADD_IO_SEG(0x0001180050001088ull))
0033 #define CVMX_PKO_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050001100ull))
0034 #define CVMX_PKO_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180050001108ull))
0035 #define CVMX_PKO_MEM_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180050001150ull))
0036 #define CVMX_PKO_MEM_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180050001158ull))
0037 #define CVMX_PKO_MEM_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180050001160ull))
0038 #define CVMX_PKO_MEM_DEBUG13 (CVMX_ADD_IO_SEG(0x0001180050001168ull))
0039 #define CVMX_PKO_MEM_DEBUG14 (CVMX_ADD_IO_SEG(0x0001180050001170ull))
0040 #define CVMX_PKO_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180050001110ull))
0041 #define CVMX_PKO_MEM_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180050001118ull))
0042 #define CVMX_PKO_MEM_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180050001120ull))
0043 #define CVMX_PKO_MEM_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180050001128ull))
0044 #define CVMX_PKO_MEM_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180050001130ull))
0045 #define CVMX_PKO_MEM_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180050001138ull))
0046 #define CVMX_PKO_MEM_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180050001140ull))
0047 #define CVMX_PKO_MEM_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180050001148ull))
0048 #define CVMX_PKO_MEM_IPORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001030ull))
0049 #define CVMX_PKO_MEM_IPORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001038ull))
0050 #define CVMX_PKO_MEM_IQUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001040ull))
0051 #define CVMX_PKO_MEM_IQUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001048ull))
0052 #define CVMX_PKO_MEM_PORT_PTRS (CVMX_ADD_IO_SEG(0x0001180050001010ull))
0053 #define CVMX_PKO_MEM_PORT_QOS (CVMX_ADD_IO_SEG(0x0001180050001018ull))
0054 #define CVMX_PKO_MEM_PORT_RATE0 (CVMX_ADD_IO_SEG(0x0001180050001020ull))
0055 #define CVMX_PKO_MEM_PORT_RATE1 (CVMX_ADD_IO_SEG(0x0001180050001028ull))
0056 #define CVMX_PKO_MEM_QUEUE_PTRS (CVMX_ADD_IO_SEG(0x0001180050001000ull))
0057 #define CVMX_PKO_MEM_QUEUE_QOS (CVMX_ADD_IO_SEG(0x0001180050001008ull))
0058 #define CVMX_PKO_MEM_THROTTLE_INT (CVMX_ADD_IO_SEG(0x0001180050001058ull))
0059 #define CVMX_PKO_MEM_THROTTLE_PIPE (CVMX_ADD_IO_SEG(0x0001180050001050ull))
0060 #define CVMX_PKO_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180050000080ull))
0061 #define CVMX_PKO_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180050000010ull))
0062 #define CVMX_PKO_REG_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180050000028ull) + ((offset) & 1) * 8)
0063 #define CVMX_PKO_REG_CRC_ENABLE (CVMX_ADD_IO_SEG(0x0001180050000020ull))
0064 #define CVMX_PKO_REG_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x0001180050000038ull) + ((offset) & 1) * 8)
0065 #define CVMX_PKO_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180050000098ull))
0066 #define CVMX_PKO_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x00011800500000A0ull))
0067 #define CVMX_PKO_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x00011800500000A8ull))
0068 #define CVMX_PKO_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x00011800500000B0ull))
0069 #define CVMX_PKO_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x00011800500000B8ull))
0070 #define CVMX_PKO_REG_ENGINE_INFLIGHT (CVMX_ADD_IO_SEG(0x0001180050000050ull))
0071 #define CVMX_PKO_REG_ENGINE_INFLIGHT1 (CVMX_ADD_IO_SEG(0x0001180050000318ull))
0072 #define CVMX_PKO_REG_ENGINE_STORAGEX(offset) (CVMX_ADD_IO_SEG(0x0001180050000300ull) + ((offset) & 1) * 8)
0073 #define CVMX_PKO_REG_ENGINE_THRESH (CVMX_ADD_IO_SEG(0x0001180050000058ull))
0074 #define CVMX_PKO_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180050000088ull))
0075 #define CVMX_PKO_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180050000000ull))
0076 #define CVMX_PKO_REG_GMX_PORT_MODE (CVMX_ADD_IO_SEG(0x0001180050000018ull))
0077 #define CVMX_PKO_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180050000090ull))
0078 #define CVMX_PKO_REG_LOOPBACK_BPID (CVMX_ADD_IO_SEG(0x0001180050000118ull))
0079 #define CVMX_PKO_REG_LOOPBACK_PKIND (CVMX_ADD_IO_SEG(0x0001180050000068ull))
0080 #define CVMX_PKO_REG_MIN_PKT (CVMX_ADD_IO_SEG(0x0001180050000070ull))
0081 #define CVMX_PKO_REG_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000110ull))
0082 #define CVMX_PKO_REG_QUEUE_MODE (CVMX_ADD_IO_SEG(0x0001180050000048ull))
0083 #define CVMX_PKO_REG_QUEUE_PREEMPT (CVMX_ADD_IO_SEG(0x0001180050000108ull))
0084 #define CVMX_PKO_REG_QUEUE_PTRS1 (CVMX_ADD_IO_SEG(0x0001180050000100ull))
0085 #define CVMX_PKO_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180050000008ull))
0086 #define CVMX_PKO_REG_THROTTLE (CVMX_ADD_IO_SEG(0x0001180050000078ull))
0087 #define CVMX_PKO_REG_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001180050000060ull))
0088
0089 union cvmx_pko_mem_count0 {
0090     uint64_t u64;
0091     struct cvmx_pko_mem_count0_s {
0092 #ifdef __BIG_ENDIAN_BITFIELD
0093         uint64_t reserved_32_63:32;
0094         uint64_t count:32;
0095 #else
0096         uint64_t count:32;
0097         uint64_t reserved_32_63:32;
0098 #endif
0099     } s;
0100 };
0101
0102 union cvmx_pko_mem_count1 {
0103     uint64_t u64;
0104     struct cvmx_pko_mem_count1_s {
0105 #ifdef __BIG_ENDIAN_BITFIELD
0106         uint64_t reserved_48_63:16;
0107         uint64_t count:48;
0108 #else
0109         uint64_t count:48;
0110         uint64_t reserved_48_63:16;
0111 #endif
0112     } s;
0113 };
0114
0115 union cvmx_pko_mem_debug0 {
0116     uint64_t u64;
0117     struct cvmx_pko_mem_debug0_s {
0118 #ifdef __BIG_ENDIAN_BITFIELD
0119         uint64_t fau:28;
0120         uint64_t cmd:14;
0121         uint64_t segs:6;
0122         uint64_t size:16;
0123 #else
0124         uint64_t size:16;
0125         uint64_t segs:6;
0126         uint64_t cmd:14;
0127         uint64_t fau:28;
0128 #endif
0129     } s;
0130 };
0131
0132 union cvmx_pko_mem_debug1 {
0133     uint64_t u64;
0134     struct cvmx_pko_mem_debug1_s {
0135 #ifdef __BIG_ENDIAN_BITFIELD
0136         uint64_t i:1;
0137         uint64_t back:4;
0138         uint64_t pool:3;
0139         uint64_t size:16;
0140         uint64_t ptr:40;
0141 #else
0142         uint64_t ptr:40;
0143         uint64_t size:16;
0144         uint64_t pool:3;
0145         uint64_t back:4;
0146         uint64_t i:1;
0147 #endif
0148     } s;
0149 };
0150
0151 union cvmx_pko_mem_debug10 {
0152     uint64_t u64;
0153     struct cvmx_pko_mem_debug10_s {
0154 #ifdef __BIG_ENDIAN_BITFIELD
0155         uint64_t reserved_0_63:64;
0156 #else
0157         uint64_t reserved_0_63:64;
0158 #endif
0159     } s;
0160     struct cvmx_pko_mem_debug10_cn30xx {
0161 #ifdef __BIG_ENDIAN_BITFIELD
0162         uint64_t fau:28;
0163         uint64_t cmd:14;
0164         uint64_t segs:6;
0165         uint64_t size:16;
0166 #else
0167         uint64_t size:16;
0168         uint64_t segs:6;
0169         uint64_t cmd:14;
0170         uint64_t fau:28;
0171 #endif
0172     } cn30xx;
0173     struct cvmx_pko_mem_debug10_cn50xx {
0174 #ifdef __BIG_ENDIAN_BITFIELD
0175         uint64_t reserved_49_63:15;
0176         uint64_t ptrs1:17;
0177         uint64_t reserved_17_31:15;
0178         uint64_t ptrs2:17;
0179 #else
0180         uint64_t ptrs2:17;
0181         uint64_t reserved_17_31:15;
0182         uint64_t ptrs1:17;
0183         uint64_t reserved_49_63:15;
0184 #endif
0185     } cn50xx;
0186 };
0187
0188 union cvmx_pko_mem_debug11 {
0189     uint64_t u64;
0190     struct cvmx_pko_mem_debug11_s {
0191 #ifdef __BIG_ENDIAN_BITFIELD
0192         uint64_t i:1;
0193         uint64_t back:4;
0194         uint64_t pool:3;
0195         uint64_t size:16;
0196         uint64_t reserved_0_39:40;
0197 #else
0198         uint64_t reserved_0_39:40;
0199         uint64_t size:16;
0200         uint64_t pool:3;
0201         uint64_t back:4;
0202         uint64_t i:1;
0203 #endif
0204     } s;
0205     struct cvmx_pko_mem_debug11_cn30xx {
0206 #ifdef __BIG_ENDIAN_BITFIELD
0207         uint64_t i:1;
0208         uint64_t back:4;
0209         uint64_t pool:3;
0210         uint64_t size:16;
0211         uint64_t ptr:40;
0212 #else
0213         uint64_t ptr:40;
0214         uint64_t size:16;
0215         uint64_t pool:3;
0216         uint64_t back:4;
0217         uint64_t i:1;
0218 #endif
0219     } cn30xx;
0220     struct cvmx_pko_mem_debug11_cn50xx {
0221 #ifdef __BIG_ENDIAN_BITFIELD
0222         uint64_t reserved_23_63:41;
0223         uint64_t maj:1;
0224         uint64_t uid:3;
0225         uint64_t sop:1;
0226         uint64_t len:1;
0227         uint64_t chk:1;
0228         uint64_t cnt:13;
0229         uint64_t mod:3;
0230 #else
0231         uint64_t mod:3;
0232         uint64_t cnt:13;
0233         uint64_t chk:1;
0234         uint64_t len:1;
0235         uint64_t sop:1;
0236         uint64_t uid:3;
0237         uint64_t maj:1;
0238         uint64_t reserved_23_63:41;
0239 #endif
0240     } cn50xx;
0241 };
0242
0243 union cvmx_pko_mem_debug12 {
0244     uint64_t u64;
0245     struct cvmx_pko_mem_debug12_s {
0246 #ifdef __BIG_ENDIAN_BITFIELD
0247         uint64_t reserved_0_63:64;
0248 #else
0249         uint64_t reserved_0_63:64;
0250 #endif
0251     } s;
0252     struct cvmx_pko_mem_debug12_cn30xx {
0253 #ifdef __BIG_ENDIAN_BITFIELD
0254         uint64_t data:64;
0255 #else
0256         uint64_t data:64;
0257 #endif
0258     } cn30xx;
0259     struct cvmx_pko_mem_debug12_cn50xx {
0260 #ifdef __BIG_ENDIAN_BITFIELD
0261         uint64_t fau:28;
0262         uint64_t cmd:14;
0263         uint64_t segs:6;
0264         uint64_t size:16;
0265 #else
0266         uint64_t size:16;
0267         uint64_t segs:6;
0268         uint64_t cmd:14;
0269         uint64_t fau:28;
0270 #endif
0271     } cn50xx;
0272     struct cvmx_pko_mem_debug12_cn68xx {
0273 #ifdef __BIG_ENDIAN_BITFIELD
0274         uint64_t state:64;
0275 #else
0276         uint64_t state:64;
0277 #endif
0278     } cn68xx;
0279 };
0280
0281 union cvmx_pko_mem_debug13 {
0282     uint64_t u64;
0283     struct cvmx_pko_mem_debug13_s {
0284 #ifdef __BIG_ENDIAN_BITFIELD
0285         uint64_t reserved_0_63:64;
0286 #else
0287         uint64_t reserved_0_63:64;
0288 #endif
0289     } s;
0290     struct cvmx_pko_mem_debug13_cn30xx {
0291 #ifdef __BIG_ENDIAN_BITFIELD
0292         uint64_t reserved_51_63:13;
0293         uint64_t widx:17;
0294         uint64_t ridx2:17;
0295         uint64_t widx2:17;
0296 #else
0297         uint64_t widx2:17;
0298         uint64_t ridx2:17;
0299         uint64_t widx:17;
0300         uint64_t reserved_51_63:13;
0301 #endif
0302     } cn30xx;
0303     struct cvmx_pko_mem_debug13_cn50xx {
0304 #ifdef __BIG_ENDIAN_BITFIELD
0305         uint64_t i:1;
0306         uint64_t back:4;
0307         uint64_t pool:3;
0308         uint64_t size:16;
0309         uint64_t ptr:40;
0310 #else
0311         uint64_t ptr:40;
0312         uint64_t size:16;
0313         uint64_t pool:3;
0314         uint64_t back:4;
0315         uint64_t i:1;
0316 #endif
0317     } cn50xx;
0318     struct cvmx_pko_mem_debug13_cn68xx {
0319 #ifdef __BIG_ENDIAN_BITFIELD
0320         uint64_t state:64;
0321 #else
0322         uint64_t state:64;
0323 #endif
0324     } cn68xx;
0325 };
0326
0327 union cvmx_pko_mem_debug14 {
0328     uint64_t u64;
0329     struct cvmx_pko_mem_debug14_s {
0330 #ifdef __BIG_ENDIAN_BITFIELD
0331         uint64_t reserved_0_63:64;
0332 #else
0333         uint64_t reserved_0_63:64;
0334 #endif
0335     } s;
0336     struct cvmx_pko_mem_debug14_cn30xx {
0337 #ifdef __BIG_ENDIAN_BITFIELD
0338         uint64_t reserved_17_63:47;
0339         uint64_t ridx:17;
0340 #else
0341         uint64_t ridx:17;
0342         uint64_t reserved_17_63:47;
0343 #endif
0344     } cn30xx;
0345     struct cvmx_pko_mem_debug14_cn52xx {
0346 #ifdef __BIG_ENDIAN_BITFIELD
0347         uint64_t data:64;
0348 #else
0349         uint64_t data:64;
0350 #endif
0351     } cn52xx;
0352 };
0353
0354 union cvmx_pko_mem_debug2 {
0355     uint64_t u64;
0356     struct cvmx_pko_mem_debug2_s {
0357 #ifdef __BIG_ENDIAN_BITFIELD
0358         uint64_t i:1;
0359         uint64_t back:4;
0360         uint64_t pool:3;
0361         uint64_t size:16;
0362         uint64_t ptr:40;
0363 #else
0364         uint64_t ptr:40;
0365         uint64_t size:16;
0366         uint64_t pool:3;
0367         uint64_t back:4;
0368         uint64_t i:1;
0369 #endif
0370     } s;
0371 };
0372
0373 union cvmx_pko_mem_debug3 {
0374     uint64_t u64;
0375     struct cvmx_pko_mem_debug3_s {
0376 #ifdef __BIG_ENDIAN_BITFIELD
0377         uint64_t reserved_0_63:64;
0378 #else
0379         uint64_t reserved_0_63:64;
0380 #endif
0381     } s;
0382     struct cvmx_pko_mem_debug3_cn30xx {
0383 #ifdef __BIG_ENDIAN_BITFIELD
0384         uint64_t i:1;
0385         uint64_t back:4;
0386         uint64_t pool:3;
0387         uint64_t size:16;
0388         uint64_t ptr:40;
0389 #else
0390         uint64_t ptr:40;
0391         uint64_t size:16;
0392         uint64_t pool:3;
0393         uint64_t back:4;
0394         uint64_t i:1;
0395 #endif
0396     } cn30xx;
0397     struct cvmx_pko_mem_debug3_cn50xx {
0398 #ifdef __BIG_ENDIAN_BITFIELD
0399         uint64_t data:64;
0400 #else
0401         uint64_t data:64;
0402 #endif
0403     } cn50xx;
0404 };
0405
0406 union cvmx_pko_mem_debug4 {
0407     uint64_t u64;
0408     struct cvmx_pko_mem_debug4_s {
0409 #ifdef __BIG_ENDIAN_BITFIELD
0410         uint64_t reserved_0_63:64;
0411 #else
0412         uint64_t reserved_0_63:64;
0413 #endif
0414     } s;
0415     struct cvmx_pko_mem_debug4_cn30xx {
0416 #ifdef __BIG_ENDIAN_BITFIELD
0417         uint64_t data:64;
0418 #else
0419         uint64_t data:64;
0420 #endif
0421     } cn30xx;
0422     struct cvmx_pko_mem_debug4_cn50xx {
0423 #ifdef __BIG_ENDIAN_BITFIELD
0424         uint64_t cmnd_segs:3;
0425         uint64_t cmnd_siz:16;
0426         uint64_t cmnd_off:6;
0427         uint64_t uid:3;
0428         uint64_t dread_sop:1;
0429         uint64_t init_dwrite:1;
0430         uint64_t chk_once:1;
0431         uint64_t chk_mode:1;
0432         uint64_t active:1;
0433         uint64_t static_p:1;
0434         uint64_t qos:3;
0435         uint64_t qcb_ridx:5;
0436         uint64_t qid_off_max:4;
0437         uint64_t qid_off:4;
0438         uint64_t qid_base:8;
0439         uint64_t wait:1;
0440         uint64_t minor:2;
0441         uint64_t major:3;
0442 #else
0443         uint64_t major:3;
0444         uint64_t minor:2;
0445         uint64_t wait:1;
0446         uint64_t qid_base:8;
0447         uint64_t qid_off:4;
0448         uint64_t qid_off_max:4;
0449         uint64_t qcb_ridx:5;
0450         uint64_t qos:3;
0451         uint64_t static_p:1;
0452         uint64_t active:1;
0453         uint64_t chk_mode:1;
0454         uint64_t chk_once:1;
0455         uint64_t init_dwrite:1;
0456         uint64_t dread_sop:1;
0457         uint64_t uid:3;
0458         uint64_t cmnd_off:6;
0459         uint64_t cmnd_siz:16;
0460         uint64_t cmnd_segs:3;
0461 #endif
0462     } cn50xx;
0463     struct cvmx_pko_mem_debug4_cn52xx {
0464 #ifdef __BIG_ENDIAN_BITFIELD
0465         uint64_t curr_siz:8;
0466         uint64_t curr_off:16;
0467         uint64_t cmnd_segs:6;
0468         uint64_t cmnd_siz:16;
0469         uint64_t cmnd_off:6;
0470         uint64_t uid:2;
0471         uint64_t dread_sop:1;
0472         uint64_t init_dwrite:1;
0473         uint64_t chk_once:1;
0474         uint64_t chk_mode:1;
0475         uint64_t wait:1;
0476         uint64_t minor:2;
0477         uint64_t major:3;
0478 #else
0479         uint64_t major:3;
0480         uint64_t minor:2;
0481         uint64_t wait:1;
0482         uint64_t chk_mode:1;
0483         uint64_t chk_once:1;
0484         uint64_t init_dwrite:1;
0485         uint64_t dread_sop:1;
0486         uint64_t uid:2;
0487         uint64_t cmnd_off:6;
0488         uint64_t cmnd_siz:16;
0489         uint64_t cmnd_segs:6;
0490         uint64_t curr_off:16;
0491         uint64_t curr_siz:8;
0492 #endif
0493     } cn52xx;
0494 };
0495
0496 union cvmx_pko_mem_debug5 {
0497     uint64_t u64;
0498     struct cvmx_pko_mem_debug5_s {
0499 #ifdef __BIG_ENDIAN_BITFIELD
0500         uint64_t reserved_0_63:64;
0501 #else
0502         uint64_t reserved_0_63:64;
0503 #endif
0504     } s;
0505     struct cvmx_pko_mem_debug5_cn30xx {
0506 #ifdef __BIG_ENDIAN_BITFIELD
0507         uint64_t dwri_mod:1;
0508         uint64_t dwri_sop:1;
0509         uint64_t dwri_len:1;
0510         uint64_t dwri_cnt:13;
0511         uint64_t cmnd_siz:16;
0512         uint64_t uid:1;
0513         uint64_t xfer_wor:1;
0514         uint64_t xfer_dwr:1;
0515         uint64_t cbuf_fre:1;
0516         uint64_t reserved_27_27:1;
0517         uint64_t chk_mode:1;
0518         uint64_t active:1;
0519         uint64_t qos:3;
0520         uint64_t qcb_ridx:5;
0521         uint64_t qid_off:3;
0522         uint64_t qid_base:7;
0523         uint64_t wait:1;
0524         uint64_t minor:2;
0525         uint64_t major:4;
0526 #else
0527         uint64_t major:4;
0528         uint64_t minor:2;
0529         uint64_t wait:1;
0530         uint64_t qid_base:7;
0531         uint64_t qid_off:3;
0532         uint64_t qcb_ridx:5;
0533         uint64_t qos:3;
0534         uint64_t active:1;
0535         uint64_t chk_mode:1;
0536         uint64_t reserved_27_27:1;
0537         uint64_t cbuf_fre:1;
0538         uint64_t xfer_dwr:1;
0539         uint64_t xfer_wor:1;
0540         uint64_t uid:1;
0541         uint64_t cmnd_siz:16;
0542         uint64_t dwri_cnt:13;
0543         uint64_t dwri_len:1;
0544         uint64_t dwri_sop:1;
0545         uint64_t dwri_mod:1;
0546 #endif
0547     } cn30xx;
0548     struct cvmx_pko_mem_debug5_cn50xx {
0549 #ifdef __BIG_ENDIAN_BITFIELD
0550         uint64_t curr_ptr:29;
0551         uint64_t curr_siz:16;
0552         uint64_t curr_off:16;
0553         uint64_t cmnd_segs:3;
0554 #else
0555         uint64_t cmnd_segs:3;
0556         uint64_t curr_off:16;
0557         uint64_t curr_siz:16;
0558         uint64_t curr_ptr:29;
0559 #endif
0560     } cn50xx;
0561     struct cvmx_pko_mem_debug5_cn52xx {
0562 #ifdef __BIG_ENDIAN_BITFIELD
0563         uint64_t reserved_54_63:10;
0564         uint64_t nxt_inflt:6;
0565         uint64_t curr_ptr:40;
0566         uint64_t curr_siz:8;
0567 #else
0568         uint64_t curr_siz:8;
0569         uint64_t curr_ptr:40;
0570         uint64_t nxt_inflt:6;
0571         uint64_t reserved_54_63:10;
0572 #endif
0573     } cn52xx;
0574     struct cvmx_pko_mem_debug5_cn61xx {
0575 #ifdef __BIG_ENDIAN_BITFIELD
0576         uint64_t reserved_56_63:8;
0577         uint64_t ptp:1;
0578         uint64_t major_3:1;
0579         uint64_t nxt_inflt:6;
0580         uint64_t curr_ptr:40;
0581         uint64_t curr_siz:8;
0582 #else
0583         uint64_t curr_siz:8;
0584         uint64_t curr_ptr:40;
0585         uint64_t nxt_inflt:6;
0586         uint64_t major_3:1;
0587         uint64_t ptp:1;
0588         uint64_t reserved_56_63:8;
0589 #endif
0590     } cn61xx;
0591     struct cvmx_pko_mem_debug5_cn68xx {
0592 #ifdef __BIG_ENDIAN_BITFIELD
0593         uint64_t reserved_57_63:7;
0594         uint64_t uid_2:1;
0595         uint64_t ptp:1;
0596         uint64_t major_3:1;
0597         uint64_t nxt_inflt:6;
0598         uint64_t curr_ptr:40;
0599         uint64_t curr_siz:8;
0600 #else
0601         uint64_t curr_siz:8;
0602         uint64_t curr_ptr:40;
0603         uint64_t nxt_inflt:6;
0604         uint64_t major_3:1;
0605         uint64_t ptp:1;
0606         uint64_t uid_2:1;
0607         uint64_t reserved_57_63:7;
0608 #endif
0609     } cn68xx;
0610 };
0611
0612 union cvmx_pko_mem_debug6 {
0613     uint64_t u64;
0614     struct cvmx_pko_mem_debug6_s {
0615 #ifdef __BIG_ENDIAN_BITFIELD
0616         uint64_t reserved_37_63:27;
0617         uint64_t qid_offres:4;
0618         uint64_t qid_offths:4;
0619         uint64_t preempter:1;
0620         uint64_t preemptee:1;
0621         uint64_t preempted:1;
0622         uint64_t active:1;
0623         uint64_t statc:1;
0624         uint64_t qos:3;
0625         uint64_t qcb_ridx:5;
0626         uint64_t qid_offmax:4;
0627         uint64_t reserved_0_11:12;
0628 #else
0629         uint64_t reserved_0_11:12;
0630         uint64_t qid_offmax:4;
0631         uint64_t qcb_ridx:5;
0632         uint64_t qos:3;
0633         uint64_t statc:1;
0634         uint64_t active:1;
0635         uint64_t preempted:1;
0636         uint64_t preemptee:1;
0637         uint64_t preempter:1;
0638         uint64_t qid_offths:4;
0639         uint64_t qid_offres:4;
0640         uint64_t reserved_37_63:27;
0641 #endif
0642     } s;
0643     struct cvmx_pko_mem_debug6_cn30xx {
0644 #ifdef __BIG_ENDIAN_BITFIELD
0645         uint64_t reserved_11_63:53;
0646         uint64_t qid_offm:3;
0647         uint64_t static_p:1;
0648         uint64_t work_min:3;
0649         uint64_t dwri_chk:1;
0650         uint64_t dwri_uid:1;
0651         uint64_t dwri_mod:2;
0652 #else
0653         uint64_t dwri_mod:2;
0654         uint64_t dwri_uid:1;
0655         uint64_t dwri_chk:1;
0656         uint64_t work_min:3;
0657         uint64_t static_p:1;
0658         uint64_t qid_offm:3;
0659         uint64_t reserved_11_63:53;
0660 #endif
0661     } cn30xx;
0662     struct cvmx_pko_mem_debug6_cn50xx {
0663 #ifdef __BIG_ENDIAN_BITFIELD
0664         uint64_t reserved_11_63:53;
0665         uint64_t curr_ptr:11;
0666 #else
0667         uint64_t curr_ptr:11;
0668         uint64_t reserved_11_63:53;
0669 #endif
0670     } cn50xx;
0671     struct cvmx_pko_mem_debug6_cn52xx {
0672 #ifdef __BIG_ENDIAN_BITFIELD
0673         uint64_t reserved_37_63:27;
0674         uint64_t qid_offres:4;
0675         uint64_t qid_offths:4;
0676         uint64_t preempter:1;
0677         uint64_t preemptee:1;
0678         uint64_t preempted:1;
0679         uint64_t active:1;
0680         uint64_t statc:1;
0681         uint64_t qos:3;
0682         uint64_t qcb_ridx:5;
0683         uint64_t qid_offmax:4;
0684         uint64_t qid_off:4;
0685         uint64_t qid_base:8;
0686 #else
0687         uint64_t qid_base:8;
0688         uint64_t qid_off:4;
0689         uint64_t qid_offmax:4;
0690         uint64_t qcb_ridx:5;
0691         uint64_t qos:3;
0692         uint64_t statc:1;
0693         uint64_t active:1;
0694         uint64_t preempted:1;
0695         uint64_t preemptee:1;
0696         uint64_t preempter:1;
0697         uint64_t qid_offths:4;
0698         uint64_t qid_offres:4;
0699         uint64_t reserved_37_63:27;
0700 #endif
0701     } cn52xx;
0702 };
0703
0704 union cvmx_pko_mem_debug7 {
0705     uint64_t u64;
0706     struct cvmx_pko_mem_debug7_s {
0707 #ifdef __BIG_ENDIAN_BITFIELD
0708         uint64_t reserved_0_63:64;
0709 #else
0710         uint64_t reserved_0_63:64;
0711 #endif
0712     } s;
0713     struct cvmx_pko_mem_debug7_cn30xx {
0714 #ifdef __BIG_ENDIAN_BITFIELD
0715         uint64_t reserved_58_63:6;
0716         uint64_t dwb:9;
0717         uint64_t start:33;
0718         uint64_t size:16;
0719 #else
0720         uint64_t size:16;
0721         uint64_t start:33;
0722         uint64_t dwb:9;
0723         uint64_t reserved_58_63:6;
0724 #endif
0725     } cn30xx;
0726     struct cvmx_pko_mem_debug7_cn50xx {
0727 #ifdef __BIG_ENDIAN_BITFIELD
0728         uint64_t qos:5;
0729         uint64_t tail:1;
0730         uint64_t buf_siz:13;
0731         uint64_t buf_ptr:33;
0732         uint64_t qcb_widx:6;
0733         uint64_t qcb_ridx:6;
0734 #else
0735         uint64_t qcb_ridx:6;
0736         uint64_t qcb_widx:6;
0737         uint64_t buf_ptr:33;
0738         uint64_t buf_siz:13;
0739         uint64_t tail:1;
0740         uint64_t qos:5;
0741 #endif
0742     } cn50xx;
0743     struct cvmx_pko_mem_debug7_cn68xx {
0744 #ifdef __BIG_ENDIAN_BITFIELD
0745         uint64_t qos:3;
0746         uint64_t tail:1;
0747         uint64_t buf_siz:13;
0748         uint64_t buf_ptr:33;
0749         uint64_t qcb_widx:7;
0750         uint64_t qcb_ridx:7;
0751 #else
0752         uint64_t qcb_ridx:7;
0753         uint64_t qcb_widx:7;
0754         uint64_t buf_ptr:33;
0755         uint64_t buf_siz:13;
0756         uint64_t tail:1;
0757         uint64_t qos:3;
0758 #endif
0759     } cn68xx;
0760 };
0761
0762 union cvmx_pko_mem_debug8 {
0763     uint64_t u64;
0764     struct cvmx_pko_mem_debug8_s {
0765 #ifdef __BIG_ENDIAN_BITFIELD
0766         uint64_t reserved_59_63:5;
0767         uint64_t tail:1;
0768         uint64_t buf_siz:13;
0769         uint64_t reserved_0_44:45;
0770 #else
0771         uint64_t reserved_0_44:45;
0772         uint64_t buf_siz:13;
0773         uint64_t tail:1;
0774         uint64_t reserved_59_63:5;
0775 #endif
0776     } s;
0777     struct cvmx_pko_mem_debug8_cn30xx {
0778 #ifdef __BIG_ENDIAN_BITFIELD
0779         uint64_t qos:5;
0780         uint64_t tail:1;
0781         uint64_t buf_siz:13;
0782         uint64_t buf_ptr:33;
0783         uint64_t qcb_widx:6;
0784         uint64_t qcb_ridx:6;
0785 #else
0786         uint64_t qcb_ridx:6;
0787         uint64_t qcb_widx:6;
0788         uint64_t buf_ptr:33;
0789         uint64_t buf_siz:13;
0790         uint64_t tail:1;
0791         uint64_t qos:5;
0792 #endif
0793     } cn30xx;
0794     struct cvmx_pko_mem_debug8_cn50xx {
0795 #ifdef __BIG_ENDIAN_BITFIELD
0796         uint64_t reserved_28_63:36;
0797         uint64_t doorbell:20;
0798         uint64_t reserved_6_7:2;
0799         uint64_t static_p:1;
0800         uint64_t s_tail:1;
0801         uint64_t static_q:1;
0802         uint64_t qos:3;
0803 #else
0804         uint64_t qos:3;
0805         uint64_t static_q:1;
0806         uint64_t s_tail:1;
0807         uint64_t static_p:1;
0808         uint64_t reserved_6_7:2;
0809         uint64_t doorbell:20;
0810         uint64_t reserved_28_63:36;
0811 #endif
0812     } cn50xx;
0813     struct cvmx_pko_mem_debug8_cn52xx {
0814 #ifdef __BIG_ENDIAN_BITFIELD
0815         uint64_t reserved_29_63:35;
0816         uint64_t preempter:1;
0817         uint64_t doorbell:20;
0818         uint64_t reserved_7_7:1;
0819         uint64_t preemptee:1;
0820         uint64_t static_p:1;
0821         uint64_t s_tail:1;
0822         uint64_t static_q:1;
0823         uint64_t qos:3;
0824 #else
0825         uint64_t qos:3;
0826         uint64_t static_q:1;
0827         uint64_t s_tail:1;
0828         uint64_t static_p:1;
0829         uint64_t preemptee:1;
0830         uint64_t reserved_7_7:1;
0831         uint64_t doorbell:20;
0832         uint64_t preempter:1;
0833         uint64_t reserved_29_63:35;
0834 #endif
0835     } cn52xx;
0836     struct cvmx_pko_mem_debug8_cn61xx {
0837 #ifdef __BIG_ENDIAN_BITFIELD
0838         uint64_t reserved_42_63:22;
0839         uint64_t qid_qqos:8;
0840         uint64_t reserved_33_33:1;
0841         uint64_t qid_idx:4;
0842         uint64_t preempter:1;
0843         uint64_t doorbell:20;
0844         uint64_t reserved_7_7:1;
0845         uint64_t preemptee:1;
0846         uint64_t static_p:1;
0847         uint64_t s_tail:1;
0848         uint64_t static_q:1;
0849         uint64_t qos:3;
0850 #else
0851         uint64_t qos:3;
0852         uint64_t static_q:1;
0853         uint64_t s_tail:1;
0854         uint64_t static_p:1;
0855         uint64_t preemptee:1;
0856         uint64_t reserved_7_7:1;
0857         uint64_t doorbell:20;
0858         uint64_t preempter:1;
0859         uint64_t qid_idx:4;
0860         uint64_t reserved_33_33:1;
0861         uint64_t qid_qqos:8;
0862         uint64_t reserved_42_63:22;
0863 #endif
0864     } cn61xx;
0865     struct cvmx_pko_mem_debug8_cn68xx {
0866 #ifdef __BIG_ENDIAN_BITFIELD
0867         uint64_t reserved_37_63:27;
0868         uint64_t preempter:1;
0869         uint64_t doorbell:20;
0870         uint64_t reserved_9_15:7;
0871         uint64_t preemptee:1;
0872         uint64_t static_p:1;
0873         uint64_t s_tail:1;
0874         uint64_t static_q:1;
0875         uint64_t qos:5;
0876 #else
0877         uint64_t qos:5;
0878         uint64_t static_q:1;
0879         uint64_t s_tail:1;
0880         uint64_t static_p:1;
0881         uint64_t preemptee:1;
0882         uint64_t reserved_9_15:7;
0883         uint64_t doorbell:20;
0884         uint64_t preempter:1;
0885         uint64_t reserved_37_63:27;
0886 #endif
0887     } cn68xx;
0888 };
0889
0890 union cvmx_pko_mem_debug9 {
0891     uint64_t u64;
0892     struct cvmx_pko_mem_debug9_s {
0893 #ifdef __BIG_ENDIAN_BITFIELD
0894         uint64_t reserved_49_63:15;
0895         uint64_t ptrs0:17;
0896         uint64_t reserved_0_31:32;
0897 #else
0898         uint64_t reserved_0_31:32;
0899         uint64_t ptrs0:17;
0900         uint64_t reserved_49_63:15;
0901 #endif
0902     } s;
0903     struct cvmx_pko_mem_debug9_cn30xx {
0904 #ifdef __BIG_ENDIAN_BITFIELD
0905         uint64_t reserved_28_63:36;
0906         uint64_t doorbell:20;
0907         uint64_t reserved_5_7:3;
0908         uint64_t s_tail:1;
0909         uint64_t static_q:1;
0910         uint64_t qos:3;
0911 #else
0912         uint64_t qos:3;
0913         uint64_t static_q:1;
0914         uint64_t s_tail:1;
0915         uint64_t reserved_5_7:3;
0916         uint64_t doorbell:20;
0917         uint64_t reserved_28_63:36;
0918 #endif
0919     } cn30xx;
0920     struct cvmx_pko_mem_debug9_cn38xx {
0921 #ifdef __BIG_ENDIAN_BITFIELD
0922         uint64_t reserved_28_63:36;
0923         uint64_t doorbell:20;
0924         uint64_t reserved_6_7:2;
0925         uint64_t static_p:1;
0926         uint64_t s_tail:1;
0927         uint64_t static_q:1;
0928         uint64_t qos:3;
0929 #else
0930         uint64_t qos:3;
0931         uint64_t static_q:1;
0932         uint64_t s_tail:1;
0933         uint64_t static_p:1;
0934         uint64_t reserved_6_7:2;
0935         uint64_t doorbell:20;
0936         uint64_t reserved_28_63:36;
0937 #endif
0938     } cn38xx;
0939     struct cvmx_pko_mem_debug9_cn50xx {
0940 #ifdef __BIG_ENDIAN_BITFIELD
0941         uint64_t reserved_49_63:15;
0942         uint64_t ptrs0:17;
0943         uint64_t reserved_17_31:15;
0944         uint64_t ptrs3:17;
0945 #else
0946         uint64_t ptrs3:17;
0947         uint64_t reserved_17_31:15;
0948         uint64_t ptrs0:17;
0949         uint64_t reserved_49_63:15;
0950 #endif
0951     } cn50xx;
0952 };
0953
0954 union cvmx_pko_mem_iport_ptrs {
0955     uint64_t u64;
0956     struct cvmx_pko_mem_iport_ptrs_s {
0957 #ifdef __BIG_ENDIAN_BITFIELD
0958         uint64_t reserved_63_63:1;
0959         uint64_t crc:1;
0960         uint64_t static_p:1;
0961         uint64_t qos_mask:8;
0962         uint64_t min_pkt:3;
0963         uint64_t reserved_31_49:19;
0964         uint64_t pipe:7;
0965         uint64_t reserved_21_23:3;
0966         uint64_t intr:5;
0967         uint64_t reserved_13_15:3;
0968         uint64_t eid:5;
0969         uint64_t reserved_7_7:1;
0970         uint64_t ipid:7;
0971 #else
0972         uint64_t ipid:7;
0973         uint64_t reserved_7_7:1;
0974         uint64_t eid:5;
0975         uint64_t reserved_13_15:3;
0976         uint64_t intr:5;
0977         uint64_t reserved_21_23:3;
0978         uint64_t pipe:7;
0979         uint64_t reserved_31_49:19;
0980         uint64_t min_pkt:3;
0981         uint64_t qos_mask:8;
0982         uint64_t static_p:1;
0983         uint64_t crc:1;
0984         uint64_t reserved_63_63:1;
0985 #endif
0986     } s;
0987 };
0988
0989 union cvmx_pko_mem_iport_qos {
0990     uint64_t u64;
0991     struct cvmx_pko_mem_iport_qos_s {
0992 #ifdef __BIG_ENDIAN_BITFIELD
0993         uint64_t reserved_61_63:3;
0994         uint64_t qos_mask:8;
0995         uint64_t reserved_13_52:40;
0996         uint64_t eid:5;
0997         uint64_t reserved_7_7:1;
0998         uint64_t ipid:7;
0999 #else
1000         uint64_t ipid:7;
1001         uint64_t reserved_7_7:1;
1002         uint64_t eid:5;
1003         uint64_t reserved_13_52:40;
1004         uint64_t qos_mask:8;
1005         uint64_t reserved_61_63:3;
1006 #endif
1007     } s;
1008 };
1009
1010 union cvmx_pko_mem_iqueue_ptrs {
1011     uint64_t u64;
1012     struct cvmx_pko_mem_iqueue_ptrs_s {
1013 #ifdef __BIG_ENDIAN_BITFIELD
1014         uint64_t s_tail:1;
1015         uint64_t static_p:1;
1016         uint64_t static_q:1;
1017         uint64_t qos_mask:8;
1018         uint64_t buf_ptr:31;
1019         uint64_t tail:1;
1020         uint64_t index:5;
1021         uint64_t reserved_15_15:1;
1022         uint64_t ipid:7;
1023         uint64_t qid:8;
1024 #else
1025         uint64_t qid:8;
1026         uint64_t ipid:7;
1027         uint64_t reserved_15_15:1;
1028         uint64_t index:5;
1029         uint64_t tail:1;
1030         uint64_t buf_ptr:31;
1031         uint64_t qos_mask:8;
1032         uint64_t static_q:1;
1033         uint64_t static_p:1;
1034         uint64_t s_tail:1;
1035 #endif
1036     } s;
1037 };
1038
1039 union cvmx_pko_mem_iqueue_qos {
1040     uint64_t u64;
1041     struct cvmx_pko_mem_iqueue_qos_s {
1042 #ifdef __BIG_ENDIAN_BITFIELD
1043         uint64_t reserved_61_63:3;
1044         uint64_t qos_mask:8;
1045         uint64_t reserved_15_52:38;
1046         uint64_t ipid:7;
1047         uint64_t qid:8;
1048 #else
1049         uint64_t qid:8;
1050         uint64_t ipid:7;
1051         uint64_t reserved_15_52:38;
1052         uint64_t qos_mask:8;
1053         uint64_t reserved_61_63:3;
1054 #endif
1055     } s;
1056 };
1057
1058 union cvmx_pko_mem_port_ptrs {
1059     uint64_t u64;
1060     struct cvmx_pko_mem_port_ptrs_s {
1061 #ifdef __BIG_ENDIAN_BITFIELD
1062         uint64_t reserved_62_63:2;
1063         uint64_t static_p:1;
1064         uint64_t qos_mask:8;
1065         uint64_t reserved_16_52:37;
1066         uint64_t bp_port:6;
1067         uint64_t eid:4;
1068         uint64_t pid:6;
1069 #else
1070         uint64_t pid:6;
1071         uint64_t eid:4;
1072         uint64_t bp_port:6;
1073         uint64_t reserved_16_52:37;
1074         uint64_t qos_mask:8;
1075         uint64_t static_p:1;
1076         uint64_t reserved_62_63:2;
1077 #endif
1078     } s;
1079 };
1080
1081 union cvmx_pko_mem_port_qos {
1082     uint64_t u64;
1083     struct cvmx_pko_mem_port_qos_s {
1084 #ifdef __BIG_ENDIAN_BITFIELD
1085         uint64_t reserved_61_63:3;
1086         uint64_t qos_mask:8;
1087         uint64_t reserved_10_52:43;
1088         uint64_t eid:4;
1089         uint64_t pid:6;
1090 #else
1091         uint64_t pid:6;
1092         uint64_t eid:4;
1093         uint64_t reserved_10_52:43;
1094         uint64_t qos_mask:8;
1095         uint64_t reserved_61_63:3;
1096 #endif
1097     } s;
1098 };
1099
1100 union cvmx_pko_mem_port_rate0 {
1101     uint64_t u64;
1102     struct cvmx_pko_mem_port_rate0_s {
1103 #ifdef __BIG_ENDIAN_BITFIELD
1104         uint64_t reserved_51_63:13;
1105         uint64_t rate_word:19;
1106         uint64_t rate_pkt:24;
1107         uint64_t reserved_7_7:1;
1108         uint64_t pid:7;
1109 #else
1110         uint64_t pid:7;
1111         uint64_t reserved_7_7:1;
1112         uint64_t rate_pkt:24;
1113         uint64_t rate_word:19;
1114         uint64_t reserved_51_63:13;
1115 #endif
1116     } s;
1117     struct cvmx_pko_mem_port_rate0_cn52xx {
1118 #ifdef __BIG_ENDIAN_BITFIELD
1119         uint64_t reserved_51_63:13;
1120         uint64_t rate_word:19;
1121         uint64_t rate_pkt:24;
1122         uint64_t reserved_6_7:2;
1123         uint64_t pid:6;
1124 #else
1125         uint64_t pid:6;
1126         uint64_t reserved_6_7:2;
1127         uint64_t rate_pkt:24;
1128         uint64_t rate_word:19;
1129         uint64_t reserved_51_63:13;
1130 #endif
1131     } cn52xx;
1132 };
1133
1134 union cvmx_pko_mem_port_rate1 {
1135     uint64_t u64;
1136     struct cvmx_pko_mem_port_rate1_s {
1137 #ifdef __BIG_ENDIAN_BITFIELD
1138         uint64_t reserved_32_63:32;
1139         uint64_t rate_lim:24;
1140         uint64_t reserved_7_7:1;
1141         uint64_t pid:7;
1142 #else
1143         uint64_t pid:7;
1144         uint64_t reserved_7_7:1;
1145         uint64_t rate_lim:24;
1146         uint64_t reserved_32_63:32;
1147 #endif
1148     } s;
1149     struct cvmx_pko_mem_port_rate1_cn52xx {
1150 #ifdef __BIG_ENDIAN_BITFIELD
1151         uint64_t reserved_32_63:32;
1152         uint64_t rate_lim:24;
1153         uint64_t reserved_6_7:2;
1154         uint64_t pid:6;
1155 #else
1156         uint64_t pid:6;
1157         uint64_t reserved_6_7:2;
1158         uint64_t rate_lim:24;
1159         uint64_t reserved_32_63:32;
1160 #endif
1161     } cn52xx;
1162 };
1163
1164 union cvmx_pko_mem_queue_ptrs {
1165     uint64_t u64;
1166     struct cvmx_pko_mem_queue_ptrs_s {
1167 #ifdef __BIG_ENDIAN_BITFIELD
1168         uint64_t s_tail:1;
1169         uint64_t static_p:1;
1170         uint64_t static_q:1;
1171         uint64_t qos_mask:8;
1172         uint64_t buf_ptr:36;
1173         uint64_t tail:1;
1174         uint64_t index:3;
1175         uint64_t port:6;
1176         uint64_t queue:7;
1177 #else
1178         uint64_t queue:7;
1179         uint64_t port:6;
1180         uint64_t index:3;
1181         uint64_t tail:1;
1182         uint64_t buf_ptr:36;
1183         uint64_t qos_mask:8;
1184         uint64_t static_q:1;
1185         uint64_t static_p:1;
1186         uint64_t s_tail:1;
1187 #endif
1188     } s;
1189 };
1190
1191 union cvmx_pko_mem_queue_qos {
1192     uint64_t u64;
1193     struct cvmx_pko_mem_queue_qos_s {
1194 #ifdef __BIG_ENDIAN_BITFIELD
1195         uint64_t reserved_61_63:3;
1196         uint64_t qos_mask:8;
1197         uint64_t reserved_13_52:40;
1198         uint64_t pid:6;
1199         uint64_t qid:7;
1200 #else
1201         uint64_t qid:7;
1202         uint64_t pid:6;
1203         uint64_t reserved_13_52:40;
1204         uint64_t qos_mask:8;
1205         uint64_t reserved_61_63:3;
1206 #endif
1207     } s;
1208 };
1209
1210 union cvmx_pko_mem_throttle_int {
1211     uint64_t u64;
1212     struct cvmx_pko_mem_throttle_int_s {
1213 #ifdef __BIG_ENDIAN_BITFIELD
1214         uint64_t reserved_47_63:17;
1215         uint64_t word:15;
1216         uint64_t reserved_14_31:18;
1217         uint64_t packet:6;
1218         uint64_t reserved_5_7:3;
1219         uint64_t intr:5;
1220 #else
1221         uint64_t intr:5;
1222         uint64_t reserved_5_7:3;
1223         uint64_t packet:6;
1224         uint64_t reserved_14_31:18;
1225         uint64_t word:15;
1226         uint64_t reserved_47_63:17;
1227 #endif
1228     } s;
1229 };
1230
1231 union cvmx_pko_mem_throttle_pipe {
1232     uint64_t u64;
1233     struct cvmx_pko_mem_throttle_pipe_s {
1234 #ifdef __BIG_ENDIAN_BITFIELD
1235         uint64_t reserved_47_63:17;
1236         uint64_t word:15;
1237         uint64_t reserved_14_31:18;
1238         uint64_t packet:6;
1239         uint64_t reserved_7_7:1;
1240         uint64_t pipe:7;
1241 #else
1242         uint64_t pipe:7;
1243         uint64_t reserved_7_7:1;
1244         uint64_t packet:6;
1245         uint64_t reserved_14_31:18;
1246         uint64_t word:15;
1247         uint64_t reserved_47_63:17;
1248 #endif
1249     } s;
1250 };
1251
1252 union cvmx_pko_reg_bist_result {
1253     uint64_t u64;
1254     struct cvmx_pko_reg_bist_result_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256         uint64_t reserved_0_63:64;
1257 #else
1258         uint64_t reserved_0_63:64;
1259 #endif
1260     } s;
1261     struct cvmx_pko_reg_bist_result_cn30xx {
1262 #ifdef __BIG_ENDIAN_BITFIELD
1263         uint64_t reserved_27_63:37;
1264         uint64_t psb2:5;
1265         uint64_t count:1;
1266         uint64_t rif:1;
1267         uint64_t wif:1;
1268         uint64_t ncb:1;
1269         uint64_t out:1;
1270         uint64_t crc:1;
1271         uint64_t chk:1;
1272         uint64_t qsb:2;
1273         uint64_t qcb:2;
1274         uint64_t pdb:4;
1275         uint64_t psb:7;
1276 #else
1277         uint64_t psb:7;
1278         uint64_t pdb:4;
1279         uint64_t qcb:2;
1280         uint64_t qsb:2;
1281         uint64_t chk:1;
1282         uint64_t crc:1;
1283         uint64_t out:1;
1284         uint64_t ncb:1;
1285         uint64_t wif:1;
1286         uint64_t rif:1;
1287         uint64_t count:1;
1288         uint64_t psb2:5;
1289         uint64_t reserved_27_63:37;
1290 #endif
1291     } cn30xx;
1292     struct cvmx_pko_reg_bist_result_cn50xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294         uint64_t reserved_33_63:31;
1295         uint64_t csr:1;
1296         uint64_t iob:1;
1297         uint64_t out_crc:1;
1298         uint64_t out_ctl:3;
1299         uint64_t out_sta:1;
1300         uint64_t out_wif:1;
1301         uint64_t prt_chk:3;
1302         uint64_t prt_nxt:1;
1303         uint64_t prt_psb:6;
1304         uint64_t ncb_inb:2;
1305         uint64_t prt_qcb:2;
1306         uint64_t prt_qsb:3;
1307         uint64_t dat_dat:4;
1308         uint64_t dat_ptr:4;
1309 #else
1310         uint64_t dat_ptr:4;
1311         uint64_t dat_dat:4;
1312         uint64_t prt_qsb:3;
1313         uint64_t prt_qcb:2;
1314         uint64_t ncb_inb:2;
1315         uint64_t prt_psb:6;
1316         uint64_t prt_nxt:1;
1317         uint64_t prt_chk:3;
1318         uint64_t out_wif:1;
1319         uint64_t out_sta:1;
1320         uint64_t out_ctl:3;
1321         uint64_t out_crc:1;
1322         uint64_t iob:1;
1323         uint64_t csr:1;
1324         uint64_t reserved_33_63:31;
1325 #endif
1326     } cn50xx;
1327     struct cvmx_pko_reg_bist_result_cn52xx {
1328 #ifdef __BIG_ENDIAN_BITFIELD
1329         uint64_t reserved_35_63:29;
1330         uint64_t csr:1;
1331         uint64_t iob:1;
1332         uint64_t out_dat:1;
1333         uint64_t out_ctl:3;
1334         uint64_t out_sta:1;
1335         uint64_t out_wif:1;
1336         uint64_t prt_chk:3;
1337         uint64_t prt_nxt:1;
1338         uint64_t prt_psb:8;
1339         uint64_t ncb_inb:2;
1340         uint64_t prt_qcb:2;
1341         uint64_t prt_qsb:3;
1342         uint64_t prt_ctl:2;
1343         uint64_t dat_dat:2;
1344         uint64_t dat_ptr:4;
1345 #else
1346         uint64_t dat_ptr:4;
1347         uint64_t dat_dat:2;
1348         uint64_t prt_ctl:2;
1349         uint64_t prt_qsb:3;
1350         uint64_t prt_qcb:2;
1351         uint64_t ncb_inb:2;
1352         uint64_t prt_psb:8;
1353         uint64_t prt_nxt:1;
1354         uint64_t prt_chk:3;
1355         uint64_t out_wif:1;
1356         uint64_t out_sta:1;
1357         uint64_t out_ctl:3;
1358         uint64_t out_dat:1;
1359         uint64_t iob:1;
1360         uint64_t csr:1;
1361         uint64_t reserved_35_63:29;
1362 #endif
1363     } cn52xx;
1364     struct cvmx_pko_reg_bist_result_cn68xx {
1365 #ifdef __BIG_ENDIAN_BITFIELD
1366         uint64_t reserved_36_63:28;
1367         uint64_t crc:1;
1368         uint64_t csr:1;
1369         uint64_t iob:1;
1370         uint64_t out_dat:1;
1371         uint64_t reserved_31_31:1;
1372         uint64_t out_ctl:2;
1373         uint64_t out_sta:1;
1374         uint64_t out_wif:1;
1375         uint64_t prt_chk:3;
1376         uint64_t prt_nxt:1;
1377         uint64_t prt_psb7:1;
1378         uint64_t reserved_21_21:1;
1379         uint64_t prt_psb:6;
1380         uint64_t ncb_inb:2;
1381         uint64_t prt_qcb:2;
1382         uint64_t prt_qsb:3;
1383         uint64_t prt_ctl:2;
1384         uint64_t dat_dat:2;
1385         uint64_t dat_ptr:4;
1386 #else
1387         uint64_t dat_ptr:4;
1388         uint64_t dat_dat:2;
1389         uint64_t prt_ctl:2;
1390         uint64_t prt_qsb:3;
1391         uint64_t prt_qcb:2;
1392         uint64_t ncb_inb:2;
1393         uint64_t prt_psb:6;
1394         uint64_t reserved_21_21:1;
1395         uint64_t prt_psb7:1;
1396         uint64_t prt_nxt:1;
1397         uint64_t prt_chk:3;
1398         uint64_t out_wif:1;
1399         uint64_t out_sta:1;
1400         uint64_t out_ctl:2;
1401         uint64_t reserved_31_31:1;
1402         uint64_t out_dat:1;
1403         uint64_t iob:1;
1404         uint64_t csr:1;
1405         uint64_t crc:1;
1406         uint64_t reserved_36_63:28;
1407 #endif
1408     } cn68xx;
1409     struct cvmx_pko_reg_bist_result_cn68xxp1 {
1410 #ifdef __BIG_ENDIAN_BITFIELD
1411         uint64_t reserved_35_63:29;
1412         uint64_t csr:1;
1413         uint64_t iob:1;
1414         uint64_t out_dat:1;
1415         uint64_t reserved_31_31:1;
1416         uint64_t out_ctl:2;
1417         uint64_t out_sta:1;
1418         uint64_t out_wif:1;
1419         uint64_t prt_chk:3;
1420         uint64_t prt_nxt:1;
1421         uint64_t prt_psb7:1;
1422         uint64_t reserved_21_21:1;
1423         uint64_t prt_psb:6;
1424         uint64_t ncb_inb:2;
1425         uint64_t prt_qcb:2;
1426         uint64_t prt_qsb:3;
1427         uint64_t prt_ctl:2;
1428         uint64_t dat_dat:2;
1429         uint64_t dat_ptr:4;
1430 #else
1431         uint64_t dat_ptr:4;
1432         uint64_t dat_dat:2;
1433         uint64_t prt_ctl:2;
1434         uint64_t prt_qsb:3;
1435         uint64_t prt_qcb:2;
1436         uint64_t ncb_inb:2;
1437         uint64_t prt_psb:6;
1438         uint64_t reserved_21_21:1;
1439         uint64_t prt_psb7:1;
1440         uint64_t prt_nxt:1;
1441         uint64_t prt_chk:3;
1442         uint64_t out_wif:1;
1443         uint64_t out_sta:1;
1444         uint64_t out_ctl:2;
1445         uint64_t reserved_31_31:1;
1446         uint64_t out_dat:1;
1447         uint64_t iob:1;
1448         uint64_t csr:1;
1449         uint64_t reserved_35_63:29;
1450 #endif
1451     } cn68xxp1;
1452 };
1453
1454 union cvmx_pko_reg_cmd_buf {
1455     uint64_t u64;
1456     struct cvmx_pko_reg_cmd_buf_s {
1457 #ifdef __BIG_ENDIAN_BITFIELD
1458         uint64_t reserved_23_63:41;
1459         uint64_t pool:3;
1460         uint64_t reserved_13_19:7;
1461         uint64_t size:13;
1462 #else
1463         uint64_t size:13;
1464         uint64_t reserved_13_19:7;
1465         uint64_t pool:3;
1466         uint64_t reserved_23_63:41;
1467 #endif
1468     } s;
1469 };
1470
1471 union cvmx_pko_reg_crc_ctlx {
1472     uint64_t u64;
1473     struct cvmx_pko_reg_crc_ctlx_s {
1474 #ifdef __BIG_ENDIAN_BITFIELD
1475         uint64_t reserved_2_63:62;
1476         uint64_t invres:1;
1477         uint64_t refin:1;
1478 #else
1479         uint64_t refin:1;
1480         uint64_t invres:1;
1481         uint64_t reserved_2_63:62;
1482 #endif
1483     } s;
1484 };
1485
1486 union cvmx_pko_reg_crc_enable {
1487     uint64_t u64;
1488     struct cvmx_pko_reg_crc_enable_s {
1489 #ifdef __BIG_ENDIAN_BITFIELD
1490         uint64_t reserved_32_63:32;
1491         uint64_t enable:32;
1492 #else
1493         uint64_t enable:32;
1494         uint64_t reserved_32_63:32;
1495 #endif
1496     } s;
1497 };
1498
1499 union cvmx_pko_reg_crc_ivx {
1500     uint64_t u64;
1501     struct cvmx_pko_reg_crc_ivx_s {
1502 #ifdef __BIG_ENDIAN_BITFIELD
1503         uint64_t reserved_32_63:32;
1504         uint64_t iv:32;
1505 #else
1506         uint64_t iv:32;
1507         uint64_t reserved_32_63:32;
1508 #endif
1509     } s;
1510 };
1511
1512 union cvmx_pko_reg_debug0 {
1513     uint64_t u64;
1514     struct cvmx_pko_reg_debug0_s {
1515 #ifdef __BIG_ENDIAN_BITFIELD
1516         uint64_t asserts:64;
1517 #else
1518         uint64_t asserts:64;
1519 #endif
1520     } s;
1521     struct cvmx_pko_reg_debug0_cn30xx {
1522 #ifdef __BIG_ENDIAN_BITFIELD
1523         uint64_t reserved_17_63:47;
1524         uint64_t asserts:17;
1525 #else
1526         uint64_t asserts:17;
1527         uint64_t reserved_17_63:47;
1528 #endif
1529     } cn30xx;
1530 };
1531
1532 union cvmx_pko_reg_debug1 {
1533     uint64_t u64;
1534     struct cvmx_pko_reg_debug1_s {
1535 #ifdef __BIG_ENDIAN_BITFIELD
1536         uint64_t asserts:64;
1537 #else
1538         uint64_t asserts:64;
1539 #endif
1540     } s;
1541 };
1542
1543 union cvmx_pko_reg_debug2 {
1544     uint64_t u64;
1545     struct cvmx_pko_reg_debug2_s {
1546 #ifdef __BIG_ENDIAN_BITFIELD
1547         uint64_t asserts:64;
1548 #else
1549         uint64_t asserts:64;
1550 #endif
1551     } s;
1552 };
1553
1554 union cvmx_pko_reg_debug3 {
1555     uint64_t u64;
1556     struct cvmx_pko_reg_debug3_s {
1557 #ifdef __BIG_ENDIAN_BITFIELD
1558         uint64_t asserts:64;
1559 #else
1560         uint64_t asserts:64;
1561 #endif
1562     } s;
1563 };
1564
1565 union cvmx_pko_reg_debug4 {
1566     uint64_t u64;
1567     struct cvmx_pko_reg_debug4_s {
1568 #ifdef __BIG_ENDIAN_BITFIELD
1569         uint64_t asserts:64;
1570 #else
1571         uint64_t asserts:64;
1572 #endif
1573     } s;
1574 };
1575
1576 union cvmx_pko_reg_engine_inflight {
1577     uint64_t u64;
1578     struct cvmx_pko_reg_engine_inflight_s {
1579 #ifdef __BIG_ENDIAN_BITFIELD
1580         uint64_t engine15:4;
1581         uint64_t engine14:4;
1582         uint64_t engine13:4;
1583         uint64_t engine12:4;
1584         uint64_t engine11:4;
1585         uint64_t engine10:4;
1586         uint64_t engine9:4;
1587         uint64_t engine8:4;
1588         uint64_t engine7:4;
1589         uint64_t engine6:4;
1590         uint64_t engine5:4;
1591         uint64_t engine4:4;
1592         uint64_t engine3:4;
1593         uint64_t engine2:4;
1594         uint64_t engine1:4;
1595         uint64_t engine0:4;
1596 #else
1597         uint64_t engine0:4;
1598         uint64_t engine1:4;
1599         uint64_t engine2:4;
1600         uint64_t engine3:4;
1601         uint64_t engine4:4;
1602         uint64_t engine5:4;
1603         uint64_t engine6:4;
1604         uint64_t engine7:4;
1605         uint64_t engine8:4;
1606         uint64_t engine9:4;
1607         uint64_t engine10:4;
1608         uint64_t engine11:4;
1609         uint64_t engine12:4;
1610         uint64_t engine13:4;
1611         uint64_t engine14:4;
1612         uint64_t engine15:4;
1613 #endif
1614     } s;
1615     struct cvmx_pko_reg_engine_inflight_cn52xx {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617         uint64_t reserved_40_63:24;
1618         uint64_t engine9:4;
1619         uint64_t engine8:4;
1620         uint64_t engine7:4;
1621         uint64_t engine6:4;
1622         uint64_t engine5:4;
1623         uint64_t engine4:4;
1624         uint64_t engine3:4;
1625         uint64_t engine2:4;
1626         uint64_t engine1:4;
1627         uint64_t engine0:4;
1628 #else
1629         uint64_t engine0:4;
1630         uint64_t engine1:4;
1631         uint64_t engine2:4;
1632         uint64_t engine3:4;
1633         uint64_t engine4:4;
1634         uint64_t engine5:4;
1635         uint64_t engine6:4;
1636         uint64_t engine7:4;
1637         uint64_t engine8:4;
1638         uint64_t engine9:4;
1639         uint64_t reserved_40_63:24;
1640 #endif
1641     } cn52xx;
1642     struct cvmx_pko_reg_engine_inflight_cn61xx {
1643 #ifdef __BIG_ENDIAN_BITFIELD
1644         uint64_t reserved_56_63:8;
1645         uint64_t engine13:4;
1646         uint64_t engine12:4;
1647         uint64_t engine11:4;
1648         uint64_t engine10:4;
1649         uint64_t engine9:4;
1650         uint64_t engine8:4;
1651         uint64_t engine7:4;
1652         uint64_t engine6:4;
1653         uint64_t engine5:4;
1654         uint64_t engine4:4;
1655         uint64_t engine3:4;
1656         uint64_t engine2:4;
1657         uint64_t engine1:4;
1658         uint64_t engine0:4;
1659 #else
1660         uint64_t engine0:4;
1661         uint64_t engine1:4;
1662         uint64_t engine2:4;
1663         uint64_t engine3:4;
1664         uint64_t engine4:4;
1665         uint64_t engine5:4;
1666         uint64_t engine6:4;
1667         uint64_t engine7:4;
1668         uint64_t engine8:4;
1669         uint64_t engine9:4;
1670         uint64_t engine10:4;
1671         uint64_t engine11:4;
1672         uint64_t engine12:4;
1673         uint64_t engine13:4;
1674         uint64_t reserved_56_63:8;
1675 #endif
1676     } cn61xx;
1677     struct cvmx_pko_reg_engine_inflight_cn63xx {
1678 #ifdef __BIG_ENDIAN_BITFIELD
1679         uint64_t reserved_48_63:16;
1680         uint64_t engine11:4;
1681         uint64_t engine10:4;
1682         uint64_t engine9:4;
1683         uint64_t engine8:4;
1684         uint64_t engine7:4;
1685         uint64_t engine6:4;
1686         uint64_t engine5:4;
1687         uint64_t engine4:4;
1688         uint64_t engine3:4;
1689         uint64_t engine2:4;
1690         uint64_t engine1:4;
1691         uint64_t engine0:4;
1692 #else
1693         uint64_t engine0:4;
1694         uint64_t engine1:4;
1695         uint64_t engine2:4;
1696         uint64_t engine3:4;
1697         uint64_t engine4:4;
1698         uint64_t engine5:4;
1699         uint64_t engine6:4;
1700         uint64_t engine7:4;
1701         uint64_t engine8:4;
1702         uint64_t engine9:4;
1703         uint64_t engine10:4;
1704         uint64_t engine11:4;
1705         uint64_t reserved_48_63:16;
1706 #endif
1707     } cn63xx;
1708 };
1709
1710 union cvmx_pko_reg_engine_inflight1 {
1711     uint64_t u64;
1712     struct cvmx_pko_reg_engine_inflight1_s {
1713 #ifdef __BIG_ENDIAN_BITFIELD
1714         uint64_t reserved_16_63:48;
1715         uint64_t engine19:4;
1716         uint64_t engine18:4;
1717         uint64_t engine17:4;
1718         uint64_t engine16:4;
1719 #else
1720         uint64_t engine16:4;
1721         uint64_t engine17:4;
1722         uint64_t engine18:4;
1723         uint64_t engine19:4;
1724         uint64_t reserved_16_63:48;
1725 #endif
1726     } s;
1727 };
1728
1729 union cvmx_pko_reg_engine_storagex {
1730     uint64_t u64;
1731     struct cvmx_pko_reg_engine_storagex_s {
1732 #ifdef __BIG_ENDIAN_BITFIELD
1733         uint64_t engine15:4;
1734         uint64_t engine14:4;
1735         uint64_t engine13:4;
1736         uint64_t engine12:4;
1737         uint64_t engine11:4;
1738         uint64_t engine10:4;
1739         uint64_t engine9:4;
1740         uint64_t engine8:4;
1741         uint64_t engine7:4;
1742         uint64_t engine6:4;
1743         uint64_t engine5:4;
1744         uint64_t engine4:4;
1745         uint64_t engine3:4;
1746         uint64_t engine2:4;
1747         uint64_t engine1:4;
1748         uint64_t engine0:4;
1749 #else
1750         uint64_t engine0:4;
1751         uint64_t engine1:4;
1752         uint64_t engine2:4;
1753         uint64_t engine3:4;
1754         uint64_t engine4:4;
1755         uint64_t engine5:4;
1756         uint64_t engine6:4;
1757         uint64_t engine7:4;
1758         uint64_t engine8:4;
1759         uint64_t engine9:4;
1760         uint64_t engine10:4;
1761         uint64_t engine11:4;
1762         uint64_t engine12:4;
1763         uint64_t engine13:4;
1764         uint64_t engine14:4;
1765         uint64_t engine15:4;
1766 #endif
1767     } s;
1768 };
1769
1770 union cvmx_pko_reg_engine_thresh {
1771     uint64_t u64;
1772     struct cvmx_pko_reg_engine_thresh_s {
1773 #ifdef __BIG_ENDIAN_BITFIELD
1774         uint64_t reserved_20_63:44;
1775         uint64_t mask:20;
1776 #else
1777         uint64_t mask:20;
1778         uint64_t reserved_20_63:44;
1779 #endif
1780     } s;
1781     struct cvmx_pko_reg_engine_thresh_cn52xx {
1782 #ifdef __BIG_ENDIAN_BITFIELD
1783         uint64_t reserved_10_63:54;
1784         uint64_t mask:10;
1785 #else
1786         uint64_t mask:10;
1787         uint64_t reserved_10_63:54;
1788 #endif
1789     } cn52xx;
1790     struct cvmx_pko_reg_engine_thresh_cn61xx {
1791 #ifdef __BIG_ENDIAN_BITFIELD
1792         uint64_t reserved_14_63:50;
1793         uint64_t mask:14;
1794 #else
1795         uint64_t mask:14;
1796         uint64_t reserved_14_63:50;
1797 #endif
1798     } cn61xx;
1799     struct cvmx_pko_reg_engine_thresh_cn63xx {
1800 #ifdef __BIG_ENDIAN_BITFIELD
1801         uint64_t reserved_12_63:52;
1802         uint64_t mask:12;
1803 #else
1804         uint64_t mask:12;
1805         uint64_t reserved_12_63:52;
1806 #endif
1807     } cn63xx;
1808 };
1809
1810 union cvmx_pko_reg_error {
1811     uint64_t u64;
1812     struct cvmx_pko_reg_error_s {
1813 #ifdef __BIG_ENDIAN_BITFIELD
1814         uint64_t reserved_4_63:60;
1815         uint64_t loopback:1;
1816         uint64_t currzero:1;
1817         uint64_t doorbell:1;
1818         uint64_t parity:1;
1819 #else
1820         uint64_t parity:1;
1821         uint64_t doorbell:1;
1822         uint64_t currzero:1;
1823         uint64_t loopback:1;
1824         uint64_t reserved_4_63:60;
1825 #endif
1826     } s;
1827     struct cvmx_pko_reg_error_cn30xx {
1828 #ifdef __BIG_ENDIAN_BITFIELD
1829         uint64_t reserved_2_63:62;
1830         uint64_t doorbell:1;
1831         uint64_t parity:1;
1832 #else
1833         uint64_t parity:1;
1834         uint64_t doorbell:1;
1835         uint64_t reserved_2_63:62;
1836 #endif
1837     } cn30xx;
1838     struct cvmx_pko_reg_error_cn50xx {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840         uint64_t reserved_3_63:61;
1841         uint64_t currzero:1;
1842         uint64_t doorbell:1;
1843         uint64_t parity:1;
1844 #else
1845         uint64_t parity:1;
1846         uint64_t doorbell:1;
1847         uint64_t currzero:1;
1848         uint64_t reserved_3_63:61;
1849 #endif
1850     } cn50xx;
1851 };
1852
1853 union cvmx_pko_reg_flags {
1854     uint64_t u64;
1855     struct cvmx_pko_reg_flags_s {
1856 #ifdef __BIG_ENDIAN_BITFIELD
1857         uint64_t reserved_9_63:55;
1858         uint64_t dis_perf3:1;
1859         uint64_t dis_perf2:1;
1860         uint64_t dis_perf1:1;
1861         uint64_t dis_perf0:1;
1862         uint64_t ena_throttle:1;
1863         uint64_t reset:1;
1864         uint64_t store_be:1;
1865         uint64_t ena_dwb:1;
1866         uint64_t ena_pko:1;
1867 #else
1868         uint64_t ena_pko:1;
1869         uint64_t ena_dwb:1;
1870         uint64_t store_be:1;
1871         uint64_t reset:1;
1872         uint64_t ena_throttle:1;
1873         uint64_t dis_perf0:1;
1874         uint64_t dis_perf1:1;
1875         uint64_t dis_perf2:1;
1876         uint64_t dis_perf3:1;
1877         uint64_t reserved_9_63:55;
1878 #endif
1879     } s;
1880     struct cvmx_pko_reg_flags_cn30xx {
1881 #ifdef __BIG_ENDIAN_BITFIELD
1882         uint64_t reserved_4_63:60;
1883         uint64_t reset:1;
1884         uint64_t store_be:1;
1885         uint64_t ena_dwb:1;
1886         uint64_t ena_pko:1;
1887 #else
1888         uint64_t ena_pko:1;
1889         uint64_t ena_dwb:1;
1890         uint64_t store_be:1;
1891         uint64_t reset:1;
1892         uint64_t reserved_4_63:60;
1893 #endif
1894     } cn30xx;
1895     struct cvmx_pko_reg_flags_cn61xx {
1896 #ifdef __BIG_ENDIAN_BITFIELD
1897         uint64_t reserved_9_63:55;
1898         uint64_t dis_perf3:1;
1899         uint64_t dis_perf2:1;
1900         uint64_t reserved_4_6:3;
1901         uint64_t reset:1;
1902         uint64_t store_be:1;
1903         uint64_t ena_dwb:1;
1904         uint64_t ena_pko:1;
1905 #else
1906         uint64_t ena_pko:1;
1907         uint64_t ena_dwb:1;
1908         uint64_t store_be:1;
1909         uint64_t reset:1;
1910         uint64_t reserved_4_6:3;
1911         uint64_t dis_perf2:1;
1912         uint64_t dis_perf3:1;
1913         uint64_t reserved_9_63:55;
1914 #endif
1915     } cn61xx;
1916     struct cvmx_pko_reg_flags_cn68xxp1 {
1917 #ifdef __BIG_ENDIAN_BITFIELD
1918         uint64_t reserved_7_63:57;
1919         uint64_t dis_perf1:1;
1920         uint64_t dis_perf0:1;
1921         uint64_t ena_throttle:1;
1922         uint64_t reset:1;
1923         uint64_t store_be:1;
1924         uint64_t ena_dwb:1;
1925         uint64_t ena_pko:1;
1926 #else
1927         uint64_t ena_pko:1;
1928         uint64_t ena_dwb:1;
1929         uint64_t store_be:1;
1930         uint64_t reset:1;
1931         uint64_t ena_throttle:1;
1932         uint64_t dis_perf0:1;
1933         uint64_t dis_perf1:1;
1934         uint64_t reserved_7_63:57;
1935 #endif
1936     } cn68xxp1;
1937 };
1938
1939 union cvmx_pko_reg_gmx_port_mode {
1940     uint64_t u64;
1941     struct cvmx_pko_reg_gmx_port_mode_s {
1942 #ifdef __BIG_ENDIAN_BITFIELD
1943         uint64_t reserved_6_63:58;
1944         uint64_t mode1:3;
1945         uint64_t mode0:3;
1946 #else
1947         uint64_t mode0:3;
1948         uint64_t mode1:3;
1949         uint64_t reserved_6_63:58;
1950 #endif
1951     } s;
1952 };
1953
1954 union cvmx_pko_reg_int_mask {
1955     uint64_t u64;
1956     struct cvmx_pko_reg_int_mask_s {
1957 #ifdef __BIG_ENDIAN_BITFIELD
1958         uint64_t reserved_4_63:60;
1959         uint64_t loopback:1;
1960         uint64_t currzero:1;
1961         uint64_t doorbell:1;
1962         uint64_t parity:1;
1963 #else
1964         uint64_t parity:1;
1965         uint64_t doorbell:1;
1966         uint64_t currzero:1;
1967         uint64_t loopback:1;
1968         uint64_t reserved_4_63:60;
1969 #endif
1970     } s;
1971     struct cvmx_pko_reg_int_mask_cn30xx {
1972 #ifdef __BIG_ENDIAN_BITFIELD
1973         uint64_t reserved_2_63:62;
1974         uint64_t doorbell:1;
1975         uint64_t parity:1;
1976 #else
1977         uint64_t parity:1;
1978         uint64_t doorbell:1;
1979         uint64_t reserved_2_63:62;
1980 #endif
1981     } cn30xx;
1982     struct cvmx_pko_reg_int_mask_cn50xx {
1983 #ifdef __BIG_ENDIAN_BITFIELD
1984         uint64_t reserved_3_63:61;
1985         uint64_t currzero:1;
1986         uint64_t doorbell:1;
1987         uint64_t parity:1;
1988 #else
1989         uint64_t parity:1;
1990         uint64_t doorbell:1;
1991         uint64_t currzero:1;
1992         uint64_t reserved_3_63:61;
1993 #endif
1994     } cn50xx;
1995 };
1996
1997 union cvmx_pko_reg_loopback_bpid {
1998     uint64_t u64;
1999     struct cvmx_pko_reg_loopback_bpid_s {
2000 #ifdef __BIG_ENDIAN_BITFIELD
2001         uint64_t reserved_59_63:5;
2002         uint64_t bpid7:6;
2003         uint64_t reserved_52_52:1;
2004         uint64_t bpid6:6;
2005         uint64_t reserved_45_45:1;
2006         uint64_t bpid5:6;
2007         uint64_t reserved_38_38:1;
2008         uint64_t bpid4:6;
2009         uint64_t reserved_31_31:1;
2010         uint64_t bpid3:6;
2011         uint64_t reserved_24_24:1;
2012         uint64_t bpid2:6;
2013         uint64_t reserved_17_17:1;
2014         uint64_t bpid1:6;
2015         uint64_t reserved_10_10:1;
2016         uint64_t bpid0:6;
2017         uint64_t reserved_0_3:4;
2018 #else
2019         uint64_t reserved_0_3:4;
2020         uint64_t bpid0:6;
2021         uint64_t reserved_10_10:1;
2022         uint64_t bpid1:6;
2023         uint64_t reserved_17_17:1;
2024         uint64_t bpid2:6;
2025         uint64_t reserved_24_24:1;
2026         uint64_t bpid3:6;
2027         uint64_t reserved_31_31:1;
2028         uint64_t bpid4:6;
2029         uint64_t reserved_38_38:1;
2030         uint64_t bpid5:6;
2031         uint64_t reserved_45_45:1;
2032         uint64_t bpid6:6;
2033         uint64_t reserved_52_52:1;
2034         uint64_t bpid7:6;
2035         uint64_t reserved_59_63:5;
2036 #endif
2037     } s;
2038 };
2039
2040 union cvmx_pko_reg_loopback_pkind {
2041     uint64_t u64;
2042     struct cvmx_pko_reg_loopback_pkind_s {
2043 #ifdef __BIG_ENDIAN_BITFIELD
2044         uint64_t reserved_59_63:5;
2045         uint64_t pkind7:6;
2046         uint64_t reserved_52_52:1;
2047         uint64_t pkind6:6;
2048         uint64_t reserved_45_45:1;
2049         uint64_t pkind5:6;
2050         uint64_t reserved_38_38:1;
2051         uint64_t pkind4:6;
2052         uint64_t reserved_31_31:1;
2053         uint64_t pkind3:6;
2054         uint64_t reserved_24_24:1;
2055         uint64_t pkind2:6;
2056         uint64_t reserved_17_17:1;
2057         uint64_t pkind1:6;
2058         uint64_t reserved_10_10:1;
2059         uint64_t pkind0:6;
2060         uint64_t num_ports:4;
2061 #else
2062         uint64_t num_ports:4;
2063         uint64_t pkind0:6;
2064         uint64_t reserved_10_10:1;
2065         uint64_t pkind1:6;
2066         uint64_t reserved_17_17:1;
2067         uint64_t pkind2:6;
2068         uint64_t reserved_24_24:1;
2069         uint64_t pkind3:6;
2070         uint64_t reserved_31_31:1;
2071         uint64_t pkind4:6;
2072         uint64_t reserved_38_38:1;
2073         uint64_t pkind5:6;
2074         uint64_t reserved_45_45:1;
2075         uint64_t pkind6:6;
2076         uint64_t reserved_52_52:1;
2077         uint64_t pkind7:6;
2078         uint64_t reserved_59_63:5;
2079 #endif
2080     } s;
2081 };
2082
2083 union cvmx_pko_reg_min_pkt {
2084     uint64_t u64;
2085     struct cvmx_pko_reg_min_pkt_s {
2086 #ifdef __BIG_ENDIAN_BITFIELD
2087         uint64_t size7:8;
2088         uint64_t size6:8;
2089         uint64_t size5:8;
2090         uint64_t size4:8;
2091         uint64_t size3:8;
2092         uint64_t size2:8;
2093         uint64_t size1:8;
2094         uint64_t size0:8;
2095 #else
2096         uint64_t size0:8;
2097         uint64_t size1:8;
2098         uint64_t size2:8;
2099         uint64_t size3:8;
2100         uint64_t size4:8;
2101         uint64_t size5:8;
2102         uint64_t size6:8;
2103         uint64_t size7:8;
2104 #endif
2105     } s;
2106 };
2107
2108 union cvmx_pko_reg_preempt {
2109     uint64_t u64;
2110     struct cvmx_pko_reg_preempt_s {
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112         uint64_t reserved_16_63:48;
2113         uint64_t min_size:16;
2114 #else
2115         uint64_t min_size:16;
2116         uint64_t reserved_16_63:48;
2117 #endif
2118     } s;
2119 };
2120
2121 union cvmx_pko_reg_queue_mode {
2122     uint64_t u64;
2123     struct cvmx_pko_reg_queue_mode_s {
2124 #ifdef __BIG_ENDIAN_BITFIELD
2125         uint64_t reserved_2_63:62;
2126         uint64_t mode:2;
2127 #else
2128         uint64_t mode:2;
2129         uint64_t reserved_2_63:62;
2130 #endif
2131     } s;
2132 };
2133
2134 union cvmx_pko_reg_queue_preempt {
2135     uint64_t u64;
2136     struct cvmx_pko_reg_queue_preempt_s {
2137 #ifdef __BIG_ENDIAN_BITFIELD
2138         uint64_t reserved_2_63:62;
2139         uint64_t preemptee:1;
2140         uint64_t preempter:1;
2141 #else
2142         uint64_t preempter:1;
2143         uint64_t preemptee:1;
2144         uint64_t reserved_2_63:62;
2145 #endif
2146     } s;
2147 };
2148
2149 union cvmx_pko_reg_queue_ptrs1 {
2150     uint64_t u64;
2151     struct cvmx_pko_reg_queue_ptrs1_s {
2152 #ifdef __BIG_ENDIAN_BITFIELD
2153         uint64_t reserved_2_63:62;
2154         uint64_t idx3:1;
2155         uint64_t qid7:1;
2156 #else
2157         uint64_t qid7:1;
2158         uint64_t idx3:1;
2159         uint64_t reserved_2_63:62;
2160 #endif
2161     } s;
2162 };
2163
2164 union cvmx_pko_reg_read_idx {
2165     uint64_t u64;
2166     struct cvmx_pko_reg_read_idx_s {
2167 #ifdef __BIG_ENDIAN_BITFIELD
2168         uint64_t reserved_16_63:48;
2169         uint64_t inc:8;
2170         uint64_t index:8;
2171 #else
2172         uint64_t index:8;
2173         uint64_t inc:8;
2174         uint64_t reserved_16_63:48;
2175 #endif
2176     } s;
2177 };
2178
2179 union cvmx_pko_reg_throttle {
2180     uint64_t u64;
2181     struct cvmx_pko_reg_throttle_s {
2182 #ifdef __BIG_ENDIAN_BITFIELD
2183         uint64_t reserved_32_63:32;
2184         uint64_t int_mask:32;
2185 #else
2186         uint64_t int_mask:32;
2187         uint64_t reserved_32_63:32;
2188 #endif
2189     } s;
2190 };
2191
2192 union cvmx_pko_reg_timestamp {
2193     uint64_t u64;
2194     struct cvmx_pko_reg_timestamp_s {
2195 #ifdef __BIG_ENDIAN_BITFIELD
2196         uint64_t reserved_4_63:60;
2197         uint64_t wqe_word:4;
2198 #else
2199         uint64_t wqe_word:4;
2200         uint64_t reserved_4_63:60;
2201 #endif
2202     } s;
2203 };
2204
2205 #endif