asm/octeon/cvmx-pip.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2008 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /*
0029  * Interface to the hardware Packet Input Processing unit.
0030  *
0031  */
0032
0033 #ifndef __CVMX_PIP_H__
0034 #define __CVMX_PIP_H__
0035
0036 #include <asm/octeon/cvmx-wqe.h>
0037 #include <asm/octeon/cvmx-fpa.h>
0038 #include <asm/octeon/cvmx-pip-defs.h>
0039
0040 #define CVMX_PIP_NUM_INPUT_PORTS        48
0041 #define CVMX_PIP_NUM_WATCHERS           4
0042
0043 /*
0044  * Encodes the different error and exception codes
0045  */
0046 typedef enum {
0047     CVMX_PIP_L4_NO_ERR = 0ull,
0048     /*
0049      * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
0050      * header
0051      */
0052     CVMX_PIP_L4_MAL_ERR = 1ull,
0053     /* 2  = TCP/UDP checksum failure */
0054     CVMX_PIP_CHK_ERR = 2ull,
0055     /*
0056      * 3 = TCP/UDP length check (TCP/UDP length does not match IP
0057      * length).
0058      */
0059     CVMX_PIP_L4_LENGTH_ERR = 3ull,
0060     /* 4  = illegal TCP/UDP port (either source or dest port is zero) */
0061     CVMX_PIP_BAD_PRT_ERR = 4ull,
0062     /* 8  = TCP flags = FIN only */
0063     CVMX_PIP_TCP_FLG8_ERR = 8ull,
0064     /* 9  = TCP flags = 0 */
0065     CVMX_PIP_TCP_FLG9_ERR = 9ull,
0066     /* 10 = TCP flags = FIN+RST+* */
0067     CVMX_PIP_TCP_FLG10_ERR = 10ull,
0068     /* 11 = TCP flags = SYN+URG+* */
0069     CVMX_PIP_TCP_FLG11_ERR = 11ull,
0070     /* 12 = TCP flags = SYN+RST+* */
0071     CVMX_PIP_TCP_FLG12_ERR = 12ull,
0072     /* 13 = TCP flags = SYN+FIN+* */
0073     CVMX_PIP_TCP_FLG13_ERR = 13ull
0074 } cvmx_pip_l4_err_t;
0075
0076 typedef enum {
0077
0078     CVMX_PIP_IP_NO_ERR = 0ull,
0079     /* 1 = not IPv4 or IPv6 */
0080     CVMX_PIP_NOT_IP = 1ull,
0081     /* 2 = IPv4 header checksum violation */
0082     CVMX_PIP_IPV4_HDR_CHK = 2ull,
0083     /* 3 = malformed (packet not long enough to cover IP hdr) */
0084     CVMX_PIP_IP_MAL_HDR = 3ull,
0085     /* 4 = malformed (packet not long enough to cover len in IP hdr) */
0086     CVMX_PIP_IP_MAL_PKT = 4ull,
0087     /* 5 = TTL / hop count equal zero */
0088     CVMX_PIP_TTL_HOP = 5ull,
0089     /* 6 = IPv4 options / IPv6 early extension headers */
0090     CVMX_PIP_OPTS = 6ull
0091 } cvmx_pip_ip_exc_t;
0092
0093 /**
0094  * NOTES
0095  *   late collision (data received before collision)
0096  *        late collisions cannot be detected by the receiver
0097  *        they would appear as JAM bits which would appear as bad FCS
0098  *        or carrier extend error which is CVMX_PIP_EXTEND_ERR
0099  */
0100 typedef enum {
0101     /* No error */
0102     CVMX_PIP_RX_NO_ERR = 0ull,
0103     /* RGM+SPI 1 = partially received packet (buffering/bandwidth
0104      * not adequate) */
0105     CVMX_PIP_PARTIAL_ERR = 1ull,
0106     /* RGM+SPI 2 = receive packet too large and truncated */
0107     CVMX_PIP_JABBER_ERR = 2ull,
0108     /*
0109      * RGM 3 = max frame error (pkt len > max frame len) (with FCS
0110      * error)
0111      */
0112     CVMX_PIP_OVER_FCS_ERR = 3ull,
0113     /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
0114     CVMX_PIP_OVER_ERR = 4ull,
0115     /*
0116      * RGM 5 = nibble error (data not byte multiple - 100M and 10M
0117      * only)
0118      */
0119     CVMX_PIP_ALIGN_ERR = 5ull,
0120     /*
0121      * RGM 6 = min frame error (pkt len < min frame len) (with FCS
0122      * error)
0123      */
0124     CVMX_PIP_UNDER_FCS_ERR = 6ull,
0125     /* RGM     7 = FCS error */
0126     CVMX_PIP_GMX_FCS_ERR = 7ull,
0127     /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
0128     CVMX_PIP_UNDER_ERR = 8ull,
0129     /* RGM     9 = Frame carrier extend error */
0130     CVMX_PIP_EXTEND_ERR = 9ull,
0131     /*
0132      * RGM 10 = length mismatch (len did not match len in L2
0133      * length/type)
0134      */
0135     CVMX_PIP_LENGTH_ERR = 10ull,
0136     /* RGM 11 = Frame error (some or all data bits marked err) */
0137     CVMX_PIP_DAT_ERR = 11ull,
0138     /*     SPI 11 = DIP4 error */
0139     CVMX_PIP_DIP_ERR = 11ull,
0140     /*
0141      * RGM 12 = packet was not large enough to pass the skipper -
0142      * no inspection could occur.
0143      */
0144     CVMX_PIP_SKIP_ERR = 12ull,
0145     /*
0146      * RGM 13 = studder error (data not repeated - 100M and 10M
0147      * only)
0148      */
0149     CVMX_PIP_NIBBLE_ERR = 13ull,
0150     /* RGM+SPI 16 = FCS error */
0151     CVMX_PIP_PIP_FCS = 16L,
0152     /*
0153      * RGM+SPI+PCI 17 = packet was not large enough to pass the
0154      * skipper - no inspection could occur.
0155      */
0156     CVMX_PIP_PIP_SKIP_ERR = 17L,
0157     /*
0158      * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
0159      * cover L2 hdr).
0160      */
0161     CVMX_PIP_PIP_L2_MAL_HDR = 18L
0162     /*
0163      * NOTES: xx = late collision (data received before collision)
0164      *   late collisions cannot be detected by the receiver
0165      *   they would appear as JAM bits which would appear as
0166      *   bad FCS or carrier extend error which is
0167      *   CVMX_PIP_EXTEND_ERR
0168      */
0169 } cvmx_pip_rcv_err_t;
0170
0171 /**
0172  * This defines the err_code field errors in the work Q entry
0173  */
0174 typedef union {
0175     cvmx_pip_l4_err_t l4_err;
0176     cvmx_pip_ip_exc_t ip_exc;
0177     cvmx_pip_rcv_err_t rcv_err;
0178 } cvmx_pip_err_t;
0179
0180 /**
0181  * Status statistics for a port
0182  */
0183 typedef struct {
0184     /* Inbound octets marked to be dropped by the IPD */
0185     uint32_t dropped_octets;
0186     /* Inbound packets marked to be dropped by the IPD */
0187     uint32_t dropped_packets;
0188     /* RAW PCI Packets received by PIP per port */
0189     uint32_t pci_raw_packets;
0190     /* Number of octets processed by PIP */
0191     uint32_t octets;
0192     /* Number of packets processed by PIP */
0193     uint32_t packets;
0194     /*
0195      * Number of identified L2 multicast packets.   Does not
0196      * include broadcast packets.  Only includes packets whose
0197      * parse mode is SKIP_TO_L2
0198      */
0199     uint32_t multicast_packets;
0200     /*
0201      * Number of identified L2 broadcast packets.   Does not
0202      * include multicast packets.  Only includes packets whose
0203      * parse mode is SKIP_TO_L2
0204      */
0205     uint32_t broadcast_packets;
0206     /* Number of 64B packets */
0207     uint32_t len_64_packets;
0208     /* Number of 65-127B packets */
0209     uint32_t len_65_127_packets;
0210     /* Number of 128-255B packets */
0211     uint32_t len_128_255_packets;
0212     /* Number of 256-511B packets */
0213     uint32_t len_256_511_packets;
0214     /* Number of 512-1023B packets */
0215     uint32_t len_512_1023_packets;
0216     /* Number of 1024-1518B packets */
0217     uint32_t len_1024_1518_packets;
0218     /* Number of 1519-max packets */
0219     uint32_t len_1519_max_packets;
0220     /* Number of packets with FCS or Align opcode errors */
0221     uint32_t fcs_align_err_packets;
0222     /* Number of packets with length < min */
0223     uint32_t runt_packets;
0224     /* Number of packets with length < min and FCS error */
0225     uint32_t runt_crc_packets;
0226     /* Number of packets with length > max */
0227     uint32_t oversize_packets;
0228     /* Number of packets with length > max and FCS error */
0229     uint32_t oversize_crc_packets;
0230     /* Number of packets without GMX/SPX/PCI errors received by PIP */
0231     uint32_t inb_packets;
0232     /*
0233      * Total number of octets from all packets received by PIP,
0234      * including CRC
0235      */
0236     uint64_t inb_octets;
0237     /* Number of packets with GMX/SPX/PCI errors received by PIP */
0238     uint16_t inb_errors;
0239 } cvmx_pip_port_status_t;
0240
0241 /**
0242  * Definition of the PIP custom header that can be prepended
0243  * to a packet by external hardware.
0244  */
0245 typedef union {
0246     uint64_t u64;
0247     struct {
0248         /*
0249          * Documented as R - Set if the Packet is RAWFULL. If
0250          * set, this header must be the full 8 bytes.
0251          */
0252         uint64_t rawfull:1;
0253         /* Must be zero */
0254         uint64_t reserved0:5;
0255         /* PIP parse mode for this packet */
0256         uint64_t parse_mode:2;
0257         /* Must be zero */
0258         uint64_t reserved1:1;
0259         /*
0260          * Skip amount, including this header, to the
0261          * beginning of the packet
0262          */
0263         uint64_t skip_len:7;
0264         /* Must be zero */
0265         uint64_t reserved2:6;
0266         /* POW input queue for this packet */
0267         uint64_t qos:3;
0268         /* POW input group for this packet */
0269         uint64_t grp:4;
0270         /*
0271          * Flag to store this packet in the work queue entry,
0272          * if possible
0273          */
0274         uint64_t rs:1;
0275         /* POW input tag type */
0276         uint64_t tag_type:2;
0277         /* POW input tag */
0278         uint64_t tag:32;
0279     } s;
0280 } cvmx_pip_pkt_inst_hdr_t;
0281
0282 /* CSR typedefs have been moved to cvmx-csr-*.h */
0283
0284 /**
0285  * Configure an ethernet input port
0286  *
0287  * @port_num: Port number to configure
0288  * @port_cfg: Port hardware configuration
0289  * @port_tag_cfg:
0290  *         Port POW tagging configuration
0291  */
0292 static inline void cvmx_pip_config_port(uint64_t port_num,
0293                     union cvmx_pip_prt_cfgx port_cfg,
0294                     union cvmx_pip_prt_tagx port_tag_cfg)
0295 {
0296     cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
0297     cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
0298 }
0299 #if 0
0300 /**
0301  * @deprecated      This function is a thin wrapper around the Pass1 version
0302  *          of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
0303  *          setting the group that is incompatible with this function,
0304  *          the preferred upgrade path is to use the CSR directly.
0305  *
0306  * Configure the global QoS packet watchers. Each watcher is
0307  * capable of matching a field in a packet to determine the
0308  * QoS queue for scheduling.
0309  *
0310  * @watcher:    Watcher number to configure (0 - 3).
0311  * @match_type: Watcher match type
0312  * @match_value:
0313  *           Value the watcher will match against
0314  * @qos:    QoS queue for packets matching this watcher
0315  */
0316 static inline void cvmx_pip_config_watcher(uint64_t watcher,
0317                        cvmx_pip_qos_watch_types match_type,
0318                        uint64_t match_value, uint64_t qos)
0319 {
0320     cvmx_pip_port_watcher_cfg_t watcher_config;
0321
0322     watcher_config.u64 = 0;
0323     watcher_config.s.match_type = match_type;
0324     watcher_config.s.match_value = match_value;
0325     watcher_config.s.qos = qos;
0326
0327     cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
0328 }
0329 #endif
0330 /**
0331  * Configure the VLAN priority to QoS queue mapping.
0332  *
0333  * @vlan_priority:
0334  *       VLAN priority (0-7)
0335  * @qos:    QoS queue for packets matching this watcher
0336  */
0337 static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
0338                         uint64_t qos)
0339 {
0340     union cvmx_pip_qos_vlanx pip_qos_vlanx;
0341     pip_qos_vlanx.u64 = 0;
0342     pip_qos_vlanx.s.qos = qos;
0343     cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
0344 }
0345
0346 /**
0347  * Configure the Diffserv to QoS queue mapping.
0348  *
0349  * @diffserv: Diffserv field value (0-63)
0350  * @qos:      QoS queue for packets matching this watcher
0351  */
0352 static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
0353 {
0354     union cvmx_pip_qos_diffx pip_qos_diffx;
0355     pip_qos_diffx.u64 = 0;
0356     pip_qos_diffx.s.qos = qos;
0357     cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
0358 }
0359
0360 /**
0361  * Get the status counters for a port.
0362  *
0363  * @port_num: Port number to get statistics for.
0364  * @clear:    Set to 1 to clear the counters after they are read
0365  * @status:   Where to put the results.
0366  */
0367 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
0368                         cvmx_pip_port_status_t *status)
0369 {
0370     union cvmx_pip_stat_ctl pip_stat_ctl;
0371     union cvmx_pip_stat0_prtx stat0;
0372     union cvmx_pip_stat1_prtx stat1;
0373     union cvmx_pip_stat2_prtx stat2;
0374     union cvmx_pip_stat3_prtx stat3;
0375     union cvmx_pip_stat4_prtx stat4;
0376     union cvmx_pip_stat5_prtx stat5;
0377     union cvmx_pip_stat6_prtx stat6;
0378     union cvmx_pip_stat7_prtx stat7;
0379     union cvmx_pip_stat8_prtx stat8;
0380     union cvmx_pip_stat9_prtx stat9;
0381     union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
0382     union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
0383     union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
0384
0385     pip_stat_ctl.u64 = 0;
0386     pip_stat_ctl.s.rdclr = clear;
0387     cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
0388
0389     stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
0390     stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
0391     stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
0392     stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
0393     stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
0394     stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
0395     stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
0396     stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
0397     stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
0398     stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
0399     pip_stat_inb_pktsx.u64 =
0400         cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
0401     pip_stat_inb_octsx.u64 =
0402         cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
0403     pip_stat_inb_errsx.u64 =
0404         cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
0405
0406     status->dropped_octets = stat0.s.drp_octs;
0407     status->dropped_packets = stat0.s.drp_pkts;
0408     status->octets = stat1.s.octs;
0409     status->pci_raw_packets = stat2.s.raw;
0410     status->packets = stat2.s.pkts;
0411     status->multicast_packets = stat3.s.mcst;
0412     status->broadcast_packets = stat3.s.bcst;
0413     status->len_64_packets = stat4.s.h64;
0414     status->len_65_127_packets = stat4.s.h65to127;
0415     status->len_128_255_packets = stat5.s.h128to255;
0416     status->len_256_511_packets = stat5.s.h256to511;
0417     status->len_512_1023_packets = stat6.s.h512to1023;
0418     status->len_1024_1518_packets = stat6.s.h1024to1518;
0419     status->len_1519_max_packets = stat7.s.h1519;
0420     status->fcs_align_err_packets = stat7.s.fcs;
0421     status->runt_packets = stat8.s.undersz;
0422     status->runt_crc_packets = stat8.s.frag;
0423     status->oversize_packets = stat9.s.oversz;
0424     status->oversize_crc_packets = stat9.s.jabber;
0425     status->inb_packets = pip_stat_inb_pktsx.s.pkts;
0426     status->inb_octets = pip_stat_inb_octsx.s.octs;
0427     status->inb_errors = pip_stat_inb_errsx.s.errs;
0428
0429     if (cvmx_octeon_is_pass1()) {
0430         /*
0431          * Kludge to fix Octeon Pass 1 errata - Drop counts
0432          * don't work.
0433          */
0434         if (status->inb_packets > status->packets)
0435             status->dropped_packets =
0436                 status->inb_packets - status->packets;
0437         else
0438             status->dropped_packets = 0;
0439         if (status->inb_octets - status->inb_packets * 4 >
0440             status->octets)
0441             status->dropped_octets =
0442                 status->inb_octets - status->inb_packets * 4 -
0443                 status->octets;
0444         else
0445             status->dropped_octets = 0;
0446     }
0447 }
0448
0449 /**
0450  * Configure the hardware CRC engine
0451  *
0452  * @interface: Interface to configure (0 or 1)
0453  * @invert_result:
0454  *         Invert the result of the CRC
0455  * @reflect:  Reflect
0456  * @initialization_vector:
0457  *         CRC initialization vector
0458  */
0459 static inline void cvmx_pip_config_crc(uint64_t interface,
0460                        uint64_t invert_result, uint64_t reflect,
0461                        uint32_t initialization_vector)
0462 {
0463     if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
0464         union cvmx_pip_crc_ctlx config;
0465         union cvmx_pip_crc_ivx pip_crc_ivx;
0466
0467         config.u64 = 0;
0468         config.s.invres = invert_result;
0469         config.s.reflect = reflect;
0470         cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
0471
0472         pip_crc_ivx.u64 = 0;
0473         pip_crc_ivx.s.iv = initialization_vector;
0474         cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
0475     }
0476 }
0477
0478 /**
0479  * Clear all bits in a tag mask. This should be called on
0480  * startup before any calls to cvmx_pip_tag_mask_set. Each bit
0481  * set in the final mask represent a byte used in the packet for
0482  * tag generation.
0483  *
0484  * @mask_index: Which tag mask to clear (0..3)
0485  */
0486 static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
0487 {
0488     uint64_t index;
0489     union cvmx_pip_tag_incx pip_tag_incx;
0490     pip_tag_incx.u64 = 0;
0491     pip_tag_incx.s.en = 0;
0492     for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
0493         cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
0494 }
0495
0496 /**
0497  * Sets a range of bits in the tag mask. The tag mask is used
0498  * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
0499  * There are four separate masks that can be configured.
0500  *
0501  * @mask_index: Which tag mask to modify (0..3)
0502  * @offset: Offset into the bitmask to set bits at. Use the GCC macro
0503  *      offsetof() to determine the offsets into packet headers.
0504  *      For example, offsetof(ethhdr, protocol) returns the offset
0505  *      of the ethernet protocol field.  The bitmask selects which
0506  *      bytes to include the tag, with bit offset X selecting
0507  *      byte at offset X from the beginning of the packet data.
0508  * @len:    Number of bytes to include. Usually this is the sizeof()
0509  *      the field.
0510  */
0511 static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
0512                      uint64_t len)
0513 {
0514     while (len--) {
0515         union cvmx_pip_tag_incx pip_tag_incx;
0516         uint64_t index = mask_index * 16 + offset / 8;
0517         pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
0518         pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
0519         cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
0520         offset++;
0521     }
0522 }
0523
0524 #endif /*  __CVMX_PIP_H__ */