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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_PEMX_DEFS_H__
0029 #define __CVMX_PEMX_DEFS_H__
0030 
0031 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
0032 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
0033 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
0034 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
0035 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
0036 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
0037 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
0038 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
0039 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
0040 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
0041 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
0042 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
0043 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
0044 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
0045 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
0046 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
0047 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
0048 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
0049 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
0050 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
0051 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
0052 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
0053 
0054 union cvmx_pemx_bar1_indexx {
0055     uint64_t u64;
0056     struct cvmx_pemx_bar1_indexx_s {
0057 #ifdef __BIG_ENDIAN_BITFIELD
0058         uint64_t reserved_20_63:44;
0059         uint64_t addr_idx:16;
0060         uint64_t ca:1;
0061         uint64_t end_swp:2;
0062         uint64_t addr_v:1;
0063 #else
0064         uint64_t addr_v:1;
0065         uint64_t end_swp:2;
0066         uint64_t ca:1;
0067         uint64_t addr_idx:16;
0068         uint64_t reserved_20_63:44;
0069 #endif
0070     } s;
0071 };
0072 
0073 union cvmx_pemx_bar2_mask {
0074     uint64_t u64;
0075     struct cvmx_pemx_bar2_mask_s {
0076 #ifdef __BIG_ENDIAN_BITFIELD
0077         uint64_t reserved_38_63:26;
0078         uint64_t mask:35;
0079         uint64_t reserved_0_2:3;
0080 #else
0081         uint64_t reserved_0_2:3;
0082         uint64_t mask:35;
0083         uint64_t reserved_38_63:26;
0084 #endif
0085     } s;
0086 };
0087 
0088 union cvmx_pemx_bar_ctl {
0089     uint64_t u64;
0090     struct cvmx_pemx_bar_ctl_s {
0091 #ifdef __BIG_ENDIAN_BITFIELD
0092         uint64_t reserved_7_63:57;
0093         uint64_t bar1_siz:3;
0094         uint64_t bar2_enb:1;
0095         uint64_t bar2_esx:2;
0096         uint64_t bar2_cax:1;
0097 #else
0098         uint64_t bar2_cax:1;
0099         uint64_t bar2_esx:2;
0100         uint64_t bar2_enb:1;
0101         uint64_t bar1_siz:3;
0102         uint64_t reserved_7_63:57;
0103 #endif
0104     } s;
0105 };
0106 
0107 union cvmx_pemx_bist_status {
0108     uint64_t u64;
0109     struct cvmx_pemx_bist_status_s {
0110 #ifdef __BIG_ENDIAN_BITFIELD
0111         uint64_t reserved_8_63:56;
0112         uint64_t retry:1;
0113         uint64_t rqdata0:1;
0114         uint64_t rqdata1:1;
0115         uint64_t rqdata2:1;
0116         uint64_t rqdata3:1;
0117         uint64_t rqhdr1:1;
0118         uint64_t rqhdr0:1;
0119         uint64_t sot:1;
0120 #else
0121         uint64_t sot:1;
0122         uint64_t rqhdr0:1;
0123         uint64_t rqhdr1:1;
0124         uint64_t rqdata3:1;
0125         uint64_t rqdata2:1;
0126         uint64_t rqdata1:1;
0127         uint64_t rqdata0:1;
0128         uint64_t retry:1;
0129         uint64_t reserved_8_63:56;
0130 #endif
0131     } s;
0132 };
0133 
0134 union cvmx_pemx_bist_status2 {
0135     uint64_t u64;
0136     struct cvmx_pemx_bist_status2_s {
0137 #ifdef __BIG_ENDIAN_BITFIELD
0138         uint64_t reserved_10_63:54;
0139         uint64_t e2p_cpl:1;
0140         uint64_t e2p_n:1;
0141         uint64_t e2p_p:1;
0142         uint64_t peai_p2e:1;
0143         uint64_t pef_tpf1:1;
0144         uint64_t pef_tpf0:1;
0145         uint64_t pef_tnf:1;
0146         uint64_t pef_tcf1:1;
0147         uint64_t pef_tc0:1;
0148         uint64_t ppf:1;
0149 #else
0150         uint64_t ppf:1;
0151         uint64_t pef_tc0:1;
0152         uint64_t pef_tcf1:1;
0153         uint64_t pef_tnf:1;
0154         uint64_t pef_tpf0:1;
0155         uint64_t pef_tpf1:1;
0156         uint64_t peai_p2e:1;
0157         uint64_t e2p_p:1;
0158         uint64_t e2p_n:1;
0159         uint64_t e2p_cpl:1;
0160         uint64_t reserved_10_63:54;
0161 #endif
0162     } s;
0163 };
0164 
0165 union cvmx_pemx_cfg_rd {
0166     uint64_t u64;
0167     struct cvmx_pemx_cfg_rd_s {
0168 #ifdef __BIG_ENDIAN_BITFIELD
0169         uint64_t data:32;
0170         uint64_t addr:32;
0171 #else
0172         uint64_t addr:32;
0173         uint64_t data:32;
0174 #endif
0175     } s;
0176 };
0177 
0178 union cvmx_pemx_cfg_wr {
0179     uint64_t u64;
0180     struct cvmx_pemx_cfg_wr_s {
0181 #ifdef __BIG_ENDIAN_BITFIELD
0182         uint64_t data:32;
0183         uint64_t addr:32;
0184 #else
0185         uint64_t addr:32;
0186         uint64_t data:32;
0187 #endif
0188     } s;
0189 };
0190 
0191 union cvmx_pemx_cpl_lut_valid {
0192     uint64_t u64;
0193     struct cvmx_pemx_cpl_lut_valid_s {
0194 #ifdef __BIG_ENDIAN_BITFIELD
0195         uint64_t reserved_32_63:32;
0196         uint64_t tag:32;
0197 #else
0198         uint64_t tag:32;
0199         uint64_t reserved_32_63:32;
0200 #endif
0201     } s;
0202 };
0203 
0204 union cvmx_pemx_ctl_status {
0205     uint64_t u64;
0206     struct cvmx_pemx_ctl_status_s {
0207 #ifdef __BIG_ENDIAN_BITFIELD
0208         uint64_t reserved_48_63:16;
0209         uint64_t auto_sd:1;
0210         uint64_t dnum:5;
0211         uint64_t pbus:8;
0212         uint64_t reserved_32_33:2;
0213         uint64_t cfg_rtry:16;
0214         uint64_t reserved_12_15:4;
0215         uint64_t pm_xtoff:1;
0216         uint64_t pm_xpme:1;
0217         uint64_t ob_p_cmd:1;
0218         uint64_t reserved_7_8:2;
0219         uint64_t nf_ecrc:1;
0220         uint64_t dly_one:1;
0221         uint64_t lnk_enb:1;
0222         uint64_t ro_ctlp:1;
0223         uint64_t fast_lm:1;
0224         uint64_t inv_ecrc:1;
0225         uint64_t inv_lcrc:1;
0226 #else
0227         uint64_t inv_lcrc:1;
0228         uint64_t inv_ecrc:1;
0229         uint64_t fast_lm:1;
0230         uint64_t ro_ctlp:1;
0231         uint64_t lnk_enb:1;
0232         uint64_t dly_one:1;
0233         uint64_t nf_ecrc:1;
0234         uint64_t reserved_7_8:2;
0235         uint64_t ob_p_cmd:1;
0236         uint64_t pm_xpme:1;
0237         uint64_t pm_xtoff:1;
0238         uint64_t reserved_12_15:4;
0239         uint64_t cfg_rtry:16;
0240         uint64_t reserved_32_33:2;
0241         uint64_t pbus:8;
0242         uint64_t dnum:5;
0243         uint64_t auto_sd:1;
0244         uint64_t reserved_48_63:16;
0245 #endif
0246     } s;
0247 };
0248 
0249 union cvmx_pemx_dbg_info {
0250     uint64_t u64;
0251     struct cvmx_pemx_dbg_info_s {
0252 #ifdef __BIG_ENDIAN_BITFIELD
0253         uint64_t reserved_31_63:33;
0254         uint64_t ecrc_e:1;
0255         uint64_t rawwpp:1;
0256         uint64_t racpp:1;
0257         uint64_t ramtlp:1;
0258         uint64_t rarwdns:1;
0259         uint64_t caar:1;
0260         uint64_t racca:1;
0261         uint64_t racur:1;
0262         uint64_t rauc:1;
0263         uint64_t rqo:1;
0264         uint64_t fcuv:1;
0265         uint64_t rpe:1;
0266         uint64_t fcpvwt:1;
0267         uint64_t dpeoosd:1;
0268         uint64_t rtwdle:1;
0269         uint64_t rdwdle:1;
0270         uint64_t mre:1;
0271         uint64_t rte:1;
0272         uint64_t acto:1;
0273         uint64_t rvdm:1;
0274         uint64_t rumep:1;
0275         uint64_t rptamrc:1;
0276         uint64_t rpmerc:1;
0277         uint64_t rfemrc:1;
0278         uint64_t rnfemrc:1;
0279         uint64_t rcemrc:1;
0280         uint64_t rpoison:1;
0281         uint64_t recrce:1;
0282         uint64_t rtlplle:1;
0283         uint64_t rtlpmal:1;
0284         uint64_t spoison:1;
0285 #else
0286         uint64_t spoison:1;
0287         uint64_t rtlpmal:1;
0288         uint64_t rtlplle:1;
0289         uint64_t recrce:1;
0290         uint64_t rpoison:1;
0291         uint64_t rcemrc:1;
0292         uint64_t rnfemrc:1;
0293         uint64_t rfemrc:1;
0294         uint64_t rpmerc:1;
0295         uint64_t rptamrc:1;
0296         uint64_t rumep:1;
0297         uint64_t rvdm:1;
0298         uint64_t acto:1;
0299         uint64_t rte:1;
0300         uint64_t mre:1;
0301         uint64_t rdwdle:1;
0302         uint64_t rtwdle:1;
0303         uint64_t dpeoosd:1;
0304         uint64_t fcpvwt:1;
0305         uint64_t rpe:1;
0306         uint64_t fcuv:1;
0307         uint64_t rqo:1;
0308         uint64_t rauc:1;
0309         uint64_t racur:1;
0310         uint64_t racca:1;
0311         uint64_t caar:1;
0312         uint64_t rarwdns:1;
0313         uint64_t ramtlp:1;
0314         uint64_t racpp:1;
0315         uint64_t rawwpp:1;
0316         uint64_t ecrc_e:1;
0317         uint64_t reserved_31_63:33;
0318 #endif
0319     } s;
0320 };
0321 
0322 union cvmx_pemx_dbg_info_en {
0323     uint64_t u64;
0324     struct cvmx_pemx_dbg_info_en_s {
0325 #ifdef __BIG_ENDIAN_BITFIELD
0326         uint64_t reserved_31_63:33;
0327         uint64_t ecrc_e:1;
0328         uint64_t rawwpp:1;
0329         uint64_t racpp:1;
0330         uint64_t ramtlp:1;
0331         uint64_t rarwdns:1;
0332         uint64_t caar:1;
0333         uint64_t racca:1;
0334         uint64_t racur:1;
0335         uint64_t rauc:1;
0336         uint64_t rqo:1;
0337         uint64_t fcuv:1;
0338         uint64_t rpe:1;
0339         uint64_t fcpvwt:1;
0340         uint64_t dpeoosd:1;
0341         uint64_t rtwdle:1;
0342         uint64_t rdwdle:1;
0343         uint64_t mre:1;
0344         uint64_t rte:1;
0345         uint64_t acto:1;
0346         uint64_t rvdm:1;
0347         uint64_t rumep:1;
0348         uint64_t rptamrc:1;
0349         uint64_t rpmerc:1;
0350         uint64_t rfemrc:1;
0351         uint64_t rnfemrc:1;
0352         uint64_t rcemrc:1;
0353         uint64_t rpoison:1;
0354         uint64_t recrce:1;
0355         uint64_t rtlplle:1;
0356         uint64_t rtlpmal:1;
0357         uint64_t spoison:1;
0358 #else
0359         uint64_t spoison:1;
0360         uint64_t rtlpmal:1;
0361         uint64_t rtlplle:1;
0362         uint64_t recrce:1;
0363         uint64_t rpoison:1;
0364         uint64_t rcemrc:1;
0365         uint64_t rnfemrc:1;
0366         uint64_t rfemrc:1;
0367         uint64_t rpmerc:1;
0368         uint64_t rptamrc:1;
0369         uint64_t rumep:1;
0370         uint64_t rvdm:1;
0371         uint64_t acto:1;
0372         uint64_t rte:1;
0373         uint64_t mre:1;
0374         uint64_t rdwdle:1;
0375         uint64_t rtwdle:1;
0376         uint64_t dpeoosd:1;
0377         uint64_t fcpvwt:1;
0378         uint64_t rpe:1;
0379         uint64_t fcuv:1;
0380         uint64_t rqo:1;
0381         uint64_t rauc:1;
0382         uint64_t racur:1;
0383         uint64_t racca:1;
0384         uint64_t caar:1;
0385         uint64_t rarwdns:1;
0386         uint64_t ramtlp:1;
0387         uint64_t racpp:1;
0388         uint64_t rawwpp:1;
0389         uint64_t ecrc_e:1;
0390         uint64_t reserved_31_63:33;
0391 #endif
0392     } s;
0393 };
0394 
0395 union cvmx_pemx_diag_status {
0396     uint64_t u64;
0397     struct cvmx_pemx_diag_status_s {
0398 #ifdef __BIG_ENDIAN_BITFIELD
0399         uint64_t reserved_4_63:60;
0400         uint64_t pm_dst:1;
0401         uint64_t pm_stat:1;
0402         uint64_t pm_en:1;
0403         uint64_t aux_en:1;
0404 #else
0405         uint64_t aux_en:1;
0406         uint64_t pm_en:1;
0407         uint64_t pm_stat:1;
0408         uint64_t pm_dst:1;
0409         uint64_t reserved_4_63:60;
0410 #endif
0411     } s;
0412 };
0413 
0414 union cvmx_pemx_inb_read_credits {
0415     uint64_t u64;
0416     struct cvmx_pemx_inb_read_credits_s {
0417 #ifdef __BIG_ENDIAN_BITFIELD
0418         uint64_t reserved_6_63:58;
0419         uint64_t num:6;
0420 #else
0421         uint64_t num:6;
0422         uint64_t reserved_6_63:58;
0423 #endif
0424     } s;
0425 };
0426 
0427 union cvmx_pemx_int_enb {
0428     uint64_t u64;
0429     struct cvmx_pemx_int_enb_s {
0430 #ifdef __BIG_ENDIAN_BITFIELD
0431         uint64_t reserved_14_63:50;
0432         uint64_t crs_dr:1;
0433         uint64_t crs_er:1;
0434         uint64_t rdlk:1;
0435         uint64_t exc:1;
0436         uint64_t un_bx:1;
0437         uint64_t un_b2:1;
0438         uint64_t un_b1:1;
0439         uint64_t up_bx:1;
0440         uint64_t up_b2:1;
0441         uint64_t up_b1:1;
0442         uint64_t pmem:1;
0443         uint64_t pmei:1;
0444         uint64_t se:1;
0445         uint64_t aeri:1;
0446 #else
0447         uint64_t aeri:1;
0448         uint64_t se:1;
0449         uint64_t pmei:1;
0450         uint64_t pmem:1;
0451         uint64_t up_b1:1;
0452         uint64_t up_b2:1;
0453         uint64_t up_bx:1;
0454         uint64_t un_b1:1;
0455         uint64_t un_b2:1;
0456         uint64_t un_bx:1;
0457         uint64_t exc:1;
0458         uint64_t rdlk:1;
0459         uint64_t crs_er:1;
0460         uint64_t crs_dr:1;
0461         uint64_t reserved_14_63:50;
0462 #endif
0463     } s;
0464 };
0465 
0466 union cvmx_pemx_int_enb_int {
0467     uint64_t u64;
0468     struct cvmx_pemx_int_enb_int_s {
0469 #ifdef __BIG_ENDIAN_BITFIELD
0470         uint64_t reserved_14_63:50;
0471         uint64_t crs_dr:1;
0472         uint64_t crs_er:1;
0473         uint64_t rdlk:1;
0474         uint64_t exc:1;
0475         uint64_t un_bx:1;
0476         uint64_t un_b2:1;
0477         uint64_t un_b1:1;
0478         uint64_t up_bx:1;
0479         uint64_t up_b2:1;
0480         uint64_t up_b1:1;
0481         uint64_t pmem:1;
0482         uint64_t pmei:1;
0483         uint64_t se:1;
0484         uint64_t aeri:1;
0485 #else
0486         uint64_t aeri:1;
0487         uint64_t se:1;
0488         uint64_t pmei:1;
0489         uint64_t pmem:1;
0490         uint64_t up_b1:1;
0491         uint64_t up_b2:1;
0492         uint64_t up_bx:1;
0493         uint64_t un_b1:1;
0494         uint64_t un_b2:1;
0495         uint64_t un_bx:1;
0496         uint64_t exc:1;
0497         uint64_t rdlk:1;
0498         uint64_t crs_er:1;
0499         uint64_t crs_dr:1;
0500         uint64_t reserved_14_63:50;
0501 #endif
0502     } s;
0503 };
0504 
0505 union cvmx_pemx_int_sum {
0506     uint64_t u64;
0507     struct cvmx_pemx_int_sum_s {
0508 #ifdef __BIG_ENDIAN_BITFIELD
0509         uint64_t reserved_14_63:50;
0510         uint64_t crs_dr:1;
0511         uint64_t crs_er:1;
0512         uint64_t rdlk:1;
0513         uint64_t exc:1;
0514         uint64_t un_bx:1;
0515         uint64_t un_b2:1;
0516         uint64_t un_b1:1;
0517         uint64_t up_bx:1;
0518         uint64_t up_b2:1;
0519         uint64_t up_b1:1;
0520         uint64_t pmem:1;
0521         uint64_t pmei:1;
0522         uint64_t se:1;
0523         uint64_t aeri:1;
0524 #else
0525         uint64_t aeri:1;
0526         uint64_t se:1;
0527         uint64_t pmei:1;
0528         uint64_t pmem:1;
0529         uint64_t up_b1:1;
0530         uint64_t up_b2:1;
0531         uint64_t up_bx:1;
0532         uint64_t un_b1:1;
0533         uint64_t un_b2:1;
0534         uint64_t un_bx:1;
0535         uint64_t exc:1;
0536         uint64_t rdlk:1;
0537         uint64_t crs_er:1;
0538         uint64_t crs_dr:1;
0539         uint64_t reserved_14_63:50;
0540 #endif
0541     } s;
0542 };
0543 
0544 union cvmx_pemx_p2n_bar0_start {
0545     uint64_t u64;
0546     struct cvmx_pemx_p2n_bar0_start_s {
0547 #ifdef __BIG_ENDIAN_BITFIELD
0548         uint64_t addr:50;
0549         uint64_t reserved_0_13:14;
0550 #else
0551         uint64_t reserved_0_13:14;
0552         uint64_t addr:50;
0553 #endif
0554     } s;
0555 };
0556 
0557 union cvmx_pemx_p2n_bar1_start {
0558     uint64_t u64;
0559     struct cvmx_pemx_p2n_bar1_start_s {
0560 #ifdef __BIG_ENDIAN_BITFIELD
0561         uint64_t addr:38;
0562         uint64_t reserved_0_25:26;
0563 #else
0564         uint64_t reserved_0_25:26;
0565         uint64_t addr:38;
0566 #endif
0567     } s;
0568 };
0569 
0570 union cvmx_pemx_p2n_bar2_start {
0571     uint64_t u64;
0572     struct cvmx_pemx_p2n_bar2_start_s {
0573 #ifdef __BIG_ENDIAN_BITFIELD
0574         uint64_t addr:23;
0575         uint64_t reserved_0_40:41;
0576 #else
0577         uint64_t reserved_0_40:41;
0578         uint64_t addr:23;
0579 #endif
0580     } s;
0581 };
0582 
0583 union cvmx_pemx_p2p_barx_end {
0584     uint64_t u64;
0585     struct cvmx_pemx_p2p_barx_end_s {
0586 #ifdef __BIG_ENDIAN_BITFIELD
0587         uint64_t addr:52;
0588         uint64_t reserved_0_11:12;
0589 #else
0590         uint64_t reserved_0_11:12;
0591         uint64_t addr:52;
0592 #endif
0593     } s;
0594 };
0595 
0596 union cvmx_pemx_p2p_barx_start {
0597     uint64_t u64;
0598     struct cvmx_pemx_p2p_barx_start_s {
0599 #ifdef __BIG_ENDIAN_BITFIELD
0600         uint64_t addr:52;
0601         uint64_t reserved_0_11:12;
0602 #else
0603         uint64_t reserved_0_11:12;
0604         uint64_t addr:52;
0605 #endif
0606     } s;
0607 };
0608 
0609 union cvmx_pemx_tlp_credits {
0610     uint64_t u64;
0611     struct cvmx_pemx_tlp_credits_s {
0612 #ifdef __BIG_ENDIAN_BITFIELD
0613         uint64_t reserved_56_63:8;
0614         uint64_t peai_ppf:8;
0615         uint64_t pem_cpl:8;
0616         uint64_t pem_np:8;
0617         uint64_t pem_p:8;
0618         uint64_t sli_cpl:8;
0619         uint64_t sli_np:8;
0620         uint64_t sli_p:8;
0621 #else
0622         uint64_t sli_p:8;
0623         uint64_t sli_np:8;
0624         uint64_t sli_cpl:8;
0625         uint64_t pem_p:8;
0626         uint64_t pem_np:8;
0627         uint64_t pem_cpl:8;
0628         uint64_t peai_ppf:8;
0629         uint64_t reserved_56_63:8;
0630 #endif
0631     } s;
0632     struct cvmx_pemx_tlp_credits_cn61xx {
0633 #ifdef __BIG_ENDIAN_BITFIELD
0634         uint64_t reserved_56_63:8;
0635         uint64_t peai_ppf:8;
0636         uint64_t reserved_24_47:24;
0637         uint64_t sli_cpl:8;
0638         uint64_t sli_np:8;
0639         uint64_t sli_p:8;
0640 #else
0641         uint64_t sli_p:8;
0642         uint64_t sli_np:8;
0643         uint64_t sli_cpl:8;
0644         uint64_t reserved_24_47:24;
0645         uint64_t peai_ppf:8;
0646         uint64_t reserved_56_63:8;
0647 #endif
0648     } cn61xx;
0649 };
0650 
0651 #endif
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