asm/octeon/cvmx-pcsxx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_PCSXX_DEFS_H__
0029 #define __CVMX_PCSXX_DEFS_H__
0030
0031 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
0032 {
0033     switch (cvmx_get_octeon_family()) {
0034     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0035     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0036     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0037         return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
0038     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0039     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0040         return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
0041     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0042         return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
0043     }
0044     return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
0045 }
0046
0047 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
0048 {
0049     switch (cvmx_get_octeon_family()) {
0050     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0051     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0052     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0053         return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
0054     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0055     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0056         return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
0057     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0058         return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
0059     }
0060     return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
0061 }
0062
0063 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
0064 {
0065     switch (cvmx_get_octeon_family()) {
0066     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0067     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0068     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0069         return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
0070     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0071     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0072         return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
0073     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0074         return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
0075     }
0076     return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
0077 }
0078
0079 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
0080 {
0081     switch (cvmx_get_octeon_family()) {
0082     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0083     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0084     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0085         return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
0086     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0087     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0088         return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
0089     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0090         return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
0091     }
0092     return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
0093 }
0094
0095 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
0096 {
0097     switch (cvmx_get_octeon_family()) {
0098     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0099     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0100     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0101         return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
0102     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0103     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0104         return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
0105     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0106         return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
0107     }
0108     return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
0109 }
0110
0111 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
0112 {
0113     switch (cvmx_get_octeon_family()) {
0114     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0115     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0116     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0117         return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
0118     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0119     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0120         return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
0121     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0122         return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
0123     }
0124     return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
0125 }
0126
0127 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
0128 {
0129     switch (cvmx_get_octeon_family()) {
0130     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0131     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0132     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0133         return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
0134     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0135     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0136         return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
0137     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0138         return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
0139     }
0140     return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
0141 }
0142
0143 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
0144 {
0145     switch (cvmx_get_octeon_family()) {
0146     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0147     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0148     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0149         return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
0150     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0151     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0152         return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
0153     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0154         return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
0155     }
0156     return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
0157 }
0158
0159 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
0160 {
0161     switch (cvmx_get_octeon_family()) {
0162     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0163     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0164     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0165         return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
0166     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0167     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0168         return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
0169     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0170         return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
0171     }
0172     return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
0173 }
0174
0175 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
0176 {
0177     switch (cvmx_get_octeon_family()) {
0178     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0179     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0180     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0181         return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
0182     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0183     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0184         return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
0185     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0186         return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
0187     }
0188     return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
0189 }
0190
0191 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
0192 {
0193     switch (cvmx_get_octeon_family()) {
0194     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0195     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0196     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0197         return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
0198     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0199     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0200         return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
0201     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0202         return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
0203     }
0204     return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
0205 }
0206
0207 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
0208 {
0209     switch (cvmx_get_octeon_family()) {
0210     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0211     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0212     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0213         return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
0214     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0215     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0216         return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
0217     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0218         return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
0219     }
0220     return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
0221 }
0222
0223 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
0224 {
0225     switch (cvmx_get_octeon_family()) {
0226     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0227     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0228     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0229         return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
0230     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0231     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0232         return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
0233     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0234         return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
0235     }
0236     return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
0237 }
0238
0239 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
0240 {
0241     switch (cvmx_get_octeon_family()) {
0242     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0243     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0244     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0245         return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
0246     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0247     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0248         return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
0249     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0250         return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
0251     }
0252     return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
0253 }
0254
0255 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
0256 {
0257     switch (cvmx_get_octeon_family()) {
0258     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0259     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0260     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0261         return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
0262     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0263     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0264         return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
0265     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0266         return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
0267     }
0268     return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
0269 }
0270
0271 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
0272
0273 union cvmx_pcsxx_10gbx_status_reg {
0274     uint64_t u64;
0275     struct cvmx_pcsxx_10gbx_status_reg_s {
0276 #ifdef __BIG_ENDIAN_BITFIELD
0277         uint64_t reserved_13_63:51;
0278         uint64_t alignd:1;
0279         uint64_t pattst:1;
0280         uint64_t reserved_4_10:7;
0281         uint64_t l3sync:1;
0282         uint64_t l2sync:1;
0283         uint64_t l1sync:1;
0284         uint64_t l0sync:1;
0285 #else
0286         uint64_t l0sync:1;
0287         uint64_t l1sync:1;
0288         uint64_t l2sync:1;
0289         uint64_t l3sync:1;
0290         uint64_t reserved_4_10:7;
0291         uint64_t pattst:1;
0292         uint64_t alignd:1;
0293         uint64_t reserved_13_63:51;
0294 #endif
0295     } s;
0296 };
0297
0298 union cvmx_pcsxx_bist_status_reg {
0299     uint64_t u64;
0300     struct cvmx_pcsxx_bist_status_reg_s {
0301 #ifdef __BIG_ENDIAN_BITFIELD
0302         uint64_t reserved_1_63:63;
0303         uint64_t bist_status:1;
0304 #else
0305         uint64_t bist_status:1;
0306         uint64_t reserved_1_63:63;
0307 #endif
0308     } s;
0309 };
0310
0311 union cvmx_pcsxx_bit_lock_status_reg {
0312     uint64_t u64;
0313     struct cvmx_pcsxx_bit_lock_status_reg_s {
0314 #ifdef __BIG_ENDIAN_BITFIELD
0315         uint64_t reserved_4_63:60;
0316         uint64_t bitlck3:1;
0317         uint64_t bitlck2:1;
0318         uint64_t bitlck1:1;
0319         uint64_t bitlck0:1;
0320 #else
0321         uint64_t bitlck0:1;
0322         uint64_t bitlck1:1;
0323         uint64_t bitlck2:1;
0324         uint64_t bitlck3:1;
0325         uint64_t reserved_4_63:60;
0326 #endif
0327     } s;
0328 };
0329
0330 union cvmx_pcsxx_control1_reg {
0331     uint64_t u64;
0332     struct cvmx_pcsxx_control1_reg_s {
0333 #ifdef __BIG_ENDIAN_BITFIELD
0334         uint64_t reserved_16_63:48;
0335         uint64_t reset:1;
0336         uint64_t loopbck1:1;
0337         uint64_t spdsel1:1;
0338         uint64_t reserved_12_12:1;
0339         uint64_t lo_pwr:1;
0340         uint64_t reserved_7_10:4;
0341         uint64_t spdsel0:1;
0342         uint64_t spd:4;
0343         uint64_t reserved_0_1:2;
0344 #else
0345         uint64_t reserved_0_1:2;
0346         uint64_t spd:4;
0347         uint64_t spdsel0:1;
0348         uint64_t reserved_7_10:4;
0349         uint64_t lo_pwr:1;
0350         uint64_t reserved_12_12:1;
0351         uint64_t spdsel1:1;
0352         uint64_t loopbck1:1;
0353         uint64_t reset:1;
0354         uint64_t reserved_16_63:48;
0355 #endif
0356     } s;
0357 };
0358
0359 union cvmx_pcsxx_control2_reg {
0360     uint64_t u64;
0361     struct cvmx_pcsxx_control2_reg_s {
0362 #ifdef __BIG_ENDIAN_BITFIELD
0363         uint64_t reserved_2_63:62;
0364         uint64_t type:2;
0365 #else
0366         uint64_t type:2;
0367         uint64_t reserved_2_63:62;
0368 #endif
0369     } s;
0370 };
0371
0372 union cvmx_pcsxx_int_en_reg {
0373     uint64_t u64;
0374     struct cvmx_pcsxx_int_en_reg_s {
0375 #ifdef __BIG_ENDIAN_BITFIELD
0376         uint64_t reserved_7_63:57;
0377         uint64_t dbg_sync_en:1;
0378         uint64_t algnlos_en:1;
0379         uint64_t synlos_en:1;
0380         uint64_t bitlckls_en:1;
0381         uint64_t rxsynbad_en:1;
0382         uint64_t rxbad_en:1;
0383         uint64_t txflt_en:1;
0384 #else
0385         uint64_t txflt_en:1;
0386         uint64_t rxbad_en:1;
0387         uint64_t rxsynbad_en:1;
0388         uint64_t bitlckls_en:1;
0389         uint64_t synlos_en:1;
0390         uint64_t algnlos_en:1;
0391         uint64_t dbg_sync_en:1;
0392         uint64_t reserved_7_63:57;
0393 #endif
0394     } s;
0395     struct cvmx_pcsxx_int_en_reg_cn52xx {
0396 #ifdef __BIG_ENDIAN_BITFIELD
0397         uint64_t reserved_6_63:58;
0398         uint64_t algnlos_en:1;
0399         uint64_t synlos_en:1;
0400         uint64_t bitlckls_en:1;
0401         uint64_t rxsynbad_en:1;
0402         uint64_t rxbad_en:1;
0403         uint64_t txflt_en:1;
0404 #else
0405         uint64_t txflt_en:1;
0406         uint64_t rxbad_en:1;
0407         uint64_t rxsynbad_en:1;
0408         uint64_t bitlckls_en:1;
0409         uint64_t synlos_en:1;
0410         uint64_t algnlos_en:1;
0411         uint64_t reserved_6_63:58;
0412 #endif
0413     } cn52xx;
0414 };
0415
0416 union cvmx_pcsxx_int_reg {
0417     uint64_t u64;
0418     struct cvmx_pcsxx_int_reg_s {
0419 #ifdef __BIG_ENDIAN_BITFIELD
0420         uint64_t reserved_7_63:57;
0421         uint64_t dbg_sync:1;
0422         uint64_t algnlos:1;
0423         uint64_t synlos:1;
0424         uint64_t bitlckls:1;
0425         uint64_t rxsynbad:1;
0426         uint64_t rxbad:1;
0427         uint64_t txflt:1;
0428 #else
0429         uint64_t txflt:1;
0430         uint64_t rxbad:1;
0431         uint64_t rxsynbad:1;
0432         uint64_t bitlckls:1;
0433         uint64_t synlos:1;
0434         uint64_t algnlos:1;
0435         uint64_t dbg_sync:1;
0436         uint64_t reserved_7_63:57;
0437 #endif
0438     } s;
0439     struct cvmx_pcsxx_int_reg_cn52xx {
0440 #ifdef __BIG_ENDIAN_BITFIELD
0441         uint64_t reserved_6_63:58;
0442         uint64_t algnlos:1;
0443         uint64_t synlos:1;
0444         uint64_t bitlckls:1;
0445         uint64_t rxsynbad:1;
0446         uint64_t rxbad:1;
0447         uint64_t txflt:1;
0448 #else
0449         uint64_t txflt:1;
0450         uint64_t rxbad:1;
0451         uint64_t rxsynbad:1;
0452         uint64_t bitlckls:1;
0453         uint64_t synlos:1;
0454         uint64_t algnlos:1;
0455         uint64_t reserved_6_63:58;
0456 #endif
0457     } cn52xx;
0458 };
0459
0460 union cvmx_pcsxx_log_anl_reg {
0461     uint64_t u64;
0462     struct cvmx_pcsxx_log_anl_reg_s {
0463 #ifdef __BIG_ENDIAN_BITFIELD
0464         uint64_t reserved_7_63:57;
0465         uint64_t enc_mode:1;
0466         uint64_t drop_ln:2;
0467         uint64_t lafifovfl:1;
0468         uint64_t la_en:1;
0469         uint64_t pkt_sz:2;
0470 #else
0471         uint64_t pkt_sz:2;
0472         uint64_t la_en:1;
0473         uint64_t lafifovfl:1;
0474         uint64_t drop_ln:2;
0475         uint64_t enc_mode:1;
0476         uint64_t reserved_7_63:57;
0477 #endif
0478     } s;
0479 };
0480
0481 union cvmx_pcsxx_misc_ctl_reg {
0482     uint64_t u64;
0483     struct cvmx_pcsxx_misc_ctl_reg_s {
0484 #ifdef __BIG_ENDIAN_BITFIELD
0485         uint64_t reserved_4_63:60;
0486         uint64_t tx_swap:1;
0487         uint64_t rx_swap:1;
0488         uint64_t xaui:1;
0489         uint64_t gmxeno:1;
0490 #else
0491         uint64_t gmxeno:1;
0492         uint64_t xaui:1;
0493         uint64_t rx_swap:1;
0494         uint64_t tx_swap:1;
0495         uint64_t reserved_4_63:60;
0496 #endif
0497     } s;
0498 };
0499
0500 union cvmx_pcsxx_rx_sync_states_reg {
0501     uint64_t u64;
0502     struct cvmx_pcsxx_rx_sync_states_reg_s {
0503 #ifdef __BIG_ENDIAN_BITFIELD
0504         uint64_t reserved_16_63:48;
0505         uint64_t sync3st:4;
0506         uint64_t sync2st:4;
0507         uint64_t sync1st:4;
0508         uint64_t sync0st:4;
0509 #else
0510         uint64_t sync0st:4;
0511         uint64_t sync1st:4;
0512         uint64_t sync2st:4;
0513         uint64_t sync3st:4;
0514         uint64_t reserved_16_63:48;
0515 #endif
0516     } s;
0517 };
0518
0519 union cvmx_pcsxx_spd_abil_reg {
0520     uint64_t u64;
0521     struct cvmx_pcsxx_spd_abil_reg_s {
0522 #ifdef __BIG_ENDIAN_BITFIELD
0523         uint64_t reserved_2_63:62;
0524         uint64_t tenpasst:1;
0525         uint64_t tengb:1;
0526 #else
0527         uint64_t tengb:1;
0528         uint64_t tenpasst:1;
0529         uint64_t reserved_2_63:62;
0530 #endif
0531     } s;
0532 };
0533
0534 union cvmx_pcsxx_status1_reg {
0535     uint64_t u64;
0536     struct cvmx_pcsxx_status1_reg_s {
0537 #ifdef __BIG_ENDIAN_BITFIELD
0538         uint64_t reserved_8_63:56;
0539         uint64_t flt:1;
0540         uint64_t reserved_3_6:4;
0541         uint64_t rcv_lnk:1;
0542         uint64_t lpable:1;
0543         uint64_t reserved_0_0:1;
0544 #else
0545         uint64_t reserved_0_0:1;
0546         uint64_t lpable:1;
0547         uint64_t rcv_lnk:1;
0548         uint64_t reserved_3_6:4;
0549         uint64_t flt:1;
0550         uint64_t reserved_8_63:56;
0551 #endif
0552     } s;
0553 };
0554
0555 union cvmx_pcsxx_status2_reg {
0556     uint64_t u64;
0557     struct cvmx_pcsxx_status2_reg_s {
0558 #ifdef __BIG_ENDIAN_BITFIELD
0559         uint64_t reserved_16_63:48;
0560         uint64_t dev:2;
0561         uint64_t reserved_12_13:2;
0562         uint64_t xmtflt:1;
0563         uint64_t rcvflt:1;
0564         uint64_t reserved_3_9:7;
0565         uint64_t tengb_w:1;
0566         uint64_t tengb_x:1;
0567         uint64_t tengb_r:1;
0568 #else
0569         uint64_t tengb_r:1;
0570         uint64_t tengb_x:1;
0571         uint64_t tengb_w:1;
0572         uint64_t reserved_3_9:7;
0573         uint64_t rcvflt:1;
0574         uint64_t xmtflt:1;
0575         uint64_t reserved_12_13:2;
0576         uint64_t dev:2;
0577         uint64_t reserved_16_63:48;
0578 #endif
0579     } s;
0580 };
0581
0582 union cvmx_pcsxx_tx_rx_polarity_reg {
0583     uint64_t u64;
0584     struct cvmx_pcsxx_tx_rx_polarity_reg_s {
0585 #ifdef __BIG_ENDIAN_BITFIELD
0586         uint64_t reserved_10_63:54;
0587         uint64_t xor_rxplrt:4;
0588         uint64_t xor_txplrt:4;
0589         uint64_t rxplrt:1;
0590         uint64_t txplrt:1;
0591 #else
0592         uint64_t txplrt:1;
0593         uint64_t rxplrt:1;
0594         uint64_t xor_txplrt:4;
0595         uint64_t xor_rxplrt:4;
0596         uint64_t reserved_10_63:54;
0597 #endif
0598     } s;
0599     struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
0600 #ifdef __BIG_ENDIAN_BITFIELD
0601         uint64_t reserved_2_63:62;
0602         uint64_t rxplrt:1;
0603         uint64_t txplrt:1;
0604 #else
0605         uint64_t txplrt:1;
0606         uint64_t rxplrt:1;
0607         uint64_t reserved_2_63:62;
0608 #endif
0609     } cn52xxp1;
0610 };
0611
0612 union cvmx_pcsxx_tx_rx_states_reg {
0613     uint64_t u64;
0614     struct cvmx_pcsxx_tx_rx_states_reg_s {
0615 #ifdef __BIG_ENDIAN_BITFIELD
0616         uint64_t reserved_14_63:50;
0617         uint64_t term_err:1;
0618         uint64_t syn3bad:1;
0619         uint64_t syn2bad:1;
0620         uint64_t syn1bad:1;
0621         uint64_t syn0bad:1;
0622         uint64_t rxbad:1;
0623         uint64_t algn_st:3;
0624         uint64_t rx_st:2;
0625         uint64_t tx_st:3;
0626 #else
0627         uint64_t tx_st:3;
0628         uint64_t rx_st:2;
0629         uint64_t algn_st:3;
0630         uint64_t rxbad:1;
0631         uint64_t syn0bad:1;
0632         uint64_t syn1bad:1;
0633         uint64_t syn2bad:1;
0634         uint64_t syn3bad:1;
0635         uint64_t term_err:1;
0636         uint64_t reserved_14_63:50;
0637 #endif
0638     } s;
0639     struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
0640 #ifdef __BIG_ENDIAN_BITFIELD
0641         uint64_t reserved_13_63:51;
0642         uint64_t syn3bad:1;
0643         uint64_t syn2bad:1;
0644         uint64_t syn1bad:1;
0645         uint64_t syn0bad:1;
0646         uint64_t rxbad:1;
0647         uint64_t algn_st:3;
0648         uint64_t rx_st:2;
0649         uint64_t tx_st:3;
0650 #else
0651         uint64_t tx_st:3;
0652         uint64_t rx_st:2;
0653         uint64_t algn_st:3;
0654         uint64_t rxbad:1;
0655         uint64_t syn0bad:1;
0656         uint64_t syn1bad:1;
0657         uint64_t syn2bad:1;
0658         uint64_t syn3bad:1;
0659         uint64_t reserved_13_63:51;
0660 #endif
0661     } cn52xxp1;
0662 };
0663
0664 #endif