asm/octeon/cvmx-pcsx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_PCSX_DEFS_H__
0029 #define __CVMX_PCSX_DEFS_H__
0030
0031 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
0032 {
0033     switch (cvmx_get_octeon_family()) {
0034     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0035         return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0036     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0037     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0038         return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0039     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0040     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0041     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0042         return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0043     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0044         return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0045     }
0046     return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0047 }
0048
0049 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
0050 {
0051     switch (cvmx_get_octeon_family()) {
0052     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0053         return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0054     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0055     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0056         return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0057     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0058     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0059     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0060         return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0061     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0062         return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0063     }
0064     return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0065 }
0066
0067 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
0068 {
0069     switch (cvmx_get_octeon_family()) {
0070     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0071         return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0072     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0073     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0074         return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0075     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0076     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0077     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0078         return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0079     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0080         return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0081     }
0082     return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0083 }
0084
0085 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
0086 {
0087     switch (cvmx_get_octeon_family()) {
0088     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0089         return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0090     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0091     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0092         return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0093     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0094     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0095     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0096         return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0097     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0098         return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0099     }
0100     return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0101 }
0102
0103 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
0104 {
0105     switch (cvmx_get_octeon_family()) {
0106     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0107         return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0108     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0109     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0110         return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0111     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0112     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0113     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0114         return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0115     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0116         return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0117     }
0118     return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0119 }
0120
0121 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
0122 {
0123     switch (cvmx_get_octeon_family()) {
0124     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0125         return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0126     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0127     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0128         return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0129     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0130     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0131     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0132         return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0133     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0134         return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0135     }
0136     return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0137 }
0138
0139 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
0140 {
0141     switch (cvmx_get_octeon_family()) {
0142     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0143         return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0144     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0145     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0146         return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0147     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0148     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0149     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0150         return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0151     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0152         return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0153     }
0154     return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0155 }
0156
0157 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
0158 {
0159     switch (cvmx_get_octeon_family()) {
0160     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0161         return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0162     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0163     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0164         return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0165     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0166     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0167     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0168         return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0169     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0170         return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0171     }
0172     return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0173 }
0174
0175 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
0176 {
0177     switch (cvmx_get_octeon_family()) {
0178     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0179         return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0180     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0181     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0182         return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0183     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0184     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0185     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0186         return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0187     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0188         return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0189     }
0190     return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0191 }
0192
0193 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
0194 {
0195     switch (cvmx_get_octeon_family()) {
0196     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0197         return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0198     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0199     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0200         return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0201     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0202     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0203     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0204         return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0205     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0206         return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0207     }
0208     return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0209 }
0210
0211 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
0212 {
0213     switch (cvmx_get_octeon_family()) {
0214     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0215         return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0216     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0217     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0218         return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0219     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0220     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0221     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0222         return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0223     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0224         return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0225     }
0226     return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0227 }
0228
0229 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
0230 {
0231     switch (cvmx_get_octeon_family()) {
0232     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0233         return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0234     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0235     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0236         return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0237     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0238     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0239     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0240         return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0241     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0242         return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0243     }
0244     return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0245 }
0246
0247 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
0248 {
0249     switch (cvmx_get_octeon_family()) {
0250     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0251         return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0252     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0253     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0254         return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0255     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0256     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0257     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0258         return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0259     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0260         return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0261     }
0262     return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0263 }
0264
0265 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
0266 {
0267     switch (cvmx_get_octeon_family()) {
0268     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0269         return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0270     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0271     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0272         return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0273     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0274     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0275     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0276         return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0277     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0278         return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0279     }
0280     return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0281 }
0282
0283 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
0284 {
0285     switch (cvmx_get_octeon_family()) {
0286     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0287         return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0288     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0289     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0290         return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0291     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0292     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0293     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0294         return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0295     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0296         return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0297     }
0298     return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0299 }
0300
0301 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
0302 {
0303     switch (cvmx_get_octeon_family()) {
0304     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0305         return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0306     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0307     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0308         return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0309     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0310     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0311     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0312         return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0313     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0314         return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0315     }
0316     return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0317 }
0318
0319 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
0320 {
0321     switch (cvmx_get_octeon_family()) {
0322     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0323         return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0324     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0325     case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
0326         return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0327     case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
0328     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0329     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0330         return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0331     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0332         return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
0333     }
0334     return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
0335 }
0336
0337 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
0338
0339 union cvmx_pcsx_anx_adv_reg {
0340     uint64_t u64;
0341     struct cvmx_pcsx_anx_adv_reg_s {
0342 #ifdef __BIG_ENDIAN_BITFIELD
0343         uint64_t reserved_16_63:48;
0344         uint64_t np:1;
0345         uint64_t reserved_14_14:1;
0346         uint64_t rem_flt:2;
0347         uint64_t reserved_9_11:3;
0348         uint64_t pause:2;
0349         uint64_t hfd:1;
0350         uint64_t fd:1;
0351         uint64_t reserved_0_4:5;
0352 #else
0353         uint64_t reserved_0_4:5;
0354         uint64_t fd:1;
0355         uint64_t hfd:1;
0356         uint64_t pause:2;
0357         uint64_t reserved_9_11:3;
0358         uint64_t rem_flt:2;
0359         uint64_t reserved_14_14:1;
0360         uint64_t np:1;
0361         uint64_t reserved_16_63:48;
0362 #endif
0363     } s;
0364 };
0365
0366 union cvmx_pcsx_anx_ext_st_reg {
0367     uint64_t u64;
0368     struct cvmx_pcsx_anx_ext_st_reg_s {
0369 #ifdef __BIG_ENDIAN_BITFIELD
0370         uint64_t reserved_16_63:48;
0371         uint64_t thou_xfd:1;
0372         uint64_t thou_xhd:1;
0373         uint64_t thou_tfd:1;
0374         uint64_t thou_thd:1;
0375         uint64_t reserved_0_11:12;
0376 #else
0377         uint64_t reserved_0_11:12;
0378         uint64_t thou_thd:1;
0379         uint64_t thou_tfd:1;
0380         uint64_t thou_xhd:1;
0381         uint64_t thou_xfd:1;
0382         uint64_t reserved_16_63:48;
0383 #endif
0384     } s;
0385 };
0386
0387 union cvmx_pcsx_anx_lp_abil_reg {
0388     uint64_t u64;
0389     struct cvmx_pcsx_anx_lp_abil_reg_s {
0390 #ifdef __BIG_ENDIAN_BITFIELD
0391         uint64_t reserved_16_63:48;
0392         uint64_t np:1;
0393         uint64_t ack:1;
0394         uint64_t rem_flt:2;
0395         uint64_t reserved_9_11:3;
0396         uint64_t pause:2;
0397         uint64_t hfd:1;
0398         uint64_t fd:1;
0399         uint64_t reserved_0_4:5;
0400 #else
0401         uint64_t reserved_0_4:5;
0402         uint64_t fd:1;
0403         uint64_t hfd:1;
0404         uint64_t pause:2;
0405         uint64_t reserved_9_11:3;
0406         uint64_t rem_flt:2;
0407         uint64_t ack:1;
0408         uint64_t np:1;
0409         uint64_t reserved_16_63:48;
0410 #endif
0411     } s;
0412 };
0413
0414 union cvmx_pcsx_anx_results_reg {
0415     uint64_t u64;
0416     struct cvmx_pcsx_anx_results_reg_s {
0417 #ifdef __BIG_ENDIAN_BITFIELD
0418         uint64_t reserved_7_63:57;
0419         uint64_t pause:2;
0420         uint64_t spd:2;
0421         uint64_t an_cpt:1;
0422         uint64_t dup:1;
0423         uint64_t link_ok:1;
0424 #else
0425         uint64_t link_ok:1;
0426         uint64_t dup:1;
0427         uint64_t an_cpt:1;
0428         uint64_t spd:2;
0429         uint64_t pause:2;
0430         uint64_t reserved_7_63:57;
0431 #endif
0432     } s;
0433 };
0434
0435 union cvmx_pcsx_intx_en_reg {
0436     uint64_t u64;
0437     struct cvmx_pcsx_intx_en_reg_s {
0438 #ifdef __BIG_ENDIAN_BITFIELD
0439         uint64_t reserved_13_63:51;
0440         uint64_t dbg_sync_en:1;
0441         uint64_t dup:1;
0442         uint64_t sync_bad_en:1;
0443         uint64_t an_bad_en:1;
0444         uint64_t rxlock_en:1;
0445         uint64_t rxbad_en:1;
0446         uint64_t rxerr_en:1;
0447         uint64_t txbad_en:1;
0448         uint64_t txfifo_en:1;
0449         uint64_t txfifu_en:1;
0450         uint64_t an_err_en:1;
0451         uint64_t xmit_en:1;
0452         uint64_t lnkspd_en:1;
0453 #else
0454         uint64_t lnkspd_en:1;
0455         uint64_t xmit_en:1;
0456         uint64_t an_err_en:1;
0457         uint64_t txfifu_en:1;
0458         uint64_t txfifo_en:1;
0459         uint64_t txbad_en:1;
0460         uint64_t rxerr_en:1;
0461         uint64_t rxbad_en:1;
0462         uint64_t rxlock_en:1;
0463         uint64_t an_bad_en:1;
0464         uint64_t sync_bad_en:1;
0465         uint64_t dup:1;
0466         uint64_t dbg_sync_en:1;
0467         uint64_t reserved_13_63:51;
0468 #endif
0469     } s;
0470     struct cvmx_pcsx_intx_en_reg_cn52xx {
0471 #ifdef __BIG_ENDIAN_BITFIELD
0472         uint64_t reserved_12_63:52;
0473         uint64_t dup:1;
0474         uint64_t sync_bad_en:1;
0475         uint64_t an_bad_en:1;
0476         uint64_t rxlock_en:1;
0477         uint64_t rxbad_en:1;
0478         uint64_t rxerr_en:1;
0479         uint64_t txbad_en:1;
0480         uint64_t txfifo_en:1;
0481         uint64_t txfifu_en:1;
0482         uint64_t an_err_en:1;
0483         uint64_t xmit_en:1;
0484         uint64_t lnkspd_en:1;
0485 #else
0486         uint64_t lnkspd_en:1;
0487         uint64_t xmit_en:1;
0488         uint64_t an_err_en:1;
0489         uint64_t txfifu_en:1;
0490         uint64_t txfifo_en:1;
0491         uint64_t txbad_en:1;
0492         uint64_t rxerr_en:1;
0493         uint64_t rxbad_en:1;
0494         uint64_t rxlock_en:1;
0495         uint64_t an_bad_en:1;
0496         uint64_t sync_bad_en:1;
0497         uint64_t dup:1;
0498         uint64_t reserved_12_63:52;
0499 #endif
0500     } cn52xx;
0501 };
0502
0503 union cvmx_pcsx_intx_reg {
0504     uint64_t u64;
0505     struct cvmx_pcsx_intx_reg_s {
0506 #ifdef __BIG_ENDIAN_BITFIELD
0507         uint64_t reserved_13_63:51;
0508         uint64_t dbg_sync:1;
0509         uint64_t dup:1;
0510         uint64_t sync_bad:1;
0511         uint64_t an_bad:1;
0512         uint64_t rxlock:1;
0513         uint64_t rxbad:1;
0514         uint64_t rxerr:1;
0515         uint64_t txbad:1;
0516         uint64_t txfifo:1;
0517         uint64_t txfifu:1;
0518         uint64_t an_err:1;
0519         uint64_t xmit:1;
0520         uint64_t lnkspd:1;
0521 #else
0522         uint64_t lnkspd:1;
0523         uint64_t xmit:1;
0524         uint64_t an_err:1;
0525         uint64_t txfifu:1;
0526         uint64_t txfifo:1;
0527         uint64_t txbad:1;
0528         uint64_t rxerr:1;
0529         uint64_t rxbad:1;
0530         uint64_t rxlock:1;
0531         uint64_t an_bad:1;
0532         uint64_t sync_bad:1;
0533         uint64_t dup:1;
0534         uint64_t dbg_sync:1;
0535         uint64_t reserved_13_63:51;
0536 #endif
0537     } s;
0538     struct cvmx_pcsx_intx_reg_cn52xx {
0539 #ifdef __BIG_ENDIAN_BITFIELD
0540         uint64_t reserved_12_63:52;
0541         uint64_t dup:1;
0542         uint64_t sync_bad:1;
0543         uint64_t an_bad:1;
0544         uint64_t rxlock:1;
0545         uint64_t rxbad:1;
0546         uint64_t rxerr:1;
0547         uint64_t txbad:1;
0548         uint64_t txfifo:1;
0549         uint64_t txfifu:1;
0550         uint64_t an_err:1;
0551         uint64_t xmit:1;
0552         uint64_t lnkspd:1;
0553 #else
0554         uint64_t lnkspd:1;
0555         uint64_t xmit:1;
0556         uint64_t an_err:1;
0557         uint64_t txfifu:1;
0558         uint64_t txfifo:1;
0559         uint64_t txbad:1;
0560         uint64_t rxerr:1;
0561         uint64_t rxbad:1;
0562         uint64_t rxlock:1;
0563         uint64_t an_bad:1;
0564         uint64_t sync_bad:1;
0565         uint64_t dup:1;
0566         uint64_t reserved_12_63:52;
0567 #endif
0568     } cn52xx;
0569 };
0570
0571 union cvmx_pcsx_linkx_timer_count_reg {
0572     uint64_t u64;
0573     struct cvmx_pcsx_linkx_timer_count_reg_s {
0574 #ifdef __BIG_ENDIAN_BITFIELD
0575         uint64_t reserved_16_63:48;
0576         uint64_t count:16;
0577 #else
0578         uint64_t count:16;
0579         uint64_t reserved_16_63:48;
0580 #endif
0581     } s;
0582 };
0583
0584 union cvmx_pcsx_log_anlx_reg {
0585     uint64_t u64;
0586     struct cvmx_pcsx_log_anlx_reg_s {
0587 #ifdef __BIG_ENDIAN_BITFIELD
0588         uint64_t reserved_4_63:60;
0589         uint64_t lafifovfl:1;
0590         uint64_t la_en:1;
0591         uint64_t pkt_sz:2;
0592 #else
0593         uint64_t pkt_sz:2;
0594         uint64_t la_en:1;
0595         uint64_t lafifovfl:1;
0596         uint64_t reserved_4_63:60;
0597 #endif
0598     } s;
0599 };
0600
0601 union cvmx_pcsx_miscx_ctl_reg {
0602     uint64_t u64;
0603     struct cvmx_pcsx_miscx_ctl_reg_s {
0604 #ifdef __BIG_ENDIAN_BITFIELD
0605         uint64_t reserved_13_63:51;
0606         uint64_t sgmii:1;
0607         uint64_t gmxeno:1;
0608         uint64_t loopbck2:1;
0609         uint64_t mac_phy:1;
0610         uint64_t mode:1;
0611         uint64_t an_ovrd:1;
0612         uint64_t samp_pt:7;
0613 #else
0614         uint64_t samp_pt:7;
0615         uint64_t an_ovrd:1;
0616         uint64_t mode:1;
0617         uint64_t mac_phy:1;
0618         uint64_t loopbck2:1;
0619         uint64_t gmxeno:1;
0620         uint64_t sgmii:1;
0621         uint64_t reserved_13_63:51;
0622 #endif
0623     } s;
0624 };
0625
0626 union cvmx_pcsx_mrx_control_reg {
0627     uint64_t u64;
0628     struct cvmx_pcsx_mrx_control_reg_s {
0629 #ifdef __BIG_ENDIAN_BITFIELD
0630         uint64_t reserved_16_63:48;
0631         uint64_t reset:1;
0632         uint64_t loopbck1:1;
0633         uint64_t spdlsb:1;
0634         uint64_t an_en:1;
0635         uint64_t pwr_dn:1;
0636         uint64_t reserved_10_10:1;
0637         uint64_t rst_an:1;
0638         uint64_t dup:1;
0639         uint64_t coltst:1;
0640         uint64_t spdmsb:1;
0641         uint64_t uni:1;
0642         uint64_t reserved_0_4:5;
0643 #else
0644         uint64_t reserved_0_4:5;
0645         uint64_t uni:1;
0646         uint64_t spdmsb:1;
0647         uint64_t coltst:1;
0648         uint64_t dup:1;
0649         uint64_t rst_an:1;
0650         uint64_t reserved_10_10:1;
0651         uint64_t pwr_dn:1;
0652         uint64_t an_en:1;
0653         uint64_t spdlsb:1;
0654         uint64_t loopbck1:1;
0655         uint64_t reset:1;
0656         uint64_t reserved_16_63:48;
0657 #endif
0658     } s;
0659 };
0660
0661 union cvmx_pcsx_mrx_status_reg {
0662     uint64_t u64;
0663     struct cvmx_pcsx_mrx_status_reg_s {
0664 #ifdef __BIG_ENDIAN_BITFIELD
0665         uint64_t reserved_16_63:48;
0666         uint64_t hun_t4:1;
0667         uint64_t hun_xfd:1;
0668         uint64_t hun_xhd:1;
0669         uint64_t ten_fd:1;
0670         uint64_t ten_hd:1;
0671         uint64_t hun_t2fd:1;
0672         uint64_t hun_t2hd:1;
0673         uint64_t ext_st:1;
0674         uint64_t reserved_7_7:1;
0675         uint64_t prb_sup:1;
0676         uint64_t an_cpt:1;
0677         uint64_t rm_flt:1;
0678         uint64_t an_abil:1;
0679         uint64_t lnk_st:1;
0680         uint64_t reserved_1_1:1;
0681         uint64_t extnd:1;
0682 #else
0683         uint64_t extnd:1;
0684         uint64_t reserved_1_1:1;
0685         uint64_t lnk_st:1;
0686         uint64_t an_abil:1;
0687         uint64_t rm_flt:1;
0688         uint64_t an_cpt:1;
0689         uint64_t prb_sup:1;
0690         uint64_t reserved_7_7:1;
0691         uint64_t ext_st:1;
0692         uint64_t hun_t2hd:1;
0693         uint64_t hun_t2fd:1;
0694         uint64_t ten_hd:1;
0695         uint64_t ten_fd:1;
0696         uint64_t hun_xhd:1;
0697         uint64_t hun_xfd:1;
0698         uint64_t hun_t4:1;
0699         uint64_t reserved_16_63:48;
0700 #endif
0701     } s;
0702 };
0703
0704 union cvmx_pcsx_rxx_states_reg {
0705     uint64_t u64;
0706     struct cvmx_pcsx_rxx_states_reg_s {
0707 #ifdef __BIG_ENDIAN_BITFIELD
0708         uint64_t reserved_16_63:48;
0709         uint64_t rx_bad:1;
0710         uint64_t rx_st:5;
0711         uint64_t sync_bad:1;
0712         uint64_t sync:4;
0713         uint64_t an_bad:1;
0714         uint64_t an_st:4;
0715 #else
0716         uint64_t an_st:4;
0717         uint64_t an_bad:1;
0718         uint64_t sync:4;
0719         uint64_t sync_bad:1;
0720         uint64_t rx_st:5;
0721         uint64_t rx_bad:1;
0722         uint64_t reserved_16_63:48;
0723 #endif
0724     } s;
0725 };
0726
0727 union cvmx_pcsx_rxx_sync_reg {
0728     uint64_t u64;
0729     struct cvmx_pcsx_rxx_sync_reg_s {
0730 #ifdef __BIG_ENDIAN_BITFIELD
0731         uint64_t reserved_2_63:62;
0732         uint64_t sync:1;
0733         uint64_t bit_lock:1;
0734 #else
0735         uint64_t bit_lock:1;
0736         uint64_t sync:1;
0737         uint64_t reserved_2_63:62;
0738 #endif
0739     } s;
0740 };
0741
0742 union cvmx_pcsx_sgmx_an_adv_reg {
0743     uint64_t u64;
0744     struct cvmx_pcsx_sgmx_an_adv_reg_s {
0745 #ifdef __BIG_ENDIAN_BITFIELD
0746         uint64_t reserved_16_63:48;
0747         uint64_t link:1;
0748         uint64_t ack:1;
0749         uint64_t reserved_13_13:1;
0750         uint64_t dup:1;
0751         uint64_t speed:2;
0752         uint64_t reserved_1_9:9;
0753         uint64_t one:1;
0754 #else
0755         uint64_t one:1;
0756         uint64_t reserved_1_9:9;
0757         uint64_t speed:2;
0758         uint64_t dup:1;
0759         uint64_t reserved_13_13:1;
0760         uint64_t ack:1;
0761         uint64_t link:1;
0762         uint64_t reserved_16_63:48;
0763 #endif
0764     } s;
0765 };
0766
0767 union cvmx_pcsx_sgmx_lp_adv_reg {
0768     uint64_t u64;
0769     struct cvmx_pcsx_sgmx_lp_adv_reg_s {
0770 #ifdef __BIG_ENDIAN_BITFIELD
0771         uint64_t reserved_16_63:48;
0772         uint64_t link:1;
0773         uint64_t reserved_13_14:2;
0774         uint64_t dup:1;
0775         uint64_t speed:2;
0776         uint64_t reserved_1_9:9;
0777         uint64_t one:1;
0778 #else
0779         uint64_t one:1;
0780         uint64_t reserved_1_9:9;
0781         uint64_t speed:2;
0782         uint64_t dup:1;
0783         uint64_t reserved_13_14:2;
0784         uint64_t link:1;
0785         uint64_t reserved_16_63:48;
0786 #endif
0787     } s;
0788 };
0789
0790 union cvmx_pcsx_txx_states_reg {
0791     uint64_t u64;
0792     struct cvmx_pcsx_txx_states_reg_s {
0793 #ifdef __BIG_ENDIAN_BITFIELD
0794         uint64_t reserved_7_63:57;
0795         uint64_t xmit:2;
0796         uint64_t tx_bad:1;
0797         uint64_t ord_st:4;
0798 #else
0799         uint64_t ord_st:4;
0800         uint64_t tx_bad:1;
0801         uint64_t xmit:2;
0802         uint64_t reserved_7_63:57;
0803 #endif
0804     } s;
0805 };
0806
0807 union cvmx_pcsx_tx_rxx_polarity_reg {
0808     uint64_t u64;
0809     struct cvmx_pcsx_tx_rxx_polarity_reg_s {
0810 #ifdef __BIG_ENDIAN_BITFIELD
0811         uint64_t reserved_4_63:60;
0812         uint64_t rxovrd:1;
0813         uint64_t autorxpl:1;
0814         uint64_t rxplrt:1;
0815         uint64_t txplrt:1;
0816 #else
0817         uint64_t txplrt:1;
0818         uint64_t rxplrt:1;
0819         uint64_t autorxpl:1;
0820         uint64_t rxovrd:1;
0821         uint64_t reserved_4_63:60;
0822 #endif
0823     } s;
0824 };
0825
0826 #endif