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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_PCI_DEFS_H__
0029 #define __CVMX_PCI_DEFS_H__
0030 
0031 #define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
0032 #define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
0033 #define CVMX_PCI_CFG00 (0x0000000000000000ull)
0034 #define CVMX_PCI_CFG01 (0x0000000000000004ull)
0035 #define CVMX_PCI_CFG02 (0x0000000000000008ull)
0036 #define CVMX_PCI_CFG03 (0x000000000000000Cull)
0037 #define CVMX_PCI_CFG04 (0x0000000000000010ull)
0038 #define CVMX_PCI_CFG05 (0x0000000000000014ull)
0039 #define CVMX_PCI_CFG06 (0x0000000000000018ull)
0040 #define CVMX_PCI_CFG07 (0x000000000000001Cull)
0041 #define CVMX_PCI_CFG08 (0x0000000000000020ull)
0042 #define CVMX_PCI_CFG09 (0x0000000000000024ull)
0043 #define CVMX_PCI_CFG10 (0x0000000000000028ull)
0044 #define CVMX_PCI_CFG11 (0x000000000000002Cull)
0045 #define CVMX_PCI_CFG12 (0x0000000000000030ull)
0046 #define CVMX_PCI_CFG13 (0x0000000000000034ull)
0047 #define CVMX_PCI_CFG15 (0x000000000000003Cull)
0048 #define CVMX_PCI_CFG16 (0x0000000000000040ull)
0049 #define CVMX_PCI_CFG17 (0x0000000000000044ull)
0050 #define CVMX_PCI_CFG18 (0x0000000000000048ull)
0051 #define CVMX_PCI_CFG19 (0x000000000000004Cull)
0052 #define CVMX_PCI_CFG20 (0x0000000000000050ull)
0053 #define CVMX_PCI_CFG21 (0x0000000000000054ull)
0054 #define CVMX_PCI_CFG22 (0x0000000000000058ull)
0055 #define CVMX_PCI_CFG56 (0x00000000000000E0ull)
0056 #define CVMX_PCI_CFG57 (0x00000000000000E4ull)
0057 #define CVMX_PCI_CFG58 (0x00000000000000E8ull)
0058 #define CVMX_PCI_CFG59 (0x00000000000000ECull)
0059 #define CVMX_PCI_CFG60 (0x00000000000000F0ull)
0060 #define CVMX_PCI_CFG61 (0x00000000000000F4ull)
0061 #define CVMX_PCI_CFG62 (0x00000000000000F8ull)
0062 #define CVMX_PCI_CFG63 (0x00000000000000FCull)
0063 #define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
0064 #define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
0065 #define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
0066 #define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
0067 #define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
0068 #define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
0069 #define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
0070 #define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
0071 #define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
0072 #define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
0073 #define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
0074 #define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
0075 #define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
0076 #define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
0077 #define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
0078 #define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
0079 #define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
0080 #define CVMX_PCI_INT_ENB (0x0000000000000038ull)
0081 #define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
0082 #define CVMX_PCI_INT_SUM (0x0000000000000030ull)
0083 #define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
0084 #define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
0085 #define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
0086 #define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
0087 #define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
0088 #define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
0089 #define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
0090 #define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
0091 #define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
0092 #define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
0093 #define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
0094 #define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
0095 #define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
0096 #define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
0097 #define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
0098 #define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
0099 #define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
0100 #define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
0101 #define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
0102 #define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
0103 #define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
0104 #define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
0105 #define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
0106 #define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
0107 #define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
0108 #define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
0109 #define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
0110 #define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
0111 #define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
0112 #define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
0113 #define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
0114 #define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
0115 #define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
0116 
0117 union cvmx_pci_bar1_indexx {
0118     uint32_t u32;
0119     struct cvmx_pci_bar1_indexx_s {
0120 #ifdef __BIG_ENDIAN_BITFIELD
0121         uint32_t reserved_18_31:14;
0122         uint32_t addr_idx:14;
0123         uint32_t ca:1;
0124         uint32_t end_swp:2;
0125         uint32_t addr_v:1;
0126 #else
0127         uint32_t addr_v:1;
0128         uint32_t end_swp:2;
0129         uint32_t ca:1;
0130         uint32_t addr_idx:14;
0131         uint32_t reserved_18_31:14;
0132 #endif
0133     } s;
0134 };
0135 
0136 union cvmx_pci_bist_reg {
0137     uint64_t u64;
0138     struct cvmx_pci_bist_reg_s {
0139 #ifdef __BIG_ENDIAN_BITFIELD
0140         uint64_t reserved_10_63:54;
0141         uint64_t rsp_bs:1;
0142         uint64_t dma0_bs:1;
0143         uint64_t cmd0_bs:1;
0144         uint64_t cmd_bs:1;
0145         uint64_t csr2p_bs:1;
0146         uint64_t csrr_bs:1;
0147         uint64_t rsp2p_bs:1;
0148         uint64_t csr2n_bs:1;
0149         uint64_t dat2n_bs:1;
0150         uint64_t dbg2n_bs:1;
0151 #else
0152         uint64_t dbg2n_bs:1;
0153         uint64_t dat2n_bs:1;
0154         uint64_t csr2n_bs:1;
0155         uint64_t rsp2p_bs:1;
0156         uint64_t csrr_bs:1;
0157         uint64_t csr2p_bs:1;
0158         uint64_t cmd_bs:1;
0159         uint64_t cmd0_bs:1;
0160         uint64_t dma0_bs:1;
0161         uint64_t rsp_bs:1;
0162         uint64_t reserved_10_63:54;
0163 #endif
0164     } s;
0165 };
0166 
0167 union cvmx_pci_cfg00 {
0168     uint32_t u32;
0169     struct cvmx_pci_cfg00_s {
0170 #ifdef __BIG_ENDIAN_BITFIELD
0171         uint32_t devid:16;
0172         uint32_t vendid:16;
0173 #else
0174         uint32_t vendid:16;
0175         uint32_t devid:16;
0176 #endif
0177     } s;
0178 };
0179 
0180 union cvmx_pci_cfg01 {
0181     uint32_t u32;
0182     struct cvmx_pci_cfg01_s {
0183 #ifdef __BIG_ENDIAN_BITFIELD
0184         uint32_t dpe:1;
0185         uint32_t sse:1;
0186         uint32_t rma:1;
0187         uint32_t rta:1;
0188         uint32_t sta:1;
0189         uint32_t devt:2;
0190         uint32_t mdpe:1;
0191         uint32_t fbb:1;
0192         uint32_t reserved_22_22:1;
0193         uint32_t m66:1;
0194         uint32_t cle:1;
0195         uint32_t i_stat:1;
0196         uint32_t reserved_11_18:8;
0197         uint32_t i_dis:1;
0198         uint32_t fbbe:1;
0199         uint32_t see:1;
0200         uint32_t ads:1;
0201         uint32_t pee:1;
0202         uint32_t vps:1;
0203         uint32_t mwice:1;
0204         uint32_t scse:1;
0205         uint32_t me:1;
0206         uint32_t msae:1;
0207         uint32_t isae:1;
0208 #else
0209         uint32_t isae:1;
0210         uint32_t msae:1;
0211         uint32_t me:1;
0212         uint32_t scse:1;
0213         uint32_t mwice:1;
0214         uint32_t vps:1;
0215         uint32_t pee:1;
0216         uint32_t ads:1;
0217         uint32_t see:1;
0218         uint32_t fbbe:1;
0219         uint32_t i_dis:1;
0220         uint32_t reserved_11_18:8;
0221         uint32_t i_stat:1;
0222         uint32_t cle:1;
0223         uint32_t m66:1;
0224         uint32_t reserved_22_22:1;
0225         uint32_t fbb:1;
0226         uint32_t mdpe:1;
0227         uint32_t devt:2;
0228         uint32_t sta:1;
0229         uint32_t rta:1;
0230         uint32_t rma:1;
0231         uint32_t sse:1;
0232         uint32_t dpe:1;
0233 #endif
0234     } s;
0235 };
0236 
0237 union cvmx_pci_cfg02 {
0238     uint32_t u32;
0239     struct cvmx_pci_cfg02_s {
0240 #ifdef __BIG_ENDIAN_BITFIELD
0241         uint32_t cc:24;
0242         uint32_t rid:8;
0243 #else
0244         uint32_t rid:8;
0245         uint32_t cc:24;
0246 #endif
0247     } s;
0248 };
0249 
0250 union cvmx_pci_cfg03 {
0251     uint32_t u32;
0252     struct cvmx_pci_cfg03_s {
0253 #ifdef __BIG_ENDIAN_BITFIELD
0254         uint32_t bcap:1;
0255         uint32_t brb:1;
0256         uint32_t reserved_28_29:2;
0257         uint32_t bcod:4;
0258         uint32_t ht:8;
0259         uint32_t lt:8;
0260         uint32_t cls:8;
0261 #else
0262         uint32_t cls:8;
0263         uint32_t lt:8;
0264         uint32_t ht:8;
0265         uint32_t bcod:4;
0266         uint32_t reserved_28_29:2;
0267         uint32_t brb:1;
0268         uint32_t bcap:1;
0269 #endif
0270     } s;
0271 };
0272 
0273 union cvmx_pci_cfg04 {
0274     uint32_t u32;
0275     struct cvmx_pci_cfg04_s {
0276 #ifdef __BIG_ENDIAN_BITFIELD
0277         uint32_t lbase:20;
0278         uint32_t lbasez:8;
0279         uint32_t pf:1;
0280         uint32_t typ:2;
0281         uint32_t mspc:1;
0282 #else
0283         uint32_t mspc:1;
0284         uint32_t typ:2;
0285         uint32_t pf:1;
0286         uint32_t lbasez:8;
0287         uint32_t lbase:20;
0288 #endif
0289     } s;
0290 };
0291 
0292 union cvmx_pci_cfg05 {
0293     uint32_t u32;
0294     struct cvmx_pci_cfg05_s {
0295 #ifdef __BIG_ENDIAN_BITFIELD
0296         uint32_t hbase:32;
0297 #else
0298         uint32_t hbase:32;
0299 #endif
0300     } s;
0301 };
0302 
0303 union cvmx_pci_cfg06 {
0304     uint32_t u32;
0305     struct cvmx_pci_cfg06_s {
0306 #ifdef __BIG_ENDIAN_BITFIELD
0307         uint32_t lbase:5;
0308         uint32_t lbasez:23;
0309         uint32_t pf:1;
0310         uint32_t typ:2;
0311         uint32_t mspc:1;
0312 #else
0313         uint32_t mspc:1;
0314         uint32_t typ:2;
0315         uint32_t pf:1;
0316         uint32_t lbasez:23;
0317         uint32_t lbase:5;
0318 #endif
0319     } s;
0320 };
0321 
0322 union cvmx_pci_cfg07 {
0323     uint32_t u32;
0324     struct cvmx_pci_cfg07_s {
0325 #ifdef __BIG_ENDIAN_BITFIELD
0326         uint32_t hbase:32;
0327 #else
0328         uint32_t hbase:32;
0329 #endif
0330     } s;
0331 };
0332 
0333 union cvmx_pci_cfg08 {
0334     uint32_t u32;
0335     struct cvmx_pci_cfg08_s {
0336 #ifdef __BIG_ENDIAN_BITFIELD
0337         uint32_t lbasez:28;
0338         uint32_t pf:1;
0339         uint32_t typ:2;
0340         uint32_t mspc:1;
0341 #else
0342         uint32_t mspc:1;
0343         uint32_t typ:2;
0344         uint32_t pf:1;
0345         uint32_t lbasez:28;
0346 #endif
0347     } s;
0348 };
0349 
0350 union cvmx_pci_cfg09 {
0351     uint32_t u32;
0352     struct cvmx_pci_cfg09_s {
0353 #ifdef __BIG_ENDIAN_BITFIELD
0354         uint32_t hbase:25;
0355         uint32_t hbasez:7;
0356 #else
0357         uint32_t hbasez:7;
0358         uint32_t hbase:25;
0359 #endif
0360     } s;
0361 };
0362 
0363 union cvmx_pci_cfg10 {
0364     uint32_t u32;
0365     struct cvmx_pci_cfg10_s {
0366 #ifdef __BIG_ENDIAN_BITFIELD
0367         uint32_t cisp:32;
0368 #else
0369         uint32_t cisp:32;
0370 #endif
0371     } s;
0372 };
0373 
0374 union cvmx_pci_cfg11 {
0375     uint32_t u32;
0376     struct cvmx_pci_cfg11_s {
0377 #ifdef __BIG_ENDIAN_BITFIELD
0378         uint32_t ssid:16;
0379         uint32_t ssvid:16;
0380 #else
0381         uint32_t ssvid:16;
0382         uint32_t ssid:16;
0383 #endif
0384     } s;
0385 };
0386 
0387 union cvmx_pci_cfg12 {
0388     uint32_t u32;
0389     struct cvmx_pci_cfg12_s {
0390 #ifdef __BIG_ENDIAN_BITFIELD
0391         uint32_t erbar:16;
0392         uint32_t erbarz:5;
0393         uint32_t reserved_1_10:10;
0394         uint32_t erbar_en:1;
0395 #else
0396         uint32_t erbar_en:1;
0397         uint32_t reserved_1_10:10;
0398         uint32_t erbarz:5;
0399         uint32_t erbar:16;
0400 #endif
0401     } s;
0402 };
0403 
0404 union cvmx_pci_cfg13 {
0405     uint32_t u32;
0406     struct cvmx_pci_cfg13_s {
0407 #ifdef __BIG_ENDIAN_BITFIELD
0408         uint32_t reserved_8_31:24;
0409         uint32_t cp:8;
0410 #else
0411         uint32_t cp:8;
0412         uint32_t reserved_8_31:24;
0413 #endif
0414     } s;
0415 };
0416 
0417 union cvmx_pci_cfg15 {
0418     uint32_t u32;
0419     struct cvmx_pci_cfg15_s {
0420 #ifdef __BIG_ENDIAN_BITFIELD
0421         uint32_t ml:8;
0422         uint32_t mg:8;
0423         uint32_t inta:8;
0424         uint32_t il:8;
0425 #else
0426         uint32_t il:8;
0427         uint32_t inta:8;
0428         uint32_t mg:8;
0429         uint32_t ml:8;
0430 #endif
0431     } s;
0432 };
0433 
0434 union cvmx_pci_cfg16 {
0435     uint32_t u32;
0436     struct cvmx_pci_cfg16_s {
0437 #ifdef __BIG_ENDIAN_BITFIELD
0438         uint32_t trdnpr:1;
0439         uint32_t trdard:1;
0440         uint32_t rdsati:1;
0441         uint32_t trdrs:1;
0442         uint32_t trtae:1;
0443         uint32_t twsei:1;
0444         uint32_t twsen:1;
0445         uint32_t twtae:1;
0446         uint32_t tmae:1;
0447         uint32_t tslte:3;
0448         uint32_t tilt:4;
0449         uint32_t pbe:12;
0450         uint32_t dppmr:1;
0451         uint32_t reserved_2_2:1;
0452         uint32_t tswc:1;
0453         uint32_t mltd:1;
0454 #else
0455         uint32_t mltd:1;
0456         uint32_t tswc:1;
0457         uint32_t reserved_2_2:1;
0458         uint32_t dppmr:1;
0459         uint32_t pbe:12;
0460         uint32_t tilt:4;
0461         uint32_t tslte:3;
0462         uint32_t tmae:1;
0463         uint32_t twtae:1;
0464         uint32_t twsen:1;
0465         uint32_t twsei:1;
0466         uint32_t trtae:1;
0467         uint32_t trdrs:1;
0468         uint32_t rdsati:1;
0469         uint32_t trdard:1;
0470         uint32_t trdnpr:1;
0471 #endif
0472     } s;
0473 };
0474 
0475 union cvmx_pci_cfg17 {
0476     uint32_t u32;
0477     struct cvmx_pci_cfg17_s {
0478 #ifdef __BIG_ENDIAN_BITFIELD
0479         uint32_t tscme:32;
0480 #else
0481         uint32_t tscme:32;
0482 #endif
0483     } s;
0484 };
0485 
0486 union cvmx_pci_cfg18 {
0487     uint32_t u32;
0488     struct cvmx_pci_cfg18_s {
0489 #ifdef __BIG_ENDIAN_BITFIELD
0490         uint32_t tdsrps:32;
0491 #else
0492         uint32_t tdsrps:32;
0493 #endif
0494     } s;
0495 };
0496 
0497 union cvmx_pci_cfg19 {
0498     uint32_t u32;
0499     struct cvmx_pci_cfg19_s {
0500 #ifdef __BIG_ENDIAN_BITFIELD
0501         uint32_t mrbcm:1;
0502         uint32_t mrbci:1;
0503         uint32_t mdwe:1;
0504         uint32_t mdre:1;
0505         uint32_t mdrimc:1;
0506         uint32_t mdrrmc:3;
0507         uint32_t tmes:8;
0508         uint32_t teci:1;
0509         uint32_t tmei:1;
0510         uint32_t tmse:1;
0511         uint32_t tmdpes:1;
0512         uint32_t tmapes:1;
0513         uint32_t reserved_9_10:2;
0514         uint32_t tibcd:1;
0515         uint32_t tibde:1;
0516         uint32_t reserved_6_6:1;
0517         uint32_t tidomc:1;
0518         uint32_t tdomc:5;
0519 #else
0520         uint32_t tdomc:5;
0521         uint32_t tidomc:1;
0522         uint32_t reserved_6_6:1;
0523         uint32_t tibde:1;
0524         uint32_t tibcd:1;
0525         uint32_t reserved_9_10:2;
0526         uint32_t tmapes:1;
0527         uint32_t tmdpes:1;
0528         uint32_t tmse:1;
0529         uint32_t tmei:1;
0530         uint32_t teci:1;
0531         uint32_t tmes:8;
0532         uint32_t mdrrmc:3;
0533         uint32_t mdrimc:1;
0534         uint32_t mdre:1;
0535         uint32_t mdwe:1;
0536         uint32_t mrbci:1;
0537         uint32_t mrbcm:1;
0538 #endif
0539     } s;
0540 };
0541 
0542 union cvmx_pci_cfg20 {
0543     uint32_t u32;
0544     struct cvmx_pci_cfg20_s {
0545 #ifdef __BIG_ENDIAN_BITFIELD
0546         uint32_t mdsp:32;
0547 #else
0548         uint32_t mdsp:32;
0549 #endif
0550     } s;
0551 };
0552 
0553 union cvmx_pci_cfg21 {
0554     uint32_t u32;
0555     struct cvmx_pci_cfg21_s {
0556 #ifdef __BIG_ENDIAN_BITFIELD
0557         uint32_t scmre:32;
0558 #else
0559         uint32_t scmre:32;
0560 #endif
0561     } s;
0562 };
0563 
0564 union cvmx_pci_cfg22 {
0565     uint32_t u32;
0566     struct cvmx_pci_cfg22_s {
0567 #ifdef __BIG_ENDIAN_BITFIELD
0568         uint32_t mac:7;
0569         uint32_t reserved_19_24:6;
0570         uint32_t flush:1;
0571         uint32_t mra:1;
0572         uint32_t mtta:1;
0573         uint32_t mrv:8;
0574         uint32_t mttv:8;
0575 #else
0576         uint32_t mttv:8;
0577         uint32_t mrv:8;
0578         uint32_t mtta:1;
0579         uint32_t mra:1;
0580         uint32_t flush:1;
0581         uint32_t reserved_19_24:6;
0582         uint32_t mac:7;
0583 #endif
0584     } s;
0585 };
0586 
0587 union cvmx_pci_cfg56 {
0588     uint32_t u32;
0589     struct cvmx_pci_cfg56_s {
0590 #ifdef __BIG_ENDIAN_BITFIELD
0591         uint32_t reserved_23_31:9;
0592         uint32_t most:3;
0593         uint32_t mmbc:2;
0594         uint32_t roe:1;
0595         uint32_t dpere:1;
0596         uint32_t ncp:8;
0597         uint32_t pxcid:8;
0598 #else
0599         uint32_t pxcid:8;
0600         uint32_t ncp:8;
0601         uint32_t dpere:1;
0602         uint32_t roe:1;
0603         uint32_t mmbc:2;
0604         uint32_t most:3;
0605         uint32_t reserved_23_31:9;
0606 #endif
0607     } s;
0608 };
0609 
0610 union cvmx_pci_cfg57 {
0611     uint32_t u32;
0612     struct cvmx_pci_cfg57_s {
0613 #ifdef __BIG_ENDIAN_BITFIELD
0614         uint32_t reserved_30_31:2;
0615         uint32_t scemr:1;
0616         uint32_t mcrsd:3;
0617         uint32_t mostd:3;
0618         uint32_t mmrbcd:2;
0619         uint32_t dc:1;
0620         uint32_t usc:1;
0621         uint32_t scd:1;
0622         uint32_t m133:1;
0623         uint32_t w64:1;
0624         uint32_t bn:8;
0625         uint32_t dn:5;
0626         uint32_t fn:3;
0627 #else
0628         uint32_t fn:3;
0629         uint32_t dn:5;
0630         uint32_t bn:8;
0631         uint32_t w64:1;
0632         uint32_t m133:1;
0633         uint32_t scd:1;
0634         uint32_t usc:1;
0635         uint32_t dc:1;
0636         uint32_t mmrbcd:2;
0637         uint32_t mostd:3;
0638         uint32_t mcrsd:3;
0639         uint32_t scemr:1;
0640         uint32_t reserved_30_31:2;
0641 #endif
0642     } s;
0643 };
0644 
0645 union cvmx_pci_cfg58 {
0646     uint32_t u32;
0647     struct cvmx_pci_cfg58_s {
0648 #ifdef __BIG_ENDIAN_BITFIELD
0649         uint32_t pmes:5;
0650         uint32_t d2s:1;
0651         uint32_t d1s:1;
0652         uint32_t auxc:3;
0653         uint32_t dsi:1;
0654         uint32_t reserved_20_20:1;
0655         uint32_t pmec:1;
0656         uint32_t pcimiv:3;
0657         uint32_t ncp:8;
0658         uint32_t pmcid:8;
0659 #else
0660         uint32_t pmcid:8;
0661         uint32_t ncp:8;
0662         uint32_t pcimiv:3;
0663         uint32_t pmec:1;
0664         uint32_t reserved_20_20:1;
0665         uint32_t dsi:1;
0666         uint32_t auxc:3;
0667         uint32_t d1s:1;
0668         uint32_t d2s:1;
0669         uint32_t pmes:5;
0670 #endif
0671     } s;
0672 };
0673 
0674 union cvmx_pci_cfg59 {
0675     uint32_t u32;
0676     struct cvmx_pci_cfg59_s {
0677 #ifdef __BIG_ENDIAN_BITFIELD
0678         uint32_t pmdia:8;
0679         uint32_t bpccen:1;
0680         uint32_t bd3h:1;
0681         uint32_t reserved_16_21:6;
0682         uint32_t pmess:1;
0683         uint32_t pmedsia:2;
0684         uint32_t pmds:4;
0685         uint32_t pmeens:1;
0686         uint32_t reserved_2_7:6;
0687         uint32_t ps:2;
0688 #else
0689         uint32_t ps:2;
0690         uint32_t reserved_2_7:6;
0691         uint32_t pmeens:1;
0692         uint32_t pmds:4;
0693         uint32_t pmedsia:2;
0694         uint32_t pmess:1;
0695         uint32_t reserved_16_21:6;
0696         uint32_t bd3h:1;
0697         uint32_t bpccen:1;
0698         uint32_t pmdia:8;
0699 #endif
0700     } s;
0701 };
0702 
0703 union cvmx_pci_cfg60 {
0704     uint32_t u32;
0705     struct cvmx_pci_cfg60_s {
0706 #ifdef __BIG_ENDIAN_BITFIELD
0707         uint32_t reserved_24_31:8;
0708         uint32_t m64:1;
0709         uint32_t mme:3;
0710         uint32_t mmc:3;
0711         uint32_t msien:1;
0712         uint32_t ncp:8;
0713         uint32_t msicid:8;
0714 #else
0715         uint32_t msicid:8;
0716         uint32_t ncp:8;
0717         uint32_t msien:1;
0718         uint32_t mmc:3;
0719         uint32_t mme:3;
0720         uint32_t m64:1;
0721         uint32_t reserved_24_31:8;
0722 #endif
0723     } s;
0724 };
0725 
0726 union cvmx_pci_cfg61 {
0727     uint32_t u32;
0728     struct cvmx_pci_cfg61_s {
0729 #ifdef __BIG_ENDIAN_BITFIELD
0730         uint32_t msi31t2:30;
0731         uint32_t reserved_0_1:2;
0732 #else
0733         uint32_t reserved_0_1:2;
0734         uint32_t msi31t2:30;
0735 #endif
0736     } s;
0737 };
0738 
0739 union cvmx_pci_cfg62 {
0740     uint32_t u32;
0741     struct cvmx_pci_cfg62_s {
0742 #ifdef __BIG_ENDIAN_BITFIELD
0743         uint32_t msi:32;
0744 #else
0745         uint32_t msi:32;
0746 #endif
0747     } s;
0748 };
0749 
0750 union cvmx_pci_cfg63 {
0751     uint32_t u32;
0752     struct cvmx_pci_cfg63_s {
0753 #ifdef __BIG_ENDIAN_BITFIELD
0754         uint32_t reserved_16_31:16;
0755         uint32_t msimd:16;
0756 #else
0757         uint32_t msimd:16;
0758         uint32_t reserved_16_31:16;
0759 #endif
0760     } s;
0761 };
0762 
0763 union cvmx_pci_cnt_reg {
0764     uint64_t u64;
0765     struct cvmx_pci_cnt_reg_s {
0766 #ifdef __BIG_ENDIAN_BITFIELD
0767         uint64_t reserved_38_63:26;
0768         uint64_t hm_pcix:1;
0769         uint64_t hm_speed:2;
0770         uint64_t ap_pcix:1;
0771         uint64_t ap_speed:2;
0772         uint64_t pcicnt:32;
0773 #else
0774         uint64_t pcicnt:32;
0775         uint64_t ap_speed:2;
0776         uint64_t ap_pcix:1;
0777         uint64_t hm_speed:2;
0778         uint64_t hm_pcix:1;
0779         uint64_t reserved_38_63:26;
0780 #endif
0781     } s;
0782 };
0783 
0784 union cvmx_pci_ctl_status_2 {
0785     uint32_t u32;
0786     struct cvmx_pci_ctl_status_2_s {
0787 #ifdef __BIG_ENDIAN_BITFIELD
0788         uint32_t reserved_29_31:3;
0789         uint32_t bb1_hole:3;
0790         uint32_t bb1_siz:1;
0791         uint32_t bb_ca:1;
0792         uint32_t bb_es:2;
0793         uint32_t bb1:1;
0794         uint32_t bb0:1;
0795         uint32_t erst_n:1;
0796         uint32_t bar2pres:1;
0797         uint32_t scmtyp:1;
0798         uint32_t scm:1;
0799         uint32_t en_wfilt:1;
0800         uint32_t reserved_14_14:1;
0801         uint32_t ap_pcix:1;
0802         uint32_t ap_64ad:1;
0803         uint32_t b12_bist:1;
0804         uint32_t pmo_amod:1;
0805         uint32_t pmo_fpc:3;
0806         uint32_t tsr_hwm:3;
0807         uint32_t bar2_enb:1;
0808         uint32_t bar2_esx:2;
0809         uint32_t bar2_cax:1;
0810 #else
0811         uint32_t bar2_cax:1;
0812         uint32_t bar2_esx:2;
0813         uint32_t bar2_enb:1;
0814         uint32_t tsr_hwm:3;
0815         uint32_t pmo_fpc:3;
0816         uint32_t pmo_amod:1;
0817         uint32_t b12_bist:1;
0818         uint32_t ap_64ad:1;
0819         uint32_t ap_pcix:1;
0820         uint32_t reserved_14_14:1;
0821         uint32_t en_wfilt:1;
0822         uint32_t scm:1;
0823         uint32_t scmtyp:1;
0824         uint32_t bar2pres:1;
0825         uint32_t erst_n:1;
0826         uint32_t bb0:1;
0827         uint32_t bb1:1;
0828         uint32_t bb_es:2;
0829         uint32_t bb_ca:1;
0830         uint32_t bb1_siz:1;
0831         uint32_t bb1_hole:3;
0832         uint32_t reserved_29_31:3;
0833 #endif
0834     } s;
0835     struct cvmx_pci_ctl_status_2_cn31xx {
0836 #ifdef __BIG_ENDIAN_BITFIELD
0837         uint32_t reserved_20_31:12;
0838         uint32_t erst_n:1;
0839         uint32_t bar2pres:1;
0840         uint32_t scmtyp:1;
0841         uint32_t scm:1;
0842         uint32_t en_wfilt:1;
0843         uint32_t reserved_14_14:1;
0844         uint32_t ap_pcix:1;
0845         uint32_t ap_64ad:1;
0846         uint32_t b12_bist:1;
0847         uint32_t pmo_amod:1;
0848         uint32_t pmo_fpc:3;
0849         uint32_t tsr_hwm:3;
0850         uint32_t bar2_enb:1;
0851         uint32_t bar2_esx:2;
0852         uint32_t bar2_cax:1;
0853 #else
0854         uint32_t bar2_cax:1;
0855         uint32_t bar2_esx:2;
0856         uint32_t bar2_enb:1;
0857         uint32_t tsr_hwm:3;
0858         uint32_t pmo_fpc:3;
0859         uint32_t pmo_amod:1;
0860         uint32_t b12_bist:1;
0861         uint32_t ap_64ad:1;
0862         uint32_t ap_pcix:1;
0863         uint32_t reserved_14_14:1;
0864         uint32_t en_wfilt:1;
0865         uint32_t scm:1;
0866         uint32_t scmtyp:1;
0867         uint32_t bar2pres:1;
0868         uint32_t erst_n:1;
0869         uint32_t reserved_20_31:12;
0870 #endif
0871     } cn31xx;
0872 };
0873 
0874 union cvmx_pci_dbellx {
0875     uint32_t u32;
0876     struct cvmx_pci_dbellx_s {
0877 #ifdef __BIG_ENDIAN_BITFIELD
0878         uint32_t reserved_16_31:16;
0879         uint32_t inc_val:16;
0880 #else
0881         uint32_t inc_val:16;
0882         uint32_t reserved_16_31:16;
0883 #endif
0884     } s;
0885 };
0886 
0887 union cvmx_pci_dma_cntx {
0888     uint32_t u32;
0889     struct cvmx_pci_dma_cntx_s {
0890 #ifdef __BIG_ENDIAN_BITFIELD
0891         uint32_t dma_cnt:32;
0892 #else
0893         uint32_t dma_cnt:32;
0894 #endif
0895     } s;
0896 };
0897 
0898 union cvmx_pci_dma_int_levx {
0899     uint32_t u32;
0900     struct cvmx_pci_dma_int_levx_s {
0901 #ifdef __BIG_ENDIAN_BITFIELD
0902         uint32_t pkt_cnt:32;
0903 #else
0904         uint32_t pkt_cnt:32;
0905 #endif
0906     } s;
0907 };
0908 
0909 union cvmx_pci_dma_timex {
0910     uint32_t u32;
0911     struct cvmx_pci_dma_timex_s {
0912 #ifdef __BIG_ENDIAN_BITFIELD
0913         uint32_t dma_time:32;
0914 #else
0915         uint32_t dma_time:32;
0916 #endif
0917     } s;
0918 };
0919 
0920 union cvmx_pci_instr_countx {
0921     uint32_t u32;
0922     struct cvmx_pci_instr_countx_s {
0923 #ifdef __BIG_ENDIAN_BITFIELD
0924         uint32_t icnt:32;
0925 #else
0926         uint32_t icnt:32;
0927 #endif
0928     } s;
0929 };
0930 
0931 union cvmx_pci_int_enb {
0932     uint64_t u64;
0933     struct cvmx_pci_int_enb_s {
0934 #ifdef __BIG_ENDIAN_BITFIELD
0935         uint64_t reserved_34_63:30;
0936         uint64_t ill_rd:1;
0937         uint64_t ill_wr:1;
0938         uint64_t win_wr:1;
0939         uint64_t dma1_fi:1;
0940         uint64_t dma0_fi:1;
0941         uint64_t idtime1:1;
0942         uint64_t idtime0:1;
0943         uint64_t idcnt1:1;
0944         uint64_t idcnt0:1;
0945         uint64_t iptime3:1;
0946         uint64_t iptime2:1;
0947         uint64_t iptime1:1;
0948         uint64_t iptime0:1;
0949         uint64_t ipcnt3:1;
0950         uint64_t ipcnt2:1;
0951         uint64_t ipcnt1:1;
0952         uint64_t ipcnt0:1;
0953         uint64_t irsl_int:1;
0954         uint64_t ill_rrd:1;
0955         uint64_t ill_rwr:1;
0956         uint64_t idperr:1;
0957         uint64_t iaperr:1;
0958         uint64_t iserr:1;
0959         uint64_t itsr_abt:1;
0960         uint64_t imsc_msg:1;
0961         uint64_t imsi_mabt:1;
0962         uint64_t imsi_tabt:1;
0963         uint64_t imsi_per:1;
0964         uint64_t imr_tto:1;
0965         uint64_t imr_abt:1;
0966         uint64_t itr_abt:1;
0967         uint64_t imr_wtto:1;
0968         uint64_t imr_wabt:1;
0969         uint64_t itr_wabt:1;
0970 #else
0971         uint64_t itr_wabt:1;
0972         uint64_t imr_wabt:1;
0973         uint64_t imr_wtto:1;
0974         uint64_t itr_abt:1;
0975         uint64_t imr_abt:1;
0976         uint64_t imr_tto:1;
0977         uint64_t imsi_per:1;
0978         uint64_t imsi_tabt:1;
0979         uint64_t imsi_mabt:1;
0980         uint64_t imsc_msg:1;
0981         uint64_t itsr_abt:1;
0982         uint64_t iserr:1;
0983         uint64_t iaperr:1;
0984         uint64_t idperr:1;
0985         uint64_t ill_rwr:1;
0986         uint64_t ill_rrd:1;
0987         uint64_t irsl_int:1;
0988         uint64_t ipcnt0:1;
0989         uint64_t ipcnt1:1;
0990         uint64_t ipcnt2:1;
0991         uint64_t ipcnt3:1;
0992         uint64_t iptime0:1;
0993         uint64_t iptime1:1;
0994         uint64_t iptime2:1;
0995         uint64_t iptime3:1;
0996         uint64_t idcnt0:1;
0997         uint64_t idcnt1:1;
0998         uint64_t idtime0:1;
0999         uint64_t idtime1:1;
1000         uint64_t dma0_fi:1;
1001         uint64_t dma1_fi:1;
1002         uint64_t win_wr:1;
1003         uint64_t ill_wr:1;
1004         uint64_t ill_rd:1;
1005         uint64_t reserved_34_63:30;
1006 #endif
1007     } s;
1008     struct cvmx_pci_int_enb_cn30xx {
1009 #ifdef __BIG_ENDIAN_BITFIELD
1010         uint64_t reserved_34_63:30;
1011         uint64_t ill_rd:1;
1012         uint64_t ill_wr:1;
1013         uint64_t win_wr:1;
1014         uint64_t dma1_fi:1;
1015         uint64_t dma0_fi:1;
1016         uint64_t idtime1:1;
1017         uint64_t idtime0:1;
1018         uint64_t idcnt1:1;
1019         uint64_t idcnt0:1;
1020         uint64_t reserved_22_24:3;
1021         uint64_t iptime0:1;
1022         uint64_t reserved_18_20:3;
1023         uint64_t ipcnt0:1;
1024         uint64_t irsl_int:1;
1025         uint64_t ill_rrd:1;
1026         uint64_t ill_rwr:1;
1027         uint64_t idperr:1;
1028         uint64_t iaperr:1;
1029         uint64_t iserr:1;
1030         uint64_t itsr_abt:1;
1031         uint64_t imsc_msg:1;
1032         uint64_t imsi_mabt:1;
1033         uint64_t imsi_tabt:1;
1034         uint64_t imsi_per:1;
1035         uint64_t imr_tto:1;
1036         uint64_t imr_abt:1;
1037         uint64_t itr_abt:1;
1038         uint64_t imr_wtto:1;
1039         uint64_t imr_wabt:1;
1040         uint64_t itr_wabt:1;
1041 #else
1042         uint64_t itr_wabt:1;
1043         uint64_t imr_wabt:1;
1044         uint64_t imr_wtto:1;
1045         uint64_t itr_abt:1;
1046         uint64_t imr_abt:1;
1047         uint64_t imr_tto:1;
1048         uint64_t imsi_per:1;
1049         uint64_t imsi_tabt:1;
1050         uint64_t imsi_mabt:1;
1051         uint64_t imsc_msg:1;
1052         uint64_t itsr_abt:1;
1053         uint64_t iserr:1;
1054         uint64_t iaperr:1;
1055         uint64_t idperr:1;
1056         uint64_t ill_rwr:1;
1057         uint64_t ill_rrd:1;
1058         uint64_t irsl_int:1;
1059         uint64_t ipcnt0:1;
1060         uint64_t reserved_18_20:3;
1061         uint64_t iptime0:1;
1062         uint64_t reserved_22_24:3;
1063         uint64_t idcnt0:1;
1064         uint64_t idcnt1:1;
1065         uint64_t idtime0:1;
1066         uint64_t idtime1:1;
1067         uint64_t dma0_fi:1;
1068         uint64_t dma1_fi:1;
1069         uint64_t win_wr:1;
1070         uint64_t ill_wr:1;
1071         uint64_t ill_rd:1;
1072         uint64_t reserved_34_63:30;
1073 #endif
1074     } cn30xx;
1075     struct cvmx_pci_int_enb_cn31xx {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077         uint64_t reserved_34_63:30;
1078         uint64_t ill_rd:1;
1079         uint64_t ill_wr:1;
1080         uint64_t win_wr:1;
1081         uint64_t dma1_fi:1;
1082         uint64_t dma0_fi:1;
1083         uint64_t idtime1:1;
1084         uint64_t idtime0:1;
1085         uint64_t idcnt1:1;
1086         uint64_t idcnt0:1;
1087         uint64_t reserved_23_24:2;
1088         uint64_t iptime1:1;
1089         uint64_t iptime0:1;
1090         uint64_t reserved_19_20:2;
1091         uint64_t ipcnt1:1;
1092         uint64_t ipcnt0:1;
1093         uint64_t irsl_int:1;
1094         uint64_t ill_rrd:1;
1095         uint64_t ill_rwr:1;
1096         uint64_t idperr:1;
1097         uint64_t iaperr:1;
1098         uint64_t iserr:1;
1099         uint64_t itsr_abt:1;
1100         uint64_t imsc_msg:1;
1101         uint64_t imsi_mabt:1;
1102         uint64_t imsi_tabt:1;
1103         uint64_t imsi_per:1;
1104         uint64_t imr_tto:1;
1105         uint64_t imr_abt:1;
1106         uint64_t itr_abt:1;
1107         uint64_t imr_wtto:1;
1108         uint64_t imr_wabt:1;
1109         uint64_t itr_wabt:1;
1110 #else
1111         uint64_t itr_wabt:1;
1112         uint64_t imr_wabt:1;
1113         uint64_t imr_wtto:1;
1114         uint64_t itr_abt:1;
1115         uint64_t imr_abt:1;
1116         uint64_t imr_tto:1;
1117         uint64_t imsi_per:1;
1118         uint64_t imsi_tabt:1;
1119         uint64_t imsi_mabt:1;
1120         uint64_t imsc_msg:1;
1121         uint64_t itsr_abt:1;
1122         uint64_t iserr:1;
1123         uint64_t iaperr:1;
1124         uint64_t idperr:1;
1125         uint64_t ill_rwr:1;
1126         uint64_t ill_rrd:1;
1127         uint64_t irsl_int:1;
1128         uint64_t ipcnt0:1;
1129         uint64_t ipcnt1:1;
1130         uint64_t reserved_19_20:2;
1131         uint64_t iptime0:1;
1132         uint64_t iptime1:1;
1133         uint64_t reserved_23_24:2;
1134         uint64_t idcnt0:1;
1135         uint64_t idcnt1:1;
1136         uint64_t idtime0:1;
1137         uint64_t idtime1:1;
1138         uint64_t dma0_fi:1;
1139         uint64_t dma1_fi:1;
1140         uint64_t win_wr:1;
1141         uint64_t ill_wr:1;
1142         uint64_t ill_rd:1;
1143         uint64_t reserved_34_63:30;
1144 #endif
1145     } cn31xx;
1146 };
1147 
1148 union cvmx_pci_int_enb2 {
1149     uint64_t u64;
1150     struct cvmx_pci_int_enb2_s {
1151 #ifdef __BIG_ENDIAN_BITFIELD
1152         uint64_t reserved_34_63:30;
1153         uint64_t ill_rd:1;
1154         uint64_t ill_wr:1;
1155         uint64_t win_wr:1;
1156         uint64_t dma1_fi:1;
1157         uint64_t dma0_fi:1;
1158         uint64_t rdtime1:1;
1159         uint64_t rdtime0:1;
1160         uint64_t rdcnt1:1;
1161         uint64_t rdcnt0:1;
1162         uint64_t rptime3:1;
1163         uint64_t rptime2:1;
1164         uint64_t rptime1:1;
1165         uint64_t rptime0:1;
1166         uint64_t rpcnt3:1;
1167         uint64_t rpcnt2:1;
1168         uint64_t rpcnt1:1;
1169         uint64_t rpcnt0:1;
1170         uint64_t rrsl_int:1;
1171         uint64_t ill_rrd:1;
1172         uint64_t ill_rwr:1;
1173         uint64_t rdperr:1;
1174         uint64_t raperr:1;
1175         uint64_t rserr:1;
1176         uint64_t rtsr_abt:1;
1177         uint64_t rmsc_msg:1;
1178         uint64_t rmsi_mabt:1;
1179         uint64_t rmsi_tabt:1;
1180         uint64_t rmsi_per:1;
1181         uint64_t rmr_tto:1;
1182         uint64_t rmr_abt:1;
1183         uint64_t rtr_abt:1;
1184         uint64_t rmr_wtto:1;
1185         uint64_t rmr_wabt:1;
1186         uint64_t rtr_wabt:1;
1187 #else
1188         uint64_t rtr_wabt:1;
1189         uint64_t rmr_wabt:1;
1190         uint64_t rmr_wtto:1;
1191         uint64_t rtr_abt:1;
1192         uint64_t rmr_abt:1;
1193         uint64_t rmr_tto:1;
1194         uint64_t rmsi_per:1;
1195         uint64_t rmsi_tabt:1;
1196         uint64_t rmsi_mabt:1;
1197         uint64_t rmsc_msg:1;
1198         uint64_t rtsr_abt:1;
1199         uint64_t rserr:1;
1200         uint64_t raperr:1;
1201         uint64_t rdperr:1;
1202         uint64_t ill_rwr:1;
1203         uint64_t ill_rrd:1;
1204         uint64_t rrsl_int:1;
1205         uint64_t rpcnt0:1;
1206         uint64_t rpcnt1:1;
1207         uint64_t rpcnt2:1;
1208         uint64_t rpcnt3:1;
1209         uint64_t rptime0:1;
1210         uint64_t rptime1:1;
1211         uint64_t rptime2:1;
1212         uint64_t rptime3:1;
1213         uint64_t rdcnt0:1;
1214         uint64_t rdcnt1:1;
1215         uint64_t rdtime0:1;
1216         uint64_t rdtime1:1;
1217         uint64_t dma0_fi:1;
1218         uint64_t dma1_fi:1;
1219         uint64_t win_wr:1;
1220         uint64_t ill_wr:1;
1221         uint64_t ill_rd:1;
1222         uint64_t reserved_34_63:30;
1223 #endif
1224     } s;
1225     struct cvmx_pci_int_enb2_cn30xx {
1226 #ifdef __BIG_ENDIAN_BITFIELD
1227         uint64_t reserved_34_63:30;
1228         uint64_t ill_rd:1;
1229         uint64_t ill_wr:1;
1230         uint64_t win_wr:1;
1231         uint64_t dma1_fi:1;
1232         uint64_t dma0_fi:1;
1233         uint64_t rdtime1:1;
1234         uint64_t rdtime0:1;
1235         uint64_t rdcnt1:1;
1236         uint64_t rdcnt0:1;
1237         uint64_t reserved_22_24:3;
1238         uint64_t rptime0:1;
1239         uint64_t reserved_18_20:3;
1240         uint64_t rpcnt0:1;
1241         uint64_t rrsl_int:1;
1242         uint64_t ill_rrd:1;
1243         uint64_t ill_rwr:1;
1244         uint64_t rdperr:1;
1245         uint64_t raperr:1;
1246         uint64_t rserr:1;
1247         uint64_t rtsr_abt:1;
1248         uint64_t rmsc_msg:1;
1249         uint64_t rmsi_mabt:1;
1250         uint64_t rmsi_tabt:1;
1251         uint64_t rmsi_per:1;
1252         uint64_t rmr_tto:1;
1253         uint64_t rmr_abt:1;
1254         uint64_t rtr_abt:1;
1255         uint64_t rmr_wtto:1;
1256         uint64_t rmr_wabt:1;
1257         uint64_t rtr_wabt:1;
1258 #else
1259         uint64_t rtr_wabt:1;
1260         uint64_t rmr_wabt:1;
1261         uint64_t rmr_wtto:1;
1262         uint64_t rtr_abt:1;
1263         uint64_t rmr_abt:1;
1264         uint64_t rmr_tto:1;
1265         uint64_t rmsi_per:1;
1266         uint64_t rmsi_tabt:1;
1267         uint64_t rmsi_mabt:1;
1268         uint64_t rmsc_msg:1;
1269         uint64_t rtsr_abt:1;
1270         uint64_t rserr:1;
1271         uint64_t raperr:1;
1272         uint64_t rdperr:1;
1273         uint64_t ill_rwr:1;
1274         uint64_t ill_rrd:1;
1275         uint64_t rrsl_int:1;
1276         uint64_t rpcnt0:1;
1277         uint64_t reserved_18_20:3;
1278         uint64_t rptime0:1;
1279         uint64_t reserved_22_24:3;
1280         uint64_t rdcnt0:1;
1281         uint64_t rdcnt1:1;
1282         uint64_t rdtime0:1;
1283         uint64_t rdtime1:1;
1284         uint64_t dma0_fi:1;
1285         uint64_t dma1_fi:1;
1286         uint64_t win_wr:1;
1287         uint64_t ill_wr:1;
1288         uint64_t ill_rd:1;
1289         uint64_t reserved_34_63:30;
1290 #endif
1291     } cn30xx;
1292     struct cvmx_pci_int_enb2_cn31xx {
1293 #ifdef __BIG_ENDIAN_BITFIELD
1294         uint64_t reserved_34_63:30;
1295         uint64_t ill_rd:1;
1296         uint64_t ill_wr:1;
1297         uint64_t win_wr:1;
1298         uint64_t dma1_fi:1;
1299         uint64_t dma0_fi:1;
1300         uint64_t rdtime1:1;
1301         uint64_t rdtime0:1;
1302         uint64_t rdcnt1:1;
1303         uint64_t rdcnt0:1;
1304         uint64_t reserved_23_24:2;
1305         uint64_t rptime1:1;
1306         uint64_t rptime0:1;
1307         uint64_t reserved_19_20:2;
1308         uint64_t rpcnt1:1;
1309         uint64_t rpcnt0:1;
1310         uint64_t rrsl_int:1;
1311         uint64_t ill_rrd:1;
1312         uint64_t ill_rwr:1;
1313         uint64_t rdperr:1;
1314         uint64_t raperr:1;
1315         uint64_t rserr:1;
1316         uint64_t rtsr_abt:1;
1317         uint64_t rmsc_msg:1;
1318         uint64_t rmsi_mabt:1;
1319         uint64_t rmsi_tabt:1;
1320         uint64_t rmsi_per:1;
1321         uint64_t rmr_tto:1;
1322         uint64_t rmr_abt:1;
1323         uint64_t rtr_abt:1;
1324         uint64_t rmr_wtto:1;
1325         uint64_t rmr_wabt:1;
1326         uint64_t rtr_wabt:1;
1327 #else
1328         uint64_t rtr_wabt:1;
1329         uint64_t rmr_wabt:1;
1330         uint64_t rmr_wtto:1;
1331         uint64_t rtr_abt:1;
1332         uint64_t rmr_abt:1;
1333         uint64_t rmr_tto:1;
1334         uint64_t rmsi_per:1;
1335         uint64_t rmsi_tabt:1;
1336         uint64_t rmsi_mabt:1;
1337         uint64_t rmsc_msg:1;
1338         uint64_t rtsr_abt:1;
1339         uint64_t rserr:1;
1340         uint64_t raperr:1;
1341         uint64_t rdperr:1;
1342         uint64_t ill_rwr:1;
1343         uint64_t ill_rrd:1;
1344         uint64_t rrsl_int:1;
1345         uint64_t rpcnt0:1;
1346         uint64_t rpcnt1:1;
1347         uint64_t reserved_19_20:2;
1348         uint64_t rptime0:1;
1349         uint64_t rptime1:1;
1350         uint64_t reserved_23_24:2;
1351         uint64_t rdcnt0:1;
1352         uint64_t rdcnt1:1;
1353         uint64_t rdtime0:1;
1354         uint64_t rdtime1:1;
1355         uint64_t dma0_fi:1;
1356         uint64_t dma1_fi:1;
1357         uint64_t win_wr:1;
1358         uint64_t ill_wr:1;
1359         uint64_t ill_rd:1;
1360         uint64_t reserved_34_63:30;
1361 #endif
1362     } cn31xx;
1363 };
1364 
1365 union cvmx_pci_int_sum {
1366     uint64_t u64;
1367     struct cvmx_pci_int_sum_s {
1368 #ifdef __BIG_ENDIAN_BITFIELD
1369         uint64_t reserved_34_63:30;
1370         uint64_t ill_rd:1;
1371         uint64_t ill_wr:1;
1372         uint64_t win_wr:1;
1373         uint64_t dma1_fi:1;
1374         uint64_t dma0_fi:1;
1375         uint64_t dtime1:1;
1376         uint64_t dtime0:1;
1377         uint64_t dcnt1:1;
1378         uint64_t dcnt0:1;
1379         uint64_t ptime3:1;
1380         uint64_t ptime2:1;
1381         uint64_t ptime1:1;
1382         uint64_t ptime0:1;
1383         uint64_t pcnt3:1;
1384         uint64_t pcnt2:1;
1385         uint64_t pcnt1:1;
1386         uint64_t pcnt0:1;
1387         uint64_t rsl_int:1;
1388         uint64_t ill_rrd:1;
1389         uint64_t ill_rwr:1;
1390         uint64_t dperr:1;
1391         uint64_t aperr:1;
1392         uint64_t serr:1;
1393         uint64_t tsr_abt:1;
1394         uint64_t msc_msg:1;
1395         uint64_t msi_mabt:1;
1396         uint64_t msi_tabt:1;
1397         uint64_t msi_per:1;
1398         uint64_t mr_tto:1;
1399         uint64_t mr_abt:1;
1400         uint64_t tr_abt:1;
1401         uint64_t mr_wtto:1;
1402         uint64_t mr_wabt:1;
1403         uint64_t tr_wabt:1;
1404 #else
1405         uint64_t tr_wabt:1;
1406         uint64_t mr_wabt:1;
1407         uint64_t mr_wtto:1;
1408         uint64_t tr_abt:1;
1409         uint64_t mr_abt:1;
1410         uint64_t mr_tto:1;
1411         uint64_t msi_per:1;
1412         uint64_t msi_tabt:1;
1413         uint64_t msi_mabt:1;
1414         uint64_t msc_msg:1;
1415         uint64_t tsr_abt:1;
1416         uint64_t serr:1;
1417         uint64_t aperr:1;
1418         uint64_t dperr:1;
1419         uint64_t ill_rwr:1;
1420         uint64_t ill_rrd:1;
1421         uint64_t rsl_int:1;
1422         uint64_t pcnt0:1;
1423         uint64_t pcnt1:1;
1424         uint64_t pcnt2:1;
1425         uint64_t pcnt3:1;
1426         uint64_t ptime0:1;
1427         uint64_t ptime1:1;
1428         uint64_t ptime2:1;
1429         uint64_t ptime3:1;
1430         uint64_t dcnt0:1;
1431         uint64_t dcnt1:1;
1432         uint64_t dtime0:1;
1433         uint64_t dtime1:1;
1434         uint64_t dma0_fi:1;
1435         uint64_t dma1_fi:1;
1436         uint64_t win_wr:1;
1437         uint64_t ill_wr:1;
1438         uint64_t ill_rd:1;
1439         uint64_t reserved_34_63:30;
1440 #endif
1441     } s;
1442     struct cvmx_pci_int_sum_cn30xx {
1443 #ifdef __BIG_ENDIAN_BITFIELD
1444         uint64_t reserved_34_63:30;
1445         uint64_t ill_rd:1;
1446         uint64_t ill_wr:1;
1447         uint64_t win_wr:1;
1448         uint64_t dma1_fi:1;
1449         uint64_t dma0_fi:1;
1450         uint64_t dtime1:1;
1451         uint64_t dtime0:1;
1452         uint64_t dcnt1:1;
1453         uint64_t dcnt0:1;
1454         uint64_t reserved_22_24:3;
1455         uint64_t ptime0:1;
1456         uint64_t reserved_18_20:3;
1457         uint64_t pcnt0:1;
1458         uint64_t rsl_int:1;
1459         uint64_t ill_rrd:1;
1460         uint64_t ill_rwr:1;
1461         uint64_t dperr:1;
1462         uint64_t aperr:1;
1463         uint64_t serr:1;
1464         uint64_t tsr_abt:1;
1465         uint64_t msc_msg:1;
1466         uint64_t msi_mabt:1;
1467         uint64_t msi_tabt:1;
1468         uint64_t msi_per:1;
1469         uint64_t mr_tto:1;
1470         uint64_t mr_abt:1;
1471         uint64_t tr_abt:1;
1472         uint64_t mr_wtto:1;
1473         uint64_t mr_wabt:1;
1474         uint64_t tr_wabt:1;
1475 #else
1476         uint64_t tr_wabt:1;
1477         uint64_t mr_wabt:1;
1478         uint64_t mr_wtto:1;
1479         uint64_t tr_abt:1;
1480         uint64_t mr_abt:1;
1481         uint64_t mr_tto:1;
1482         uint64_t msi_per:1;
1483         uint64_t msi_tabt:1;
1484         uint64_t msi_mabt:1;
1485         uint64_t msc_msg:1;
1486         uint64_t tsr_abt:1;
1487         uint64_t serr:1;
1488         uint64_t aperr:1;
1489         uint64_t dperr:1;
1490         uint64_t ill_rwr:1;
1491         uint64_t ill_rrd:1;
1492         uint64_t rsl_int:1;
1493         uint64_t pcnt0:1;
1494         uint64_t reserved_18_20:3;
1495         uint64_t ptime0:1;
1496         uint64_t reserved_22_24:3;
1497         uint64_t dcnt0:1;
1498         uint64_t dcnt1:1;
1499         uint64_t dtime0:1;
1500         uint64_t dtime1:1;
1501         uint64_t dma0_fi:1;
1502         uint64_t dma1_fi:1;
1503         uint64_t win_wr:1;
1504         uint64_t ill_wr:1;
1505         uint64_t ill_rd:1;
1506         uint64_t reserved_34_63:30;
1507 #endif
1508     } cn30xx;
1509     struct cvmx_pci_int_sum_cn31xx {
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511         uint64_t reserved_34_63:30;
1512         uint64_t ill_rd:1;
1513         uint64_t ill_wr:1;
1514         uint64_t win_wr:1;
1515         uint64_t dma1_fi:1;
1516         uint64_t dma0_fi:1;
1517         uint64_t dtime1:1;
1518         uint64_t dtime0:1;
1519         uint64_t dcnt1:1;
1520         uint64_t dcnt0:1;
1521         uint64_t reserved_23_24:2;
1522         uint64_t ptime1:1;
1523         uint64_t ptime0:1;
1524         uint64_t reserved_19_20:2;
1525         uint64_t pcnt1:1;
1526         uint64_t pcnt0:1;
1527         uint64_t rsl_int:1;
1528         uint64_t ill_rrd:1;
1529         uint64_t ill_rwr:1;
1530         uint64_t dperr:1;
1531         uint64_t aperr:1;
1532         uint64_t serr:1;
1533         uint64_t tsr_abt:1;
1534         uint64_t msc_msg:1;
1535         uint64_t msi_mabt:1;
1536         uint64_t msi_tabt:1;
1537         uint64_t msi_per:1;
1538         uint64_t mr_tto:1;
1539         uint64_t mr_abt:1;
1540         uint64_t tr_abt:1;
1541         uint64_t mr_wtto:1;
1542         uint64_t mr_wabt:1;
1543         uint64_t tr_wabt:1;
1544 #else
1545         uint64_t tr_wabt:1;
1546         uint64_t mr_wabt:1;
1547         uint64_t mr_wtto:1;
1548         uint64_t tr_abt:1;
1549         uint64_t mr_abt:1;
1550         uint64_t mr_tto:1;
1551         uint64_t msi_per:1;
1552         uint64_t msi_tabt:1;
1553         uint64_t msi_mabt:1;
1554         uint64_t msc_msg:1;
1555         uint64_t tsr_abt:1;
1556         uint64_t serr:1;
1557         uint64_t aperr:1;
1558         uint64_t dperr:1;
1559         uint64_t ill_rwr:1;
1560         uint64_t ill_rrd:1;
1561         uint64_t rsl_int:1;
1562         uint64_t pcnt0:1;
1563         uint64_t pcnt1:1;
1564         uint64_t reserved_19_20:2;
1565         uint64_t ptime0:1;
1566         uint64_t ptime1:1;
1567         uint64_t reserved_23_24:2;
1568         uint64_t dcnt0:1;
1569         uint64_t dcnt1:1;
1570         uint64_t dtime0:1;
1571         uint64_t dtime1:1;
1572         uint64_t dma0_fi:1;
1573         uint64_t dma1_fi:1;
1574         uint64_t win_wr:1;
1575         uint64_t ill_wr:1;
1576         uint64_t ill_rd:1;
1577         uint64_t reserved_34_63:30;
1578 #endif
1579     } cn31xx;
1580 };
1581 
1582 union cvmx_pci_int_sum2 {
1583     uint64_t u64;
1584     struct cvmx_pci_int_sum2_s {
1585 #ifdef __BIG_ENDIAN_BITFIELD
1586         uint64_t reserved_34_63:30;
1587         uint64_t ill_rd:1;
1588         uint64_t ill_wr:1;
1589         uint64_t win_wr:1;
1590         uint64_t dma1_fi:1;
1591         uint64_t dma0_fi:1;
1592         uint64_t dtime1:1;
1593         uint64_t dtime0:1;
1594         uint64_t dcnt1:1;
1595         uint64_t dcnt0:1;
1596         uint64_t ptime3:1;
1597         uint64_t ptime2:1;
1598         uint64_t ptime1:1;
1599         uint64_t ptime0:1;
1600         uint64_t pcnt3:1;
1601         uint64_t pcnt2:1;
1602         uint64_t pcnt1:1;
1603         uint64_t pcnt0:1;
1604         uint64_t rsl_int:1;
1605         uint64_t ill_rrd:1;
1606         uint64_t ill_rwr:1;
1607         uint64_t dperr:1;
1608         uint64_t aperr:1;
1609         uint64_t serr:1;
1610         uint64_t tsr_abt:1;
1611         uint64_t msc_msg:1;
1612         uint64_t msi_mabt:1;
1613         uint64_t msi_tabt:1;
1614         uint64_t msi_per:1;
1615         uint64_t mr_tto:1;
1616         uint64_t mr_abt:1;
1617         uint64_t tr_abt:1;
1618         uint64_t mr_wtto:1;
1619         uint64_t mr_wabt:1;
1620         uint64_t tr_wabt:1;
1621 #else
1622         uint64_t tr_wabt:1;
1623         uint64_t mr_wabt:1;
1624         uint64_t mr_wtto:1;
1625         uint64_t tr_abt:1;
1626         uint64_t mr_abt:1;
1627         uint64_t mr_tto:1;
1628         uint64_t msi_per:1;
1629         uint64_t msi_tabt:1;
1630         uint64_t msi_mabt:1;
1631         uint64_t msc_msg:1;
1632         uint64_t tsr_abt:1;
1633         uint64_t serr:1;
1634         uint64_t aperr:1;
1635         uint64_t dperr:1;
1636         uint64_t ill_rwr:1;
1637         uint64_t ill_rrd:1;
1638         uint64_t rsl_int:1;
1639         uint64_t pcnt0:1;
1640         uint64_t pcnt1:1;
1641         uint64_t pcnt2:1;
1642         uint64_t pcnt3:1;
1643         uint64_t ptime0:1;
1644         uint64_t ptime1:1;
1645         uint64_t ptime2:1;
1646         uint64_t ptime3:1;
1647         uint64_t dcnt0:1;
1648         uint64_t dcnt1:1;
1649         uint64_t dtime0:1;
1650         uint64_t dtime1:1;
1651         uint64_t dma0_fi:1;
1652         uint64_t dma1_fi:1;
1653         uint64_t win_wr:1;
1654         uint64_t ill_wr:1;
1655         uint64_t ill_rd:1;
1656         uint64_t reserved_34_63:30;
1657 #endif
1658     } s;
1659     struct cvmx_pci_int_sum2_cn30xx {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661         uint64_t reserved_34_63:30;
1662         uint64_t ill_rd:1;
1663         uint64_t ill_wr:1;
1664         uint64_t win_wr:1;
1665         uint64_t dma1_fi:1;
1666         uint64_t dma0_fi:1;
1667         uint64_t dtime1:1;
1668         uint64_t dtime0:1;
1669         uint64_t dcnt1:1;
1670         uint64_t dcnt0:1;
1671         uint64_t reserved_22_24:3;
1672         uint64_t ptime0:1;
1673         uint64_t reserved_18_20:3;
1674         uint64_t pcnt0:1;
1675         uint64_t rsl_int:1;
1676         uint64_t ill_rrd:1;
1677         uint64_t ill_rwr:1;
1678         uint64_t dperr:1;
1679         uint64_t aperr:1;
1680         uint64_t serr:1;
1681         uint64_t tsr_abt:1;
1682         uint64_t msc_msg:1;
1683         uint64_t msi_mabt:1;
1684         uint64_t msi_tabt:1;
1685         uint64_t msi_per:1;
1686         uint64_t mr_tto:1;
1687         uint64_t mr_abt:1;
1688         uint64_t tr_abt:1;
1689         uint64_t mr_wtto:1;
1690         uint64_t mr_wabt:1;
1691         uint64_t tr_wabt:1;
1692 #else
1693         uint64_t tr_wabt:1;
1694         uint64_t mr_wabt:1;
1695         uint64_t mr_wtto:1;
1696         uint64_t tr_abt:1;
1697         uint64_t mr_abt:1;
1698         uint64_t mr_tto:1;
1699         uint64_t msi_per:1;
1700         uint64_t msi_tabt:1;
1701         uint64_t msi_mabt:1;
1702         uint64_t msc_msg:1;
1703         uint64_t tsr_abt:1;
1704         uint64_t serr:1;
1705         uint64_t aperr:1;
1706         uint64_t dperr:1;
1707         uint64_t ill_rwr:1;
1708         uint64_t ill_rrd:1;
1709         uint64_t rsl_int:1;
1710         uint64_t pcnt0:1;
1711         uint64_t reserved_18_20:3;
1712         uint64_t ptime0:1;
1713         uint64_t reserved_22_24:3;
1714         uint64_t dcnt0:1;
1715         uint64_t dcnt1:1;
1716         uint64_t dtime0:1;
1717         uint64_t dtime1:1;
1718         uint64_t dma0_fi:1;
1719         uint64_t dma1_fi:1;
1720         uint64_t win_wr:1;
1721         uint64_t ill_wr:1;
1722         uint64_t ill_rd:1;
1723         uint64_t reserved_34_63:30;
1724 #endif
1725     } cn30xx;
1726     struct cvmx_pci_int_sum2_cn31xx {
1727 #ifdef __BIG_ENDIAN_BITFIELD
1728         uint64_t reserved_34_63:30;
1729         uint64_t ill_rd:1;
1730         uint64_t ill_wr:1;
1731         uint64_t win_wr:1;
1732         uint64_t dma1_fi:1;
1733         uint64_t dma0_fi:1;
1734         uint64_t dtime1:1;
1735         uint64_t dtime0:1;
1736         uint64_t dcnt1:1;
1737         uint64_t dcnt0:1;
1738         uint64_t reserved_23_24:2;
1739         uint64_t ptime1:1;
1740         uint64_t ptime0:1;
1741         uint64_t reserved_19_20:2;
1742         uint64_t pcnt1:1;
1743         uint64_t pcnt0:1;
1744         uint64_t rsl_int:1;
1745         uint64_t ill_rrd:1;
1746         uint64_t ill_rwr:1;
1747         uint64_t dperr:1;
1748         uint64_t aperr:1;
1749         uint64_t serr:1;
1750         uint64_t tsr_abt:1;
1751         uint64_t msc_msg:1;
1752         uint64_t msi_mabt:1;
1753         uint64_t msi_tabt:1;
1754         uint64_t msi_per:1;
1755         uint64_t mr_tto:1;
1756         uint64_t mr_abt:1;
1757         uint64_t tr_abt:1;
1758         uint64_t mr_wtto:1;
1759         uint64_t mr_wabt:1;
1760         uint64_t tr_wabt:1;
1761 #else
1762         uint64_t tr_wabt:1;
1763         uint64_t mr_wabt:1;
1764         uint64_t mr_wtto:1;
1765         uint64_t tr_abt:1;
1766         uint64_t mr_abt:1;
1767         uint64_t mr_tto:1;
1768         uint64_t msi_per:1;
1769         uint64_t msi_tabt:1;
1770         uint64_t msi_mabt:1;
1771         uint64_t msc_msg:1;
1772         uint64_t tsr_abt:1;
1773         uint64_t serr:1;
1774         uint64_t aperr:1;
1775         uint64_t dperr:1;
1776         uint64_t ill_rwr:1;
1777         uint64_t ill_rrd:1;
1778         uint64_t rsl_int:1;
1779         uint64_t pcnt0:1;
1780         uint64_t pcnt1:1;
1781         uint64_t reserved_19_20:2;
1782         uint64_t ptime0:1;
1783         uint64_t ptime1:1;
1784         uint64_t reserved_23_24:2;
1785         uint64_t dcnt0:1;
1786         uint64_t dcnt1:1;
1787         uint64_t dtime0:1;
1788         uint64_t dtime1:1;
1789         uint64_t dma0_fi:1;
1790         uint64_t dma1_fi:1;
1791         uint64_t win_wr:1;
1792         uint64_t ill_wr:1;
1793         uint64_t ill_rd:1;
1794         uint64_t reserved_34_63:30;
1795 #endif
1796     } cn31xx;
1797 };
1798 
1799 union cvmx_pci_msi_rcv {
1800     uint32_t u32;
1801     struct cvmx_pci_msi_rcv_s {
1802 #ifdef __BIG_ENDIAN_BITFIELD
1803         uint32_t reserved_6_31:26;
1804         uint32_t intr:6;
1805 #else
1806         uint32_t intr:6;
1807         uint32_t reserved_6_31:26;
1808 #endif
1809     } s;
1810 };
1811 
1812 union cvmx_pci_pkt_creditsx {
1813     uint32_t u32;
1814     struct cvmx_pci_pkt_creditsx_s {
1815 #ifdef __BIG_ENDIAN_BITFIELD
1816         uint32_t pkt_cnt:16;
1817         uint32_t ptr_cnt:16;
1818 #else
1819         uint32_t ptr_cnt:16;
1820         uint32_t pkt_cnt:16;
1821 #endif
1822     } s;
1823 };
1824 
1825 union cvmx_pci_pkts_sentx {
1826     uint32_t u32;
1827     struct cvmx_pci_pkts_sentx_s {
1828 #ifdef __BIG_ENDIAN_BITFIELD
1829         uint32_t pkt_cnt:32;
1830 #else
1831         uint32_t pkt_cnt:32;
1832 #endif
1833     } s;
1834 };
1835 
1836 union cvmx_pci_pkts_sent_int_levx {
1837     uint32_t u32;
1838     struct cvmx_pci_pkts_sent_int_levx_s {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840         uint32_t pkt_cnt:32;
1841 #else
1842         uint32_t pkt_cnt:32;
1843 #endif
1844     } s;
1845 };
1846 
1847 union cvmx_pci_pkts_sent_timex {
1848     uint32_t u32;
1849     struct cvmx_pci_pkts_sent_timex_s {
1850 #ifdef __BIG_ENDIAN_BITFIELD
1851         uint32_t pkt_time:32;
1852 #else
1853         uint32_t pkt_time:32;
1854 #endif
1855     } s;
1856 };
1857 
1858 union cvmx_pci_read_cmd_6 {
1859     uint32_t u32;
1860     struct cvmx_pci_read_cmd_6_s {
1861 #ifdef __BIG_ENDIAN_BITFIELD
1862         uint32_t reserved_9_31:23;
1863         uint32_t min_data:6;
1864         uint32_t prefetch:3;
1865 #else
1866         uint32_t prefetch:3;
1867         uint32_t min_data:6;
1868         uint32_t reserved_9_31:23;
1869 #endif
1870     } s;
1871 };
1872 
1873 union cvmx_pci_read_cmd_c {
1874     uint32_t u32;
1875     struct cvmx_pci_read_cmd_c_s {
1876 #ifdef __BIG_ENDIAN_BITFIELD
1877         uint32_t reserved_9_31:23;
1878         uint32_t min_data:6;
1879         uint32_t prefetch:3;
1880 #else
1881         uint32_t prefetch:3;
1882         uint32_t min_data:6;
1883         uint32_t reserved_9_31:23;
1884 #endif
1885     } s;
1886 };
1887 
1888 union cvmx_pci_read_cmd_e {
1889     uint32_t u32;
1890     struct cvmx_pci_read_cmd_e_s {
1891 #ifdef __BIG_ENDIAN_BITFIELD
1892         uint32_t reserved_9_31:23;
1893         uint32_t min_data:6;
1894         uint32_t prefetch:3;
1895 #else
1896         uint32_t prefetch:3;
1897         uint32_t min_data:6;
1898         uint32_t reserved_9_31:23;
1899 #endif
1900     } s;
1901 };
1902 
1903 union cvmx_pci_read_timeout {
1904     uint64_t u64;
1905     struct cvmx_pci_read_timeout_s {
1906 #ifdef __BIG_ENDIAN_BITFIELD
1907         uint64_t reserved_32_63:32;
1908         uint64_t enb:1;
1909         uint64_t cnt:31;
1910 #else
1911         uint64_t cnt:31;
1912         uint64_t enb:1;
1913         uint64_t reserved_32_63:32;
1914 #endif
1915     } s;
1916 };
1917 
1918 union cvmx_pci_scm_reg {
1919     uint64_t u64;
1920     struct cvmx_pci_scm_reg_s {
1921 #ifdef __BIG_ENDIAN_BITFIELD
1922         uint64_t reserved_32_63:32;
1923         uint64_t scm:32;
1924 #else
1925         uint64_t scm:32;
1926         uint64_t reserved_32_63:32;
1927 #endif
1928     } s;
1929 };
1930 
1931 union cvmx_pci_tsr_reg {
1932     uint64_t u64;
1933     struct cvmx_pci_tsr_reg_s {
1934 #ifdef __BIG_ENDIAN_BITFIELD
1935         uint64_t reserved_36_63:28;
1936         uint64_t tsr:36;
1937 #else
1938         uint64_t tsr:36;
1939         uint64_t reserved_36_63:28;
1940 #endif
1941     } s;
1942 };
1943 
1944 union cvmx_pci_win_rd_addr {
1945     uint64_t u64;
1946     struct cvmx_pci_win_rd_addr_s {
1947 #ifdef __BIG_ENDIAN_BITFIELD
1948         uint64_t reserved_49_63:15;
1949         uint64_t iobit:1;
1950         uint64_t reserved_0_47:48;
1951 #else
1952         uint64_t reserved_0_47:48;
1953         uint64_t iobit:1;
1954         uint64_t reserved_49_63:15;
1955 #endif
1956     } s;
1957     struct cvmx_pci_win_rd_addr_cn30xx {
1958 #ifdef __BIG_ENDIAN_BITFIELD
1959         uint64_t reserved_49_63:15;
1960         uint64_t iobit:1;
1961         uint64_t rd_addr:46;
1962         uint64_t reserved_0_1:2;
1963 #else
1964         uint64_t reserved_0_1:2;
1965         uint64_t rd_addr:46;
1966         uint64_t iobit:1;
1967         uint64_t reserved_49_63:15;
1968 #endif
1969     } cn30xx;
1970     struct cvmx_pci_win_rd_addr_cn38xx {
1971 #ifdef __BIG_ENDIAN_BITFIELD
1972         uint64_t reserved_49_63:15;
1973         uint64_t iobit:1;
1974         uint64_t rd_addr:45;
1975         uint64_t reserved_0_2:3;
1976 #else
1977         uint64_t reserved_0_2:3;
1978         uint64_t rd_addr:45;
1979         uint64_t iobit:1;
1980         uint64_t reserved_49_63:15;
1981 #endif
1982     } cn38xx;
1983 };
1984 
1985 union cvmx_pci_win_rd_data {
1986     uint64_t u64;
1987     struct cvmx_pci_win_rd_data_s {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989         uint64_t rd_data:64;
1990 #else
1991         uint64_t rd_data:64;
1992 #endif
1993     } s;
1994 };
1995 
1996 union cvmx_pci_win_wr_addr {
1997     uint64_t u64;
1998     struct cvmx_pci_win_wr_addr_s {
1999 #ifdef __BIG_ENDIAN_BITFIELD
2000         uint64_t reserved_49_63:15;
2001         uint64_t iobit:1;
2002         uint64_t wr_addr:45;
2003         uint64_t reserved_0_2:3;
2004 #else
2005         uint64_t reserved_0_2:3;
2006         uint64_t wr_addr:45;
2007         uint64_t iobit:1;
2008         uint64_t reserved_49_63:15;
2009 #endif
2010     } s;
2011 };
2012 
2013 union cvmx_pci_win_wr_data {
2014     uint64_t u64;
2015     struct cvmx_pci_win_wr_data_s {
2016 #ifdef __BIG_ENDIAN_BITFIELD
2017         uint64_t wr_data:64;
2018 #else
2019         uint64_t wr_data:64;
2020 #endif
2021     } s;
2022 };
2023 
2024 union cvmx_pci_win_wr_mask {
2025     uint64_t u64;
2026     struct cvmx_pci_win_wr_mask_s {
2027 #ifdef __BIG_ENDIAN_BITFIELD
2028         uint64_t reserved_8_63:56;
2029         uint64_t wr_mask:8;
2030 #else
2031         uint64_t wr_mask:8;
2032         uint64_t reserved_8_63:56;
2033 #endif
2034     } s;
2035 };
2036 
2037 #endif
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