asm/octeon/cvmx-npi-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_NPI_DEFS_H__
0029 #define __CVMX_NPI_DEFS_H__
0030
0031 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
0032 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
0033 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
0034 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
0035 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
0036 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
0037 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
0038 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
0039 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
0040 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
0041 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
0042 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
0043 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
0044 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
0045 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
0046 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
0047 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
0048 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
0049 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
0050 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
0051 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
0052 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
0053 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
0054 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
0055 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
0056 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
0057 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
0058 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
0059 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
0060 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
0061 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
0062 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
0063 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
0064 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
0065 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
0066 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
0067 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
0068 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
0069 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
0070 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
0071 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
0072 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
0073 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
0074 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
0075 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
0076 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
0077 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
0078 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
0079 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
0080 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
0081 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
0082 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
0083 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
0084 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
0085 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
0086 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
0087 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
0088 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
0089 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
0090 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
0091 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
0092 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
0093 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
0094 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
0095 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
0096 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
0097 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
0098 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
0099 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
0100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
0101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
0102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
0103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
0104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
0105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
0106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
0107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
0108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
0109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
0110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
0111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
0112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
0113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
0114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
0115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
0116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
0117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
0118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
0119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
0120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
0121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
0122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
0123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
0124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
0125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
0126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
0127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
0128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
0129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
0130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
0131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
0132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
0133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
0134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
0135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
0136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
0137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
0138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
0139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
0140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
0141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
0142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
0143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
0144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
0145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
0146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
0147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
0148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
0149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
0150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
0151
0152 union cvmx_npi_base_addr_inputx {
0153     uint64_t u64;
0154     struct cvmx_npi_base_addr_inputx_s {
0155 #ifdef __BIG_ENDIAN_BITFIELD
0156         uint64_t baddr:61;
0157         uint64_t reserved_0_2:3;
0158 #else
0159         uint64_t reserved_0_2:3;
0160         uint64_t baddr:61;
0161 #endif
0162     } s;
0163 };
0164
0165 union cvmx_npi_base_addr_outputx {
0166     uint64_t u64;
0167     struct cvmx_npi_base_addr_outputx_s {
0168 #ifdef __BIG_ENDIAN_BITFIELD
0169         uint64_t baddr:61;
0170         uint64_t reserved_0_2:3;
0171 #else
0172         uint64_t reserved_0_2:3;
0173         uint64_t baddr:61;
0174 #endif
0175     } s;
0176 };
0177
0178 union cvmx_npi_bist_status {
0179     uint64_t u64;
0180     struct cvmx_npi_bist_status_s {
0181 #ifdef __BIG_ENDIAN_BITFIELD
0182         uint64_t reserved_20_63:44;
0183         uint64_t csr_bs:1;
0184         uint64_t dif_bs:1;
0185         uint64_t rdp_bs:1;
0186         uint64_t pcnc_bs:1;
0187         uint64_t pcn_bs:1;
0188         uint64_t rdn_bs:1;
0189         uint64_t pcac_bs:1;
0190         uint64_t pcad_bs:1;
0191         uint64_t rdnl_bs:1;
0192         uint64_t pgf_bs:1;
0193         uint64_t pig_bs:1;
0194         uint64_t pof0_bs:1;
0195         uint64_t pof1_bs:1;
0196         uint64_t pof2_bs:1;
0197         uint64_t pof3_bs:1;
0198         uint64_t pos_bs:1;
0199         uint64_t nus_bs:1;
0200         uint64_t dob_bs:1;
0201         uint64_t pdf_bs:1;
0202         uint64_t dpi_bs:1;
0203 #else
0204         uint64_t dpi_bs:1;
0205         uint64_t pdf_bs:1;
0206         uint64_t dob_bs:1;
0207         uint64_t nus_bs:1;
0208         uint64_t pos_bs:1;
0209         uint64_t pof3_bs:1;
0210         uint64_t pof2_bs:1;
0211         uint64_t pof1_bs:1;
0212         uint64_t pof0_bs:1;
0213         uint64_t pig_bs:1;
0214         uint64_t pgf_bs:1;
0215         uint64_t rdnl_bs:1;
0216         uint64_t pcad_bs:1;
0217         uint64_t pcac_bs:1;
0218         uint64_t rdn_bs:1;
0219         uint64_t pcn_bs:1;
0220         uint64_t pcnc_bs:1;
0221         uint64_t rdp_bs:1;
0222         uint64_t dif_bs:1;
0223         uint64_t csr_bs:1;
0224         uint64_t reserved_20_63:44;
0225 #endif
0226     } s;
0227     struct cvmx_npi_bist_status_cn30xx {
0228 #ifdef __BIG_ENDIAN_BITFIELD
0229         uint64_t reserved_20_63:44;
0230         uint64_t csr_bs:1;
0231         uint64_t dif_bs:1;
0232         uint64_t rdp_bs:1;
0233         uint64_t pcnc_bs:1;
0234         uint64_t pcn_bs:1;
0235         uint64_t rdn_bs:1;
0236         uint64_t pcac_bs:1;
0237         uint64_t pcad_bs:1;
0238         uint64_t rdnl_bs:1;
0239         uint64_t pgf_bs:1;
0240         uint64_t pig_bs:1;
0241         uint64_t pof0_bs:1;
0242         uint64_t reserved_5_7:3;
0243         uint64_t pos_bs:1;
0244         uint64_t nus_bs:1;
0245         uint64_t dob_bs:1;
0246         uint64_t pdf_bs:1;
0247         uint64_t dpi_bs:1;
0248 #else
0249         uint64_t dpi_bs:1;
0250         uint64_t pdf_bs:1;
0251         uint64_t dob_bs:1;
0252         uint64_t nus_bs:1;
0253         uint64_t pos_bs:1;
0254         uint64_t reserved_5_7:3;
0255         uint64_t pof0_bs:1;
0256         uint64_t pig_bs:1;
0257         uint64_t pgf_bs:1;
0258         uint64_t rdnl_bs:1;
0259         uint64_t pcad_bs:1;
0260         uint64_t pcac_bs:1;
0261         uint64_t rdn_bs:1;
0262         uint64_t pcn_bs:1;
0263         uint64_t pcnc_bs:1;
0264         uint64_t rdp_bs:1;
0265         uint64_t dif_bs:1;
0266         uint64_t csr_bs:1;
0267         uint64_t reserved_20_63:44;
0268 #endif
0269     } cn30xx;
0270     struct cvmx_npi_bist_status_cn50xx {
0271 #ifdef __BIG_ENDIAN_BITFIELD
0272         uint64_t reserved_20_63:44;
0273         uint64_t csr_bs:1;
0274         uint64_t dif_bs:1;
0275         uint64_t rdp_bs:1;
0276         uint64_t pcnc_bs:1;
0277         uint64_t pcn_bs:1;
0278         uint64_t rdn_bs:1;
0279         uint64_t pcac_bs:1;
0280         uint64_t pcad_bs:1;
0281         uint64_t rdnl_bs:1;
0282         uint64_t pgf_bs:1;
0283         uint64_t pig_bs:1;
0284         uint64_t pof0_bs:1;
0285         uint64_t pof1_bs:1;
0286         uint64_t reserved_5_6:2;
0287         uint64_t pos_bs:1;
0288         uint64_t nus_bs:1;
0289         uint64_t dob_bs:1;
0290         uint64_t pdf_bs:1;
0291         uint64_t dpi_bs:1;
0292 #else
0293         uint64_t dpi_bs:1;
0294         uint64_t pdf_bs:1;
0295         uint64_t dob_bs:1;
0296         uint64_t nus_bs:1;
0297         uint64_t pos_bs:1;
0298         uint64_t reserved_5_6:2;
0299         uint64_t pof1_bs:1;
0300         uint64_t pof0_bs:1;
0301         uint64_t pig_bs:1;
0302         uint64_t pgf_bs:1;
0303         uint64_t rdnl_bs:1;
0304         uint64_t pcad_bs:1;
0305         uint64_t pcac_bs:1;
0306         uint64_t rdn_bs:1;
0307         uint64_t pcn_bs:1;
0308         uint64_t pcnc_bs:1;
0309         uint64_t rdp_bs:1;
0310         uint64_t dif_bs:1;
0311         uint64_t csr_bs:1;
0312         uint64_t reserved_20_63:44;
0313 #endif
0314     } cn50xx;
0315 };
0316
0317 union cvmx_npi_buff_size_outputx {
0318     uint64_t u64;
0319     struct cvmx_npi_buff_size_outputx_s {
0320 #ifdef __BIG_ENDIAN_BITFIELD
0321         uint64_t reserved_23_63:41;
0322         uint64_t isize:7;
0323         uint64_t bsize:16;
0324 #else
0325         uint64_t bsize:16;
0326         uint64_t isize:7;
0327         uint64_t reserved_23_63:41;
0328 #endif
0329     } s;
0330 };
0331
0332 union cvmx_npi_comp_ctl {
0333     uint64_t u64;
0334     struct cvmx_npi_comp_ctl_s {
0335 #ifdef __BIG_ENDIAN_BITFIELD
0336         uint64_t reserved_10_63:54;
0337         uint64_t pctl:5;
0338         uint64_t nctl:5;
0339 #else
0340         uint64_t nctl:5;
0341         uint64_t pctl:5;
0342         uint64_t reserved_10_63:54;
0343 #endif
0344     } s;
0345 };
0346
0347 union cvmx_npi_ctl_status {
0348     uint64_t u64;
0349     struct cvmx_npi_ctl_status_s {
0350 #ifdef __BIG_ENDIAN_BITFIELD
0351         uint64_t reserved_63_63:1;
0352         uint64_t chip_rev:8;
0353         uint64_t dis_pniw:1;
0354         uint64_t out3_enb:1;
0355         uint64_t out2_enb:1;
0356         uint64_t out1_enb:1;
0357         uint64_t out0_enb:1;
0358         uint64_t ins3_enb:1;
0359         uint64_t ins2_enb:1;
0360         uint64_t ins1_enb:1;
0361         uint64_t ins0_enb:1;
0362         uint64_t ins3_64b:1;
0363         uint64_t ins2_64b:1;
0364         uint64_t ins1_64b:1;
0365         uint64_t ins0_64b:1;
0366         uint64_t pci_wdis:1;
0367         uint64_t wait_com:1;
0368         uint64_t reserved_37_39:3;
0369         uint64_t max_word:5;
0370         uint64_t reserved_10_31:22;
0371         uint64_t timer:10;
0372 #else
0373         uint64_t timer:10;
0374         uint64_t reserved_10_31:22;
0375         uint64_t max_word:5;
0376         uint64_t reserved_37_39:3;
0377         uint64_t wait_com:1;
0378         uint64_t pci_wdis:1;
0379         uint64_t ins0_64b:1;
0380         uint64_t ins1_64b:1;
0381         uint64_t ins2_64b:1;
0382         uint64_t ins3_64b:1;
0383         uint64_t ins0_enb:1;
0384         uint64_t ins1_enb:1;
0385         uint64_t ins2_enb:1;
0386         uint64_t ins3_enb:1;
0387         uint64_t out0_enb:1;
0388         uint64_t out1_enb:1;
0389         uint64_t out2_enb:1;
0390         uint64_t out3_enb:1;
0391         uint64_t dis_pniw:1;
0392         uint64_t chip_rev:8;
0393         uint64_t reserved_63_63:1;
0394 #endif
0395     } s;
0396     struct cvmx_npi_ctl_status_cn30xx {
0397 #ifdef __BIG_ENDIAN_BITFIELD
0398         uint64_t reserved_63_63:1;
0399         uint64_t chip_rev:8;
0400         uint64_t dis_pniw:1;
0401         uint64_t reserved_51_53:3;
0402         uint64_t out0_enb:1;
0403         uint64_t reserved_47_49:3;
0404         uint64_t ins0_enb:1;
0405         uint64_t reserved_43_45:3;
0406         uint64_t ins0_64b:1;
0407         uint64_t pci_wdis:1;
0408         uint64_t wait_com:1;
0409         uint64_t reserved_37_39:3;
0410         uint64_t max_word:5;
0411         uint64_t reserved_10_31:22;
0412         uint64_t timer:10;
0413 #else
0414         uint64_t timer:10;
0415         uint64_t reserved_10_31:22;
0416         uint64_t max_word:5;
0417         uint64_t reserved_37_39:3;
0418         uint64_t wait_com:1;
0419         uint64_t pci_wdis:1;
0420         uint64_t ins0_64b:1;
0421         uint64_t reserved_43_45:3;
0422         uint64_t ins0_enb:1;
0423         uint64_t reserved_47_49:3;
0424         uint64_t out0_enb:1;
0425         uint64_t reserved_51_53:3;
0426         uint64_t dis_pniw:1;
0427         uint64_t chip_rev:8;
0428         uint64_t reserved_63_63:1;
0429 #endif
0430     } cn30xx;
0431     struct cvmx_npi_ctl_status_cn31xx {
0432 #ifdef __BIG_ENDIAN_BITFIELD
0433         uint64_t reserved_63_63:1;
0434         uint64_t chip_rev:8;
0435         uint64_t dis_pniw:1;
0436         uint64_t reserved_52_53:2;
0437         uint64_t out1_enb:1;
0438         uint64_t out0_enb:1;
0439         uint64_t reserved_48_49:2;
0440         uint64_t ins1_enb:1;
0441         uint64_t ins0_enb:1;
0442         uint64_t reserved_44_45:2;
0443         uint64_t ins1_64b:1;
0444         uint64_t ins0_64b:1;
0445         uint64_t pci_wdis:1;
0446         uint64_t wait_com:1;
0447         uint64_t reserved_37_39:3;
0448         uint64_t max_word:5;
0449         uint64_t reserved_10_31:22;
0450         uint64_t timer:10;
0451 #else
0452         uint64_t timer:10;
0453         uint64_t reserved_10_31:22;
0454         uint64_t max_word:5;
0455         uint64_t reserved_37_39:3;
0456         uint64_t wait_com:1;
0457         uint64_t pci_wdis:1;
0458         uint64_t ins0_64b:1;
0459         uint64_t ins1_64b:1;
0460         uint64_t reserved_44_45:2;
0461         uint64_t ins0_enb:1;
0462         uint64_t ins1_enb:1;
0463         uint64_t reserved_48_49:2;
0464         uint64_t out0_enb:1;
0465         uint64_t out1_enb:1;
0466         uint64_t reserved_52_53:2;
0467         uint64_t dis_pniw:1;
0468         uint64_t chip_rev:8;
0469         uint64_t reserved_63_63:1;
0470 #endif
0471     } cn31xx;
0472 };
0473
0474 union cvmx_npi_dbg_select {
0475     uint64_t u64;
0476     struct cvmx_npi_dbg_select_s {
0477 #ifdef __BIG_ENDIAN_BITFIELD
0478         uint64_t reserved_16_63:48;
0479         uint64_t dbg_sel:16;
0480 #else
0481         uint64_t dbg_sel:16;
0482         uint64_t reserved_16_63:48;
0483 #endif
0484     } s;
0485 };
0486
0487 union cvmx_npi_dma_control {
0488     uint64_t u64;
0489     struct cvmx_npi_dma_control_s {
0490 #ifdef __BIG_ENDIAN_BITFIELD
0491         uint64_t reserved_36_63:28;
0492         uint64_t b0_lend:1;
0493         uint64_t dwb_denb:1;
0494         uint64_t dwb_ichk:9;
0495         uint64_t fpa_que:3;
0496         uint64_t o_add1:1;
0497         uint64_t o_ro:1;
0498         uint64_t o_ns:1;
0499         uint64_t o_es:2;
0500         uint64_t o_mode:1;
0501         uint64_t hp_enb:1;
0502         uint64_t lp_enb:1;
0503         uint64_t csize:14;
0504 #else
0505         uint64_t csize:14;
0506         uint64_t lp_enb:1;
0507         uint64_t hp_enb:1;
0508         uint64_t o_mode:1;
0509         uint64_t o_es:2;
0510         uint64_t o_ns:1;
0511         uint64_t o_ro:1;
0512         uint64_t o_add1:1;
0513         uint64_t fpa_que:3;
0514         uint64_t dwb_ichk:9;
0515         uint64_t dwb_denb:1;
0516         uint64_t b0_lend:1;
0517         uint64_t reserved_36_63:28;
0518 #endif
0519     } s;
0520 };
0521
0522 union cvmx_npi_dma_highp_counts {
0523     uint64_t u64;
0524     struct cvmx_npi_dma_highp_counts_s {
0525 #ifdef __BIG_ENDIAN_BITFIELD
0526         uint64_t reserved_39_63:25;
0527         uint64_t fcnt:7;
0528         uint64_t dbell:32;
0529 #else
0530         uint64_t dbell:32;
0531         uint64_t fcnt:7;
0532         uint64_t reserved_39_63:25;
0533 #endif
0534     } s;
0535 };
0536
0537 union cvmx_npi_dma_highp_naddr {
0538     uint64_t u64;
0539     struct cvmx_npi_dma_highp_naddr_s {
0540 #ifdef __BIG_ENDIAN_BITFIELD
0541         uint64_t reserved_40_63:24;
0542         uint64_t state:4;
0543         uint64_t addr:36;
0544 #else
0545         uint64_t addr:36;
0546         uint64_t state:4;
0547         uint64_t reserved_40_63:24;
0548 #endif
0549     } s;
0550 };
0551
0552 union cvmx_npi_dma_lowp_counts {
0553     uint64_t u64;
0554     struct cvmx_npi_dma_lowp_counts_s {
0555 #ifdef __BIG_ENDIAN_BITFIELD
0556         uint64_t reserved_39_63:25;
0557         uint64_t fcnt:7;
0558         uint64_t dbell:32;
0559 #else
0560         uint64_t dbell:32;
0561         uint64_t fcnt:7;
0562         uint64_t reserved_39_63:25;
0563 #endif
0564     } s;
0565 };
0566
0567 union cvmx_npi_dma_lowp_naddr {
0568     uint64_t u64;
0569     struct cvmx_npi_dma_lowp_naddr_s {
0570 #ifdef __BIG_ENDIAN_BITFIELD
0571         uint64_t reserved_40_63:24;
0572         uint64_t state:4;
0573         uint64_t addr:36;
0574 #else
0575         uint64_t addr:36;
0576         uint64_t state:4;
0577         uint64_t reserved_40_63:24;
0578 #endif
0579     } s;
0580 };
0581
0582 union cvmx_npi_highp_dbell {
0583     uint64_t u64;
0584     struct cvmx_npi_highp_dbell_s {
0585 #ifdef __BIG_ENDIAN_BITFIELD
0586         uint64_t reserved_16_63:48;
0587         uint64_t dbell:16;
0588 #else
0589         uint64_t dbell:16;
0590         uint64_t reserved_16_63:48;
0591 #endif
0592     } s;
0593 };
0594
0595 union cvmx_npi_highp_ibuff_saddr {
0596     uint64_t u64;
0597     struct cvmx_npi_highp_ibuff_saddr_s {
0598 #ifdef __BIG_ENDIAN_BITFIELD
0599         uint64_t reserved_36_63:28;
0600         uint64_t saddr:36;
0601 #else
0602         uint64_t saddr:36;
0603         uint64_t reserved_36_63:28;
0604 #endif
0605     } s;
0606 };
0607
0608 union cvmx_npi_input_control {
0609     uint64_t u64;
0610     struct cvmx_npi_input_control_s {
0611 #ifdef __BIG_ENDIAN_BITFIELD
0612         uint64_t reserved_23_63:41;
0613         uint64_t pkt_rr:1;
0614         uint64_t pbp_dhi:13;
0615         uint64_t d_nsr:1;
0616         uint64_t d_esr:2;
0617         uint64_t d_ror:1;
0618         uint64_t use_csr:1;
0619         uint64_t nsr:1;
0620         uint64_t esr:2;
0621         uint64_t ror:1;
0622 #else
0623         uint64_t ror:1;
0624         uint64_t esr:2;
0625         uint64_t nsr:1;
0626         uint64_t use_csr:1;
0627         uint64_t d_ror:1;
0628         uint64_t d_esr:2;
0629         uint64_t d_nsr:1;
0630         uint64_t pbp_dhi:13;
0631         uint64_t pkt_rr:1;
0632         uint64_t reserved_23_63:41;
0633 #endif
0634     } s;
0635     struct cvmx_npi_input_control_cn30xx {
0636 #ifdef __BIG_ENDIAN_BITFIELD
0637         uint64_t reserved_22_63:42;
0638         uint64_t pbp_dhi:13;
0639         uint64_t d_nsr:1;
0640         uint64_t d_esr:2;
0641         uint64_t d_ror:1;
0642         uint64_t use_csr:1;
0643         uint64_t nsr:1;
0644         uint64_t esr:2;
0645         uint64_t ror:1;
0646 #else
0647         uint64_t ror:1;
0648         uint64_t esr:2;
0649         uint64_t nsr:1;
0650         uint64_t use_csr:1;
0651         uint64_t d_ror:1;
0652         uint64_t d_esr:2;
0653         uint64_t d_nsr:1;
0654         uint64_t pbp_dhi:13;
0655         uint64_t reserved_22_63:42;
0656 #endif
0657     } cn30xx;
0658 };
0659
0660 union cvmx_npi_int_enb {
0661     uint64_t u64;
0662     struct cvmx_npi_int_enb_s {
0663 #ifdef __BIG_ENDIAN_BITFIELD
0664         uint64_t reserved_62_63:2;
0665         uint64_t q1_a_f:1;
0666         uint64_t q1_s_e:1;
0667         uint64_t pdf_p_f:1;
0668         uint64_t pdf_p_e:1;
0669         uint64_t pcf_p_f:1;
0670         uint64_t pcf_p_e:1;
0671         uint64_t rdx_s_e:1;
0672         uint64_t rwx_s_e:1;
0673         uint64_t pnc_a_f:1;
0674         uint64_t pnc_s_e:1;
0675         uint64_t com_a_f:1;
0676         uint64_t com_s_e:1;
0677         uint64_t q3_a_f:1;
0678         uint64_t q3_s_e:1;
0679         uint64_t q2_a_f:1;
0680         uint64_t q2_s_e:1;
0681         uint64_t pcr_a_f:1;
0682         uint64_t pcr_s_e:1;
0683         uint64_t fcr_a_f:1;
0684         uint64_t fcr_s_e:1;
0685         uint64_t iobdma:1;
0686         uint64_t p_dperr:1;
0687         uint64_t win_rto:1;
0688         uint64_t i3_pperr:1;
0689         uint64_t i2_pperr:1;
0690         uint64_t i1_pperr:1;
0691         uint64_t i0_pperr:1;
0692         uint64_t p3_ptout:1;
0693         uint64_t p2_ptout:1;
0694         uint64_t p1_ptout:1;
0695         uint64_t p0_ptout:1;
0696         uint64_t p3_pperr:1;
0697         uint64_t p2_pperr:1;
0698         uint64_t p1_pperr:1;
0699         uint64_t p0_pperr:1;
0700         uint64_t g3_rtout:1;
0701         uint64_t g2_rtout:1;
0702         uint64_t g1_rtout:1;
0703         uint64_t g0_rtout:1;
0704         uint64_t p3_perr:1;
0705         uint64_t p2_perr:1;
0706         uint64_t p1_perr:1;
0707         uint64_t p0_perr:1;
0708         uint64_t p3_rtout:1;
0709         uint64_t p2_rtout:1;
0710         uint64_t p1_rtout:1;
0711         uint64_t p0_rtout:1;
0712         uint64_t i3_overf:1;
0713         uint64_t i2_overf:1;
0714         uint64_t i1_overf:1;
0715         uint64_t i0_overf:1;
0716         uint64_t i3_rtout:1;
0717         uint64_t i2_rtout:1;
0718         uint64_t i1_rtout:1;
0719         uint64_t i0_rtout:1;
0720         uint64_t po3_2sml:1;
0721         uint64_t po2_2sml:1;
0722         uint64_t po1_2sml:1;
0723         uint64_t po0_2sml:1;
0724         uint64_t pci_rsl:1;
0725         uint64_t rml_wto:1;
0726         uint64_t rml_rto:1;
0727 #else
0728         uint64_t rml_rto:1;
0729         uint64_t rml_wto:1;
0730         uint64_t pci_rsl:1;
0731         uint64_t po0_2sml:1;
0732         uint64_t po1_2sml:1;
0733         uint64_t po2_2sml:1;
0734         uint64_t po3_2sml:1;
0735         uint64_t i0_rtout:1;
0736         uint64_t i1_rtout:1;
0737         uint64_t i2_rtout:1;
0738         uint64_t i3_rtout:1;
0739         uint64_t i0_overf:1;
0740         uint64_t i1_overf:1;
0741         uint64_t i2_overf:1;
0742         uint64_t i3_overf:1;
0743         uint64_t p0_rtout:1;
0744         uint64_t p1_rtout:1;
0745         uint64_t p2_rtout:1;
0746         uint64_t p3_rtout:1;
0747         uint64_t p0_perr:1;
0748         uint64_t p1_perr:1;
0749         uint64_t p2_perr:1;
0750         uint64_t p3_perr:1;
0751         uint64_t g0_rtout:1;
0752         uint64_t g1_rtout:1;
0753         uint64_t g2_rtout:1;
0754         uint64_t g3_rtout:1;
0755         uint64_t p0_pperr:1;
0756         uint64_t p1_pperr:1;
0757         uint64_t p2_pperr:1;
0758         uint64_t p3_pperr:1;
0759         uint64_t p0_ptout:1;
0760         uint64_t p1_ptout:1;
0761         uint64_t p2_ptout:1;
0762         uint64_t p3_ptout:1;
0763         uint64_t i0_pperr:1;
0764         uint64_t i1_pperr:1;
0765         uint64_t i2_pperr:1;
0766         uint64_t i3_pperr:1;
0767         uint64_t win_rto:1;
0768         uint64_t p_dperr:1;
0769         uint64_t iobdma:1;
0770         uint64_t fcr_s_e:1;
0771         uint64_t fcr_a_f:1;
0772         uint64_t pcr_s_e:1;
0773         uint64_t pcr_a_f:1;
0774         uint64_t q2_s_e:1;
0775         uint64_t q2_a_f:1;
0776         uint64_t q3_s_e:1;
0777         uint64_t q3_a_f:1;
0778         uint64_t com_s_e:1;
0779         uint64_t com_a_f:1;
0780         uint64_t pnc_s_e:1;
0781         uint64_t pnc_a_f:1;
0782         uint64_t rwx_s_e:1;
0783         uint64_t rdx_s_e:1;
0784         uint64_t pcf_p_e:1;
0785         uint64_t pcf_p_f:1;
0786         uint64_t pdf_p_e:1;
0787         uint64_t pdf_p_f:1;
0788         uint64_t q1_s_e:1;
0789         uint64_t q1_a_f:1;
0790         uint64_t reserved_62_63:2;
0791 #endif
0792     } s;
0793     struct cvmx_npi_int_enb_cn30xx {
0794 #ifdef __BIG_ENDIAN_BITFIELD
0795         uint64_t reserved_62_63:2;
0796         uint64_t q1_a_f:1;
0797         uint64_t q1_s_e:1;
0798         uint64_t pdf_p_f:1;
0799         uint64_t pdf_p_e:1;
0800         uint64_t pcf_p_f:1;
0801         uint64_t pcf_p_e:1;
0802         uint64_t rdx_s_e:1;
0803         uint64_t rwx_s_e:1;
0804         uint64_t pnc_a_f:1;
0805         uint64_t pnc_s_e:1;
0806         uint64_t com_a_f:1;
0807         uint64_t com_s_e:1;
0808         uint64_t q3_a_f:1;
0809         uint64_t q3_s_e:1;
0810         uint64_t q2_a_f:1;
0811         uint64_t q2_s_e:1;
0812         uint64_t pcr_a_f:1;
0813         uint64_t pcr_s_e:1;
0814         uint64_t fcr_a_f:1;
0815         uint64_t fcr_s_e:1;
0816         uint64_t iobdma:1;
0817         uint64_t p_dperr:1;
0818         uint64_t win_rto:1;
0819         uint64_t reserved_36_38:3;
0820         uint64_t i0_pperr:1;
0821         uint64_t reserved_32_34:3;
0822         uint64_t p0_ptout:1;
0823         uint64_t reserved_28_30:3;
0824         uint64_t p0_pperr:1;
0825         uint64_t reserved_24_26:3;
0826         uint64_t g0_rtout:1;
0827         uint64_t reserved_20_22:3;
0828         uint64_t p0_perr:1;
0829         uint64_t reserved_16_18:3;
0830         uint64_t p0_rtout:1;
0831         uint64_t reserved_12_14:3;
0832         uint64_t i0_overf:1;
0833         uint64_t reserved_8_10:3;
0834         uint64_t i0_rtout:1;
0835         uint64_t reserved_4_6:3;
0836         uint64_t po0_2sml:1;
0837         uint64_t pci_rsl:1;
0838         uint64_t rml_wto:1;
0839         uint64_t rml_rto:1;
0840 #else
0841         uint64_t rml_rto:1;
0842         uint64_t rml_wto:1;
0843         uint64_t pci_rsl:1;
0844         uint64_t po0_2sml:1;
0845         uint64_t reserved_4_6:3;
0846         uint64_t i0_rtout:1;
0847         uint64_t reserved_8_10:3;
0848         uint64_t i0_overf:1;
0849         uint64_t reserved_12_14:3;
0850         uint64_t p0_rtout:1;
0851         uint64_t reserved_16_18:3;
0852         uint64_t p0_perr:1;
0853         uint64_t reserved_20_22:3;
0854         uint64_t g0_rtout:1;
0855         uint64_t reserved_24_26:3;
0856         uint64_t p0_pperr:1;
0857         uint64_t reserved_28_30:3;
0858         uint64_t p0_ptout:1;
0859         uint64_t reserved_32_34:3;
0860         uint64_t i0_pperr:1;
0861         uint64_t reserved_36_38:3;
0862         uint64_t win_rto:1;
0863         uint64_t p_dperr:1;
0864         uint64_t iobdma:1;
0865         uint64_t fcr_s_e:1;
0866         uint64_t fcr_a_f:1;
0867         uint64_t pcr_s_e:1;
0868         uint64_t pcr_a_f:1;
0869         uint64_t q2_s_e:1;
0870         uint64_t q2_a_f:1;
0871         uint64_t q3_s_e:1;
0872         uint64_t q3_a_f:1;
0873         uint64_t com_s_e:1;
0874         uint64_t com_a_f:1;
0875         uint64_t pnc_s_e:1;
0876         uint64_t pnc_a_f:1;
0877         uint64_t rwx_s_e:1;
0878         uint64_t rdx_s_e:1;
0879         uint64_t pcf_p_e:1;
0880         uint64_t pcf_p_f:1;
0881         uint64_t pdf_p_e:1;
0882         uint64_t pdf_p_f:1;
0883         uint64_t q1_s_e:1;
0884         uint64_t q1_a_f:1;
0885         uint64_t reserved_62_63:2;
0886 #endif
0887     } cn30xx;
0888     struct cvmx_npi_int_enb_cn31xx {
0889 #ifdef __BIG_ENDIAN_BITFIELD
0890         uint64_t reserved_62_63:2;
0891         uint64_t q1_a_f:1;
0892         uint64_t q1_s_e:1;
0893         uint64_t pdf_p_f:1;
0894         uint64_t pdf_p_e:1;
0895         uint64_t pcf_p_f:1;
0896         uint64_t pcf_p_e:1;
0897         uint64_t rdx_s_e:1;
0898         uint64_t rwx_s_e:1;
0899         uint64_t pnc_a_f:1;
0900         uint64_t pnc_s_e:1;
0901         uint64_t com_a_f:1;
0902         uint64_t com_s_e:1;
0903         uint64_t q3_a_f:1;
0904         uint64_t q3_s_e:1;
0905         uint64_t q2_a_f:1;
0906         uint64_t q2_s_e:1;
0907         uint64_t pcr_a_f:1;
0908         uint64_t pcr_s_e:1;
0909         uint64_t fcr_a_f:1;
0910         uint64_t fcr_s_e:1;
0911         uint64_t iobdma:1;
0912         uint64_t p_dperr:1;
0913         uint64_t win_rto:1;
0914         uint64_t reserved_37_38:2;
0915         uint64_t i1_pperr:1;
0916         uint64_t i0_pperr:1;
0917         uint64_t reserved_33_34:2;
0918         uint64_t p1_ptout:1;
0919         uint64_t p0_ptout:1;
0920         uint64_t reserved_29_30:2;
0921         uint64_t p1_pperr:1;
0922         uint64_t p0_pperr:1;
0923         uint64_t reserved_25_26:2;
0924         uint64_t g1_rtout:1;
0925         uint64_t g0_rtout:1;
0926         uint64_t reserved_21_22:2;
0927         uint64_t p1_perr:1;
0928         uint64_t p0_perr:1;
0929         uint64_t reserved_17_18:2;
0930         uint64_t p1_rtout:1;
0931         uint64_t p0_rtout:1;
0932         uint64_t reserved_13_14:2;
0933         uint64_t i1_overf:1;
0934         uint64_t i0_overf:1;
0935         uint64_t reserved_9_10:2;
0936         uint64_t i1_rtout:1;
0937         uint64_t i0_rtout:1;
0938         uint64_t reserved_5_6:2;
0939         uint64_t po1_2sml:1;
0940         uint64_t po0_2sml:1;
0941         uint64_t pci_rsl:1;
0942         uint64_t rml_wto:1;
0943         uint64_t rml_rto:1;
0944 #else
0945         uint64_t rml_rto:1;
0946         uint64_t rml_wto:1;
0947         uint64_t pci_rsl:1;
0948         uint64_t po0_2sml:1;
0949         uint64_t po1_2sml:1;
0950         uint64_t reserved_5_6:2;
0951         uint64_t i0_rtout:1;
0952         uint64_t i1_rtout:1;
0953         uint64_t reserved_9_10:2;
0954         uint64_t i0_overf:1;
0955         uint64_t i1_overf:1;
0956         uint64_t reserved_13_14:2;
0957         uint64_t p0_rtout:1;
0958         uint64_t p1_rtout:1;
0959         uint64_t reserved_17_18:2;
0960         uint64_t p0_perr:1;
0961         uint64_t p1_perr:1;
0962         uint64_t reserved_21_22:2;
0963         uint64_t g0_rtout:1;
0964         uint64_t g1_rtout:1;
0965         uint64_t reserved_25_26:2;
0966         uint64_t p0_pperr:1;
0967         uint64_t p1_pperr:1;
0968         uint64_t reserved_29_30:2;
0969         uint64_t p0_ptout:1;
0970         uint64_t p1_ptout:1;
0971         uint64_t reserved_33_34:2;
0972         uint64_t i0_pperr:1;
0973         uint64_t i1_pperr:1;
0974         uint64_t reserved_37_38:2;
0975         uint64_t win_rto:1;
0976         uint64_t p_dperr:1;
0977         uint64_t iobdma:1;
0978         uint64_t fcr_s_e:1;
0979         uint64_t fcr_a_f:1;
0980         uint64_t pcr_s_e:1;
0981         uint64_t pcr_a_f:1;
0982         uint64_t q2_s_e:1;
0983         uint64_t q2_a_f:1;
0984         uint64_t q3_s_e:1;
0985         uint64_t q3_a_f:1;
0986         uint64_t com_s_e:1;
0987         uint64_t com_a_f:1;
0988         uint64_t pnc_s_e:1;
0989         uint64_t pnc_a_f:1;
0990         uint64_t rwx_s_e:1;
0991         uint64_t rdx_s_e:1;
0992         uint64_t pcf_p_e:1;
0993         uint64_t pcf_p_f:1;
0994         uint64_t pdf_p_e:1;
0995         uint64_t pdf_p_f:1;
0996         uint64_t q1_s_e:1;
0997         uint64_t q1_a_f:1;
0998         uint64_t reserved_62_63:2;
0999 #endif
1000     } cn31xx;
1001     struct cvmx_npi_int_enb_cn38xxp2 {
1002 #ifdef __BIG_ENDIAN_BITFIELD
1003         uint64_t reserved_42_63:22;
1004         uint64_t iobdma:1;
1005         uint64_t p_dperr:1;
1006         uint64_t win_rto:1;
1007         uint64_t i3_pperr:1;
1008         uint64_t i2_pperr:1;
1009         uint64_t i1_pperr:1;
1010         uint64_t i0_pperr:1;
1011         uint64_t p3_ptout:1;
1012         uint64_t p2_ptout:1;
1013         uint64_t p1_ptout:1;
1014         uint64_t p0_ptout:1;
1015         uint64_t p3_pperr:1;
1016         uint64_t p2_pperr:1;
1017         uint64_t p1_pperr:1;
1018         uint64_t p0_pperr:1;
1019         uint64_t g3_rtout:1;
1020         uint64_t g2_rtout:1;
1021         uint64_t g1_rtout:1;
1022         uint64_t g0_rtout:1;
1023         uint64_t p3_perr:1;
1024         uint64_t p2_perr:1;
1025         uint64_t p1_perr:1;
1026         uint64_t p0_perr:1;
1027         uint64_t p3_rtout:1;
1028         uint64_t p2_rtout:1;
1029         uint64_t p1_rtout:1;
1030         uint64_t p0_rtout:1;
1031         uint64_t i3_overf:1;
1032         uint64_t i2_overf:1;
1033         uint64_t i1_overf:1;
1034         uint64_t i0_overf:1;
1035         uint64_t i3_rtout:1;
1036         uint64_t i2_rtout:1;
1037         uint64_t i1_rtout:1;
1038         uint64_t i0_rtout:1;
1039         uint64_t po3_2sml:1;
1040         uint64_t po2_2sml:1;
1041         uint64_t po1_2sml:1;
1042         uint64_t po0_2sml:1;
1043         uint64_t pci_rsl:1;
1044         uint64_t rml_wto:1;
1045         uint64_t rml_rto:1;
1046 #else
1047         uint64_t rml_rto:1;
1048         uint64_t rml_wto:1;
1049         uint64_t pci_rsl:1;
1050         uint64_t po0_2sml:1;
1051         uint64_t po1_2sml:1;
1052         uint64_t po2_2sml:1;
1053         uint64_t po3_2sml:1;
1054         uint64_t i0_rtout:1;
1055         uint64_t i1_rtout:1;
1056         uint64_t i2_rtout:1;
1057         uint64_t i3_rtout:1;
1058         uint64_t i0_overf:1;
1059         uint64_t i1_overf:1;
1060         uint64_t i2_overf:1;
1061         uint64_t i3_overf:1;
1062         uint64_t p0_rtout:1;
1063         uint64_t p1_rtout:1;
1064         uint64_t p2_rtout:1;
1065         uint64_t p3_rtout:1;
1066         uint64_t p0_perr:1;
1067         uint64_t p1_perr:1;
1068         uint64_t p2_perr:1;
1069         uint64_t p3_perr:1;
1070         uint64_t g0_rtout:1;
1071         uint64_t g1_rtout:1;
1072         uint64_t g2_rtout:1;
1073         uint64_t g3_rtout:1;
1074         uint64_t p0_pperr:1;
1075         uint64_t p1_pperr:1;
1076         uint64_t p2_pperr:1;
1077         uint64_t p3_pperr:1;
1078         uint64_t p0_ptout:1;
1079         uint64_t p1_ptout:1;
1080         uint64_t p2_ptout:1;
1081         uint64_t p3_ptout:1;
1082         uint64_t i0_pperr:1;
1083         uint64_t i1_pperr:1;
1084         uint64_t i2_pperr:1;
1085         uint64_t i3_pperr:1;
1086         uint64_t win_rto:1;
1087         uint64_t p_dperr:1;
1088         uint64_t iobdma:1;
1089         uint64_t reserved_42_63:22;
1090 #endif
1091     } cn38xxp2;
1092 };
1093
1094 union cvmx_npi_int_sum {
1095     uint64_t u64;
1096     struct cvmx_npi_int_sum_s {
1097 #ifdef __BIG_ENDIAN_BITFIELD
1098         uint64_t reserved_62_63:2;
1099         uint64_t q1_a_f:1;
1100         uint64_t q1_s_e:1;
1101         uint64_t pdf_p_f:1;
1102         uint64_t pdf_p_e:1;
1103         uint64_t pcf_p_f:1;
1104         uint64_t pcf_p_e:1;
1105         uint64_t rdx_s_e:1;
1106         uint64_t rwx_s_e:1;
1107         uint64_t pnc_a_f:1;
1108         uint64_t pnc_s_e:1;
1109         uint64_t com_a_f:1;
1110         uint64_t com_s_e:1;
1111         uint64_t q3_a_f:1;
1112         uint64_t q3_s_e:1;
1113         uint64_t q2_a_f:1;
1114         uint64_t q2_s_e:1;
1115         uint64_t pcr_a_f:1;
1116         uint64_t pcr_s_e:1;
1117         uint64_t fcr_a_f:1;
1118         uint64_t fcr_s_e:1;
1119         uint64_t iobdma:1;
1120         uint64_t p_dperr:1;
1121         uint64_t win_rto:1;
1122         uint64_t i3_pperr:1;
1123         uint64_t i2_pperr:1;
1124         uint64_t i1_pperr:1;
1125         uint64_t i0_pperr:1;
1126         uint64_t p3_ptout:1;
1127         uint64_t p2_ptout:1;
1128         uint64_t p1_ptout:1;
1129         uint64_t p0_ptout:1;
1130         uint64_t p3_pperr:1;
1131         uint64_t p2_pperr:1;
1132         uint64_t p1_pperr:1;
1133         uint64_t p0_pperr:1;
1134         uint64_t g3_rtout:1;
1135         uint64_t g2_rtout:1;
1136         uint64_t g1_rtout:1;
1137         uint64_t g0_rtout:1;
1138         uint64_t p3_perr:1;
1139         uint64_t p2_perr:1;
1140         uint64_t p1_perr:1;
1141         uint64_t p0_perr:1;
1142         uint64_t p3_rtout:1;
1143         uint64_t p2_rtout:1;
1144         uint64_t p1_rtout:1;
1145         uint64_t p0_rtout:1;
1146         uint64_t i3_overf:1;
1147         uint64_t i2_overf:1;
1148         uint64_t i1_overf:1;
1149         uint64_t i0_overf:1;
1150         uint64_t i3_rtout:1;
1151         uint64_t i2_rtout:1;
1152         uint64_t i1_rtout:1;
1153         uint64_t i0_rtout:1;
1154         uint64_t po3_2sml:1;
1155         uint64_t po2_2sml:1;
1156         uint64_t po1_2sml:1;
1157         uint64_t po0_2sml:1;
1158         uint64_t pci_rsl:1;
1159         uint64_t rml_wto:1;
1160         uint64_t rml_rto:1;
1161 #else
1162         uint64_t rml_rto:1;
1163         uint64_t rml_wto:1;
1164         uint64_t pci_rsl:1;
1165         uint64_t po0_2sml:1;
1166         uint64_t po1_2sml:1;
1167         uint64_t po2_2sml:1;
1168         uint64_t po3_2sml:1;
1169         uint64_t i0_rtout:1;
1170         uint64_t i1_rtout:1;
1171         uint64_t i2_rtout:1;
1172         uint64_t i3_rtout:1;
1173         uint64_t i0_overf:1;
1174         uint64_t i1_overf:1;
1175         uint64_t i2_overf:1;
1176         uint64_t i3_overf:1;
1177         uint64_t p0_rtout:1;
1178         uint64_t p1_rtout:1;
1179         uint64_t p2_rtout:1;
1180         uint64_t p3_rtout:1;
1181         uint64_t p0_perr:1;
1182         uint64_t p1_perr:1;
1183         uint64_t p2_perr:1;
1184         uint64_t p3_perr:1;
1185         uint64_t g0_rtout:1;
1186         uint64_t g1_rtout:1;
1187         uint64_t g2_rtout:1;
1188         uint64_t g3_rtout:1;
1189         uint64_t p0_pperr:1;
1190         uint64_t p1_pperr:1;
1191         uint64_t p2_pperr:1;
1192         uint64_t p3_pperr:1;
1193         uint64_t p0_ptout:1;
1194         uint64_t p1_ptout:1;
1195         uint64_t p2_ptout:1;
1196         uint64_t p3_ptout:1;
1197         uint64_t i0_pperr:1;
1198         uint64_t i1_pperr:1;
1199         uint64_t i2_pperr:1;
1200         uint64_t i3_pperr:1;
1201         uint64_t win_rto:1;
1202         uint64_t p_dperr:1;
1203         uint64_t iobdma:1;
1204         uint64_t fcr_s_e:1;
1205         uint64_t fcr_a_f:1;
1206         uint64_t pcr_s_e:1;
1207         uint64_t pcr_a_f:1;
1208         uint64_t q2_s_e:1;
1209         uint64_t q2_a_f:1;
1210         uint64_t q3_s_e:1;
1211         uint64_t q3_a_f:1;
1212         uint64_t com_s_e:1;
1213         uint64_t com_a_f:1;
1214         uint64_t pnc_s_e:1;
1215         uint64_t pnc_a_f:1;
1216         uint64_t rwx_s_e:1;
1217         uint64_t rdx_s_e:1;
1218         uint64_t pcf_p_e:1;
1219         uint64_t pcf_p_f:1;
1220         uint64_t pdf_p_e:1;
1221         uint64_t pdf_p_f:1;
1222         uint64_t q1_s_e:1;
1223         uint64_t q1_a_f:1;
1224         uint64_t reserved_62_63:2;
1225 #endif
1226     } s;
1227     struct cvmx_npi_int_sum_cn30xx {
1228 #ifdef __BIG_ENDIAN_BITFIELD
1229         uint64_t reserved_62_63:2;
1230         uint64_t q1_a_f:1;
1231         uint64_t q1_s_e:1;
1232         uint64_t pdf_p_f:1;
1233         uint64_t pdf_p_e:1;
1234         uint64_t pcf_p_f:1;
1235         uint64_t pcf_p_e:1;
1236         uint64_t rdx_s_e:1;
1237         uint64_t rwx_s_e:1;
1238         uint64_t pnc_a_f:1;
1239         uint64_t pnc_s_e:1;
1240         uint64_t com_a_f:1;
1241         uint64_t com_s_e:1;
1242         uint64_t q3_a_f:1;
1243         uint64_t q3_s_e:1;
1244         uint64_t q2_a_f:1;
1245         uint64_t q2_s_e:1;
1246         uint64_t pcr_a_f:1;
1247         uint64_t pcr_s_e:1;
1248         uint64_t fcr_a_f:1;
1249         uint64_t fcr_s_e:1;
1250         uint64_t iobdma:1;
1251         uint64_t p_dperr:1;
1252         uint64_t win_rto:1;
1253         uint64_t reserved_36_38:3;
1254         uint64_t i0_pperr:1;
1255         uint64_t reserved_32_34:3;
1256         uint64_t p0_ptout:1;
1257         uint64_t reserved_28_30:3;
1258         uint64_t p0_pperr:1;
1259         uint64_t reserved_24_26:3;
1260         uint64_t g0_rtout:1;
1261         uint64_t reserved_20_22:3;
1262         uint64_t p0_perr:1;
1263         uint64_t reserved_16_18:3;
1264         uint64_t p0_rtout:1;
1265         uint64_t reserved_12_14:3;
1266         uint64_t i0_overf:1;
1267         uint64_t reserved_8_10:3;
1268         uint64_t i0_rtout:1;
1269         uint64_t reserved_4_6:3;
1270         uint64_t po0_2sml:1;
1271         uint64_t pci_rsl:1;
1272         uint64_t rml_wto:1;
1273         uint64_t rml_rto:1;
1274 #else
1275         uint64_t rml_rto:1;
1276         uint64_t rml_wto:1;
1277         uint64_t pci_rsl:1;
1278         uint64_t po0_2sml:1;
1279         uint64_t reserved_4_6:3;
1280         uint64_t i0_rtout:1;
1281         uint64_t reserved_8_10:3;
1282         uint64_t i0_overf:1;
1283         uint64_t reserved_12_14:3;
1284         uint64_t p0_rtout:1;
1285         uint64_t reserved_16_18:3;
1286         uint64_t p0_perr:1;
1287         uint64_t reserved_20_22:3;
1288         uint64_t g0_rtout:1;
1289         uint64_t reserved_24_26:3;
1290         uint64_t p0_pperr:1;
1291         uint64_t reserved_28_30:3;
1292         uint64_t p0_ptout:1;
1293         uint64_t reserved_32_34:3;
1294         uint64_t i0_pperr:1;
1295         uint64_t reserved_36_38:3;
1296         uint64_t win_rto:1;
1297         uint64_t p_dperr:1;
1298         uint64_t iobdma:1;
1299         uint64_t fcr_s_e:1;
1300         uint64_t fcr_a_f:1;
1301         uint64_t pcr_s_e:1;
1302         uint64_t pcr_a_f:1;
1303         uint64_t q2_s_e:1;
1304         uint64_t q2_a_f:1;
1305         uint64_t q3_s_e:1;
1306         uint64_t q3_a_f:1;
1307         uint64_t com_s_e:1;
1308         uint64_t com_a_f:1;
1309         uint64_t pnc_s_e:1;
1310         uint64_t pnc_a_f:1;
1311         uint64_t rwx_s_e:1;
1312         uint64_t rdx_s_e:1;
1313         uint64_t pcf_p_e:1;
1314         uint64_t pcf_p_f:1;
1315         uint64_t pdf_p_e:1;
1316         uint64_t pdf_p_f:1;
1317         uint64_t q1_s_e:1;
1318         uint64_t q1_a_f:1;
1319         uint64_t reserved_62_63:2;
1320 #endif
1321     } cn30xx;
1322     struct cvmx_npi_int_sum_cn31xx {
1323 #ifdef __BIG_ENDIAN_BITFIELD
1324         uint64_t reserved_62_63:2;
1325         uint64_t q1_a_f:1;
1326         uint64_t q1_s_e:1;
1327         uint64_t pdf_p_f:1;
1328         uint64_t pdf_p_e:1;
1329         uint64_t pcf_p_f:1;
1330         uint64_t pcf_p_e:1;
1331         uint64_t rdx_s_e:1;
1332         uint64_t rwx_s_e:1;
1333         uint64_t pnc_a_f:1;
1334         uint64_t pnc_s_e:1;
1335         uint64_t com_a_f:1;
1336         uint64_t com_s_e:1;
1337         uint64_t q3_a_f:1;
1338         uint64_t q3_s_e:1;
1339         uint64_t q2_a_f:1;
1340         uint64_t q2_s_e:1;
1341         uint64_t pcr_a_f:1;
1342         uint64_t pcr_s_e:1;
1343         uint64_t fcr_a_f:1;
1344         uint64_t fcr_s_e:1;
1345         uint64_t iobdma:1;
1346         uint64_t p_dperr:1;
1347         uint64_t win_rto:1;
1348         uint64_t reserved_37_38:2;
1349         uint64_t i1_pperr:1;
1350         uint64_t i0_pperr:1;
1351         uint64_t reserved_33_34:2;
1352         uint64_t p1_ptout:1;
1353         uint64_t p0_ptout:1;
1354         uint64_t reserved_29_30:2;
1355         uint64_t p1_pperr:1;
1356         uint64_t p0_pperr:1;
1357         uint64_t reserved_25_26:2;
1358         uint64_t g1_rtout:1;
1359         uint64_t g0_rtout:1;
1360         uint64_t reserved_21_22:2;
1361         uint64_t p1_perr:1;
1362         uint64_t p0_perr:1;
1363         uint64_t reserved_17_18:2;
1364         uint64_t p1_rtout:1;
1365         uint64_t p0_rtout:1;
1366         uint64_t reserved_13_14:2;
1367         uint64_t i1_overf:1;
1368         uint64_t i0_overf:1;
1369         uint64_t reserved_9_10:2;
1370         uint64_t i1_rtout:1;
1371         uint64_t i0_rtout:1;
1372         uint64_t reserved_5_6:2;
1373         uint64_t po1_2sml:1;
1374         uint64_t po0_2sml:1;
1375         uint64_t pci_rsl:1;
1376         uint64_t rml_wto:1;
1377         uint64_t rml_rto:1;
1378 #else
1379         uint64_t rml_rto:1;
1380         uint64_t rml_wto:1;
1381         uint64_t pci_rsl:1;
1382         uint64_t po0_2sml:1;
1383         uint64_t po1_2sml:1;
1384         uint64_t reserved_5_6:2;
1385         uint64_t i0_rtout:1;
1386         uint64_t i1_rtout:1;
1387         uint64_t reserved_9_10:2;
1388         uint64_t i0_overf:1;
1389         uint64_t i1_overf:1;
1390         uint64_t reserved_13_14:2;
1391         uint64_t p0_rtout:1;
1392         uint64_t p1_rtout:1;
1393         uint64_t reserved_17_18:2;
1394         uint64_t p0_perr:1;
1395         uint64_t p1_perr:1;
1396         uint64_t reserved_21_22:2;
1397         uint64_t g0_rtout:1;
1398         uint64_t g1_rtout:1;
1399         uint64_t reserved_25_26:2;
1400         uint64_t p0_pperr:1;
1401         uint64_t p1_pperr:1;
1402         uint64_t reserved_29_30:2;
1403         uint64_t p0_ptout:1;
1404         uint64_t p1_ptout:1;
1405         uint64_t reserved_33_34:2;
1406         uint64_t i0_pperr:1;
1407         uint64_t i1_pperr:1;
1408         uint64_t reserved_37_38:2;
1409         uint64_t win_rto:1;
1410         uint64_t p_dperr:1;
1411         uint64_t iobdma:1;
1412         uint64_t fcr_s_e:1;
1413         uint64_t fcr_a_f:1;
1414         uint64_t pcr_s_e:1;
1415         uint64_t pcr_a_f:1;
1416         uint64_t q2_s_e:1;
1417         uint64_t q2_a_f:1;
1418         uint64_t q3_s_e:1;
1419         uint64_t q3_a_f:1;
1420         uint64_t com_s_e:1;
1421         uint64_t com_a_f:1;
1422         uint64_t pnc_s_e:1;
1423         uint64_t pnc_a_f:1;
1424         uint64_t rwx_s_e:1;
1425         uint64_t rdx_s_e:1;
1426         uint64_t pcf_p_e:1;
1427         uint64_t pcf_p_f:1;
1428         uint64_t pdf_p_e:1;
1429         uint64_t pdf_p_f:1;
1430         uint64_t q1_s_e:1;
1431         uint64_t q1_a_f:1;
1432         uint64_t reserved_62_63:2;
1433 #endif
1434     } cn31xx;
1435     struct cvmx_npi_int_sum_cn38xxp2 {
1436 #ifdef __BIG_ENDIAN_BITFIELD
1437         uint64_t reserved_42_63:22;
1438         uint64_t iobdma:1;
1439         uint64_t p_dperr:1;
1440         uint64_t win_rto:1;
1441         uint64_t i3_pperr:1;
1442         uint64_t i2_pperr:1;
1443         uint64_t i1_pperr:1;
1444         uint64_t i0_pperr:1;
1445         uint64_t p3_ptout:1;
1446         uint64_t p2_ptout:1;
1447         uint64_t p1_ptout:1;
1448         uint64_t p0_ptout:1;
1449         uint64_t p3_pperr:1;
1450         uint64_t p2_pperr:1;
1451         uint64_t p1_pperr:1;
1452         uint64_t p0_pperr:1;
1453         uint64_t g3_rtout:1;
1454         uint64_t g2_rtout:1;
1455         uint64_t g1_rtout:1;
1456         uint64_t g0_rtout:1;
1457         uint64_t p3_perr:1;
1458         uint64_t p2_perr:1;
1459         uint64_t p1_perr:1;
1460         uint64_t p0_perr:1;
1461         uint64_t p3_rtout:1;
1462         uint64_t p2_rtout:1;
1463         uint64_t p1_rtout:1;
1464         uint64_t p0_rtout:1;
1465         uint64_t i3_overf:1;
1466         uint64_t i2_overf:1;
1467         uint64_t i1_overf:1;
1468         uint64_t i0_overf:1;
1469         uint64_t i3_rtout:1;
1470         uint64_t i2_rtout:1;
1471         uint64_t i1_rtout:1;
1472         uint64_t i0_rtout:1;
1473         uint64_t po3_2sml:1;
1474         uint64_t po2_2sml:1;
1475         uint64_t po1_2sml:1;
1476         uint64_t po0_2sml:1;
1477         uint64_t pci_rsl:1;
1478         uint64_t rml_wto:1;
1479         uint64_t rml_rto:1;
1480 #else
1481         uint64_t rml_rto:1;
1482         uint64_t rml_wto:1;
1483         uint64_t pci_rsl:1;
1484         uint64_t po0_2sml:1;
1485         uint64_t po1_2sml:1;
1486         uint64_t po2_2sml:1;
1487         uint64_t po3_2sml:1;
1488         uint64_t i0_rtout:1;
1489         uint64_t i1_rtout:1;
1490         uint64_t i2_rtout:1;
1491         uint64_t i3_rtout:1;
1492         uint64_t i0_overf:1;
1493         uint64_t i1_overf:1;
1494         uint64_t i2_overf:1;
1495         uint64_t i3_overf:1;
1496         uint64_t p0_rtout:1;
1497         uint64_t p1_rtout:1;
1498         uint64_t p2_rtout:1;
1499         uint64_t p3_rtout:1;
1500         uint64_t p0_perr:1;
1501         uint64_t p1_perr:1;
1502         uint64_t p2_perr:1;
1503         uint64_t p3_perr:1;
1504         uint64_t g0_rtout:1;
1505         uint64_t g1_rtout:1;
1506         uint64_t g2_rtout:1;
1507         uint64_t g3_rtout:1;
1508         uint64_t p0_pperr:1;
1509         uint64_t p1_pperr:1;
1510         uint64_t p2_pperr:1;
1511         uint64_t p3_pperr:1;
1512         uint64_t p0_ptout:1;
1513         uint64_t p1_ptout:1;
1514         uint64_t p2_ptout:1;
1515         uint64_t p3_ptout:1;
1516         uint64_t i0_pperr:1;
1517         uint64_t i1_pperr:1;
1518         uint64_t i2_pperr:1;
1519         uint64_t i3_pperr:1;
1520         uint64_t win_rto:1;
1521         uint64_t p_dperr:1;
1522         uint64_t iobdma:1;
1523         uint64_t reserved_42_63:22;
1524 #endif
1525     } cn38xxp2;
1526 };
1527
1528 union cvmx_npi_lowp_dbell {
1529     uint64_t u64;
1530     struct cvmx_npi_lowp_dbell_s {
1531 #ifdef __BIG_ENDIAN_BITFIELD
1532         uint64_t reserved_16_63:48;
1533         uint64_t dbell:16;
1534 #else
1535         uint64_t dbell:16;
1536         uint64_t reserved_16_63:48;
1537 #endif
1538     } s;
1539 };
1540
1541 union cvmx_npi_lowp_ibuff_saddr {
1542     uint64_t u64;
1543     struct cvmx_npi_lowp_ibuff_saddr_s {
1544 #ifdef __BIG_ENDIAN_BITFIELD
1545         uint64_t reserved_36_63:28;
1546         uint64_t saddr:36;
1547 #else
1548         uint64_t saddr:36;
1549         uint64_t reserved_36_63:28;
1550 #endif
1551     } s;
1552 };
1553
1554 union cvmx_npi_mem_access_subidx {
1555     uint64_t u64;
1556     struct cvmx_npi_mem_access_subidx_s {
1557 #ifdef __BIG_ENDIAN_BITFIELD
1558         uint64_t reserved_38_63:26;
1559         uint64_t shortl:1;
1560         uint64_t nmerge:1;
1561         uint64_t esr:2;
1562         uint64_t esw:2;
1563         uint64_t nsr:1;
1564         uint64_t nsw:1;
1565         uint64_t ror:1;
1566         uint64_t row:1;
1567         uint64_t ba:28;
1568 #else
1569         uint64_t ba:28;
1570         uint64_t row:1;
1571         uint64_t ror:1;
1572         uint64_t nsw:1;
1573         uint64_t nsr:1;
1574         uint64_t esw:2;
1575         uint64_t esr:2;
1576         uint64_t nmerge:1;
1577         uint64_t shortl:1;
1578         uint64_t reserved_38_63:26;
1579 #endif
1580     } s;
1581     struct cvmx_npi_mem_access_subidx_cn31xx {
1582 #ifdef __BIG_ENDIAN_BITFIELD
1583         uint64_t reserved_36_63:28;
1584         uint64_t esr:2;
1585         uint64_t esw:2;
1586         uint64_t nsr:1;
1587         uint64_t nsw:1;
1588         uint64_t ror:1;
1589         uint64_t row:1;
1590         uint64_t ba:28;
1591 #else
1592         uint64_t ba:28;
1593         uint64_t row:1;
1594         uint64_t ror:1;
1595         uint64_t nsw:1;
1596         uint64_t nsr:1;
1597         uint64_t esw:2;
1598         uint64_t esr:2;
1599         uint64_t reserved_36_63:28;
1600 #endif
1601     } cn31xx;
1602 };
1603
1604 union cvmx_npi_msi_rcv {
1605     uint64_t u64;
1606     struct cvmx_npi_msi_rcv_s {
1607 #ifdef __BIG_ENDIAN_BITFIELD
1608         uint64_t int_vec:64;
1609 #else
1610         uint64_t int_vec:64;
1611 #endif
1612     } s;
1613 };
1614
1615 union cvmx_npi_num_desc_outputx {
1616     uint64_t u64;
1617     struct cvmx_npi_num_desc_outputx_s {
1618 #ifdef __BIG_ENDIAN_BITFIELD
1619         uint64_t reserved_32_63:32;
1620         uint64_t size:32;
1621 #else
1622         uint64_t size:32;
1623         uint64_t reserved_32_63:32;
1624 #endif
1625     } s;
1626 };
1627
1628 union cvmx_npi_output_control {
1629     uint64_t u64;
1630     struct cvmx_npi_output_control_s {
1631 #ifdef __BIG_ENDIAN_BITFIELD
1632         uint64_t reserved_49_63:15;
1633         uint64_t pkt_rr:1;
1634         uint64_t p3_bmode:1;
1635         uint64_t p2_bmode:1;
1636         uint64_t p1_bmode:1;
1637         uint64_t p0_bmode:1;
1638         uint64_t o3_es:2;
1639         uint64_t o3_ns:1;
1640         uint64_t o3_ro:1;
1641         uint64_t o2_es:2;
1642         uint64_t o2_ns:1;
1643         uint64_t o2_ro:1;
1644         uint64_t o1_es:2;
1645         uint64_t o1_ns:1;
1646         uint64_t o1_ro:1;
1647         uint64_t o0_es:2;
1648         uint64_t o0_ns:1;
1649         uint64_t o0_ro:1;
1650         uint64_t o3_csrm:1;
1651         uint64_t o2_csrm:1;
1652         uint64_t o1_csrm:1;
1653         uint64_t o0_csrm:1;
1654         uint64_t reserved_20_23:4;
1655         uint64_t iptr_o3:1;
1656         uint64_t iptr_o2:1;
1657         uint64_t iptr_o1:1;
1658         uint64_t iptr_o0:1;
1659         uint64_t esr_sl3:2;
1660         uint64_t nsr_sl3:1;
1661         uint64_t ror_sl3:1;
1662         uint64_t esr_sl2:2;
1663         uint64_t nsr_sl2:1;
1664         uint64_t ror_sl2:1;
1665         uint64_t esr_sl1:2;
1666         uint64_t nsr_sl1:1;
1667         uint64_t ror_sl1:1;
1668         uint64_t esr_sl0:2;
1669         uint64_t nsr_sl0:1;
1670         uint64_t ror_sl0:1;
1671 #else
1672         uint64_t ror_sl0:1;
1673         uint64_t nsr_sl0:1;
1674         uint64_t esr_sl0:2;
1675         uint64_t ror_sl1:1;
1676         uint64_t nsr_sl1:1;
1677         uint64_t esr_sl1:2;
1678         uint64_t ror_sl2:1;
1679         uint64_t nsr_sl2:1;
1680         uint64_t esr_sl2:2;
1681         uint64_t ror_sl3:1;
1682         uint64_t nsr_sl3:1;
1683         uint64_t esr_sl3:2;
1684         uint64_t iptr_o0:1;
1685         uint64_t iptr_o1:1;
1686         uint64_t iptr_o2:1;
1687         uint64_t iptr_o3:1;
1688         uint64_t reserved_20_23:4;
1689         uint64_t o0_csrm:1;
1690         uint64_t o1_csrm:1;
1691         uint64_t o2_csrm:1;
1692         uint64_t o3_csrm:1;
1693         uint64_t o0_ro:1;
1694         uint64_t o0_ns:1;
1695         uint64_t o0_es:2;
1696         uint64_t o1_ro:1;
1697         uint64_t o1_ns:1;
1698         uint64_t o1_es:2;
1699         uint64_t o2_ro:1;
1700         uint64_t o2_ns:1;
1701         uint64_t o2_es:2;
1702         uint64_t o3_ro:1;
1703         uint64_t o3_ns:1;
1704         uint64_t o3_es:2;
1705         uint64_t p0_bmode:1;
1706         uint64_t p1_bmode:1;
1707         uint64_t p2_bmode:1;
1708         uint64_t p3_bmode:1;
1709         uint64_t pkt_rr:1;
1710         uint64_t reserved_49_63:15;
1711 #endif
1712     } s;
1713     struct cvmx_npi_output_control_cn30xx {
1714 #ifdef __BIG_ENDIAN_BITFIELD
1715         uint64_t reserved_45_63:19;
1716         uint64_t p0_bmode:1;
1717         uint64_t reserved_32_43:12;
1718         uint64_t o0_es:2;
1719         uint64_t o0_ns:1;
1720         uint64_t o0_ro:1;
1721         uint64_t reserved_25_27:3;
1722         uint64_t o0_csrm:1;
1723         uint64_t reserved_17_23:7;
1724         uint64_t iptr_o0:1;
1725         uint64_t reserved_4_15:12;
1726         uint64_t esr_sl0:2;
1727         uint64_t nsr_sl0:1;
1728         uint64_t ror_sl0:1;
1729 #else
1730         uint64_t ror_sl0:1;
1731         uint64_t nsr_sl0:1;
1732         uint64_t esr_sl0:2;
1733         uint64_t reserved_4_15:12;
1734         uint64_t iptr_o0:1;
1735         uint64_t reserved_17_23:7;
1736         uint64_t o0_csrm:1;
1737         uint64_t reserved_25_27:3;
1738         uint64_t o0_ro:1;
1739         uint64_t o0_ns:1;
1740         uint64_t o0_es:2;
1741         uint64_t reserved_32_43:12;
1742         uint64_t p0_bmode:1;
1743         uint64_t reserved_45_63:19;
1744 #endif
1745     } cn30xx;
1746     struct cvmx_npi_output_control_cn31xx {
1747 #ifdef __BIG_ENDIAN_BITFIELD
1748         uint64_t reserved_46_63:18;
1749         uint64_t p1_bmode:1;
1750         uint64_t p0_bmode:1;
1751         uint64_t reserved_36_43:8;
1752         uint64_t o1_es:2;
1753         uint64_t o1_ns:1;
1754         uint64_t o1_ro:1;
1755         uint64_t o0_es:2;
1756         uint64_t o0_ns:1;
1757         uint64_t o0_ro:1;
1758         uint64_t reserved_26_27:2;
1759         uint64_t o1_csrm:1;
1760         uint64_t o0_csrm:1;
1761         uint64_t reserved_18_23:6;
1762         uint64_t iptr_o1:1;
1763         uint64_t iptr_o0:1;
1764         uint64_t reserved_8_15:8;
1765         uint64_t esr_sl1:2;
1766         uint64_t nsr_sl1:1;
1767         uint64_t ror_sl1:1;
1768         uint64_t esr_sl0:2;
1769         uint64_t nsr_sl0:1;
1770         uint64_t ror_sl0:1;
1771 #else
1772         uint64_t ror_sl0:1;
1773         uint64_t nsr_sl0:1;
1774         uint64_t esr_sl0:2;
1775         uint64_t ror_sl1:1;
1776         uint64_t nsr_sl1:1;
1777         uint64_t esr_sl1:2;
1778         uint64_t reserved_8_15:8;
1779         uint64_t iptr_o0:1;
1780         uint64_t iptr_o1:1;
1781         uint64_t reserved_18_23:6;
1782         uint64_t o0_csrm:1;
1783         uint64_t o1_csrm:1;
1784         uint64_t reserved_26_27:2;
1785         uint64_t o0_ro:1;
1786         uint64_t o0_ns:1;
1787         uint64_t o0_es:2;
1788         uint64_t o1_ro:1;
1789         uint64_t o1_ns:1;
1790         uint64_t o1_es:2;
1791         uint64_t reserved_36_43:8;
1792         uint64_t p0_bmode:1;
1793         uint64_t p1_bmode:1;
1794         uint64_t reserved_46_63:18;
1795 #endif
1796     } cn31xx;
1797     struct cvmx_npi_output_control_cn38xxp2 {
1798 #ifdef __BIG_ENDIAN_BITFIELD
1799         uint64_t reserved_48_63:16;
1800         uint64_t p3_bmode:1;
1801         uint64_t p2_bmode:1;
1802         uint64_t p1_bmode:1;
1803         uint64_t p0_bmode:1;
1804         uint64_t o3_es:2;
1805         uint64_t o3_ns:1;
1806         uint64_t o3_ro:1;
1807         uint64_t o2_es:2;
1808         uint64_t o2_ns:1;
1809         uint64_t o2_ro:1;
1810         uint64_t o1_es:2;
1811         uint64_t o1_ns:1;
1812         uint64_t o1_ro:1;
1813         uint64_t o0_es:2;
1814         uint64_t o0_ns:1;
1815         uint64_t o0_ro:1;
1816         uint64_t o3_csrm:1;
1817         uint64_t o2_csrm:1;
1818         uint64_t o1_csrm:1;
1819         uint64_t o0_csrm:1;
1820         uint64_t reserved_20_23:4;
1821         uint64_t iptr_o3:1;
1822         uint64_t iptr_o2:1;
1823         uint64_t iptr_o1:1;
1824         uint64_t iptr_o0:1;
1825         uint64_t esr_sl3:2;
1826         uint64_t nsr_sl3:1;
1827         uint64_t ror_sl3:1;
1828         uint64_t esr_sl2:2;
1829         uint64_t nsr_sl2:1;
1830         uint64_t ror_sl2:1;
1831         uint64_t esr_sl1:2;
1832         uint64_t nsr_sl1:1;
1833         uint64_t ror_sl1:1;
1834         uint64_t esr_sl0:2;
1835         uint64_t nsr_sl0:1;
1836         uint64_t ror_sl0:1;
1837 #else
1838         uint64_t ror_sl0:1;
1839         uint64_t nsr_sl0:1;
1840         uint64_t esr_sl0:2;
1841         uint64_t ror_sl1:1;
1842         uint64_t nsr_sl1:1;
1843         uint64_t esr_sl1:2;
1844         uint64_t ror_sl2:1;
1845         uint64_t nsr_sl2:1;
1846         uint64_t esr_sl2:2;
1847         uint64_t ror_sl3:1;
1848         uint64_t nsr_sl3:1;
1849         uint64_t esr_sl3:2;
1850         uint64_t iptr_o0:1;
1851         uint64_t iptr_o1:1;
1852         uint64_t iptr_o2:1;
1853         uint64_t iptr_o3:1;
1854         uint64_t reserved_20_23:4;
1855         uint64_t o0_csrm:1;
1856         uint64_t o1_csrm:1;
1857         uint64_t o2_csrm:1;
1858         uint64_t o3_csrm:1;
1859         uint64_t o0_ro:1;
1860         uint64_t o0_ns:1;
1861         uint64_t o0_es:2;
1862         uint64_t o1_ro:1;
1863         uint64_t o1_ns:1;
1864         uint64_t o1_es:2;
1865         uint64_t o2_ro:1;
1866         uint64_t o2_ns:1;
1867         uint64_t o2_es:2;
1868         uint64_t o3_ro:1;
1869         uint64_t o3_ns:1;
1870         uint64_t o3_es:2;
1871         uint64_t p0_bmode:1;
1872         uint64_t p1_bmode:1;
1873         uint64_t p2_bmode:1;
1874         uint64_t p3_bmode:1;
1875         uint64_t reserved_48_63:16;
1876 #endif
1877     } cn38xxp2;
1878     struct cvmx_npi_output_control_cn50xx {
1879 #ifdef __BIG_ENDIAN_BITFIELD
1880         uint64_t reserved_49_63:15;
1881         uint64_t pkt_rr:1;
1882         uint64_t reserved_46_47:2;
1883         uint64_t p1_bmode:1;
1884         uint64_t p0_bmode:1;
1885         uint64_t reserved_36_43:8;
1886         uint64_t o1_es:2;
1887         uint64_t o1_ns:1;
1888         uint64_t o1_ro:1;
1889         uint64_t o0_es:2;
1890         uint64_t o0_ns:1;
1891         uint64_t o0_ro:1;
1892         uint64_t reserved_26_27:2;
1893         uint64_t o1_csrm:1;
1894         uint64_t o0_csrm:1;
1895         uint64_t reserved_18_23:6;
1896         uint64_t iptr_o1:1;
1897         uint64_t iptr_o0:1;
1898         uint64_t reserved_8_15:8;
1899         uint64_t esr_sl1:2;
1900         uint64_t nsr_sl1:1;
1901         uint64_t ror_sl1:1;
1902         uint64_t esr_sl0:2;
1903         uint64_t nsr_sl0:1;
1904         uint64_t ror_sl0:1;
1905 #else
1906         uint64_t ror_sl0:1;
1907         uint64_t nsr_sl0:1;
1908         uint64_t esr_sl0:2;
1909         uint64_t ror_sl1:1;
1910         uint64_t nsr_sl1:1;
1911         uint64_t esr_sl1:2;
1912         uint64_t reserved_8_15:8;
1913         uint64_t iptr_o0:1;
1914         uint64_t iptr_o1:1;
1915         uint64_t reserved_18_23:6;
1916         uint64_t o0_csrm:1;
1917         uint64_t o1_csrm:1;
1918         uint64_t reserved_26_27:2;
1919         uint64_t o0_ro:1;
1920         uint64_t o0_ns:1;
1921         uint64_t o0_es:2;
1922         uint64_t o1_ro:1;
1923         uint64_t o1_ns:1;
1924         uint64_t o1_es:2;
1925         uint64_t reserved_36_43:8;
1926         uint64_t p0_bmode:1;
1927         uint64_t p1_bmode:1;
1928         uint64_t reserved_46_47:2;
1929         uint64_t pkt_rr:1;
1930         uint64_t reserved_49_63:15;
1931 #endif
1932     } cn50xx;
1933 };
1934
1935 union cvmx_npi_px_dbpair_addr {
1936     uint64_t u64;
1937     struct cvmx_npi_px_dbpair_addr_s {
1938 #ifdef __BIG_ENDIAN_BITFIELD
1939         uint64_t reserved_63_63:1;
1940         uint64_t state:2;
1941         uint64_t naddr:61;
1942 #else
1943         uint64_t naddr:61;
1944         uint64_t state:2;
1945         uint64_t reserved_63_63:1;
1946 #endif
1947     } s;
1948 };
1949
1950 union cvmx_npi_px_instr_addr {
1951     uint64_t u64;
1952     struct cvmx_npi_px_instr_addr_s {
1953 #ifdef __BIG_ENDIAN_BITFIELD
1954         uint64_t state:3;
1955         uint64_t naddr:61;
1956 #else
1957         uint64_t naddr:61;
1958         uint64_t state:3;
1959 #endif
1960     } s;
1961 };
1962
1963 union cvmx_npi_px_instr_cnts {
1964     uint64_t u64;
1965     struct cvmx_npi_px_instr_cnts_s {
1966 #ifdef __BIG_ENDIAN_BITFIELD
1967         uint64_t reserved_38_63:26;
1968         uint64_t fcnt:6;
1969         uint64_t avail:32;
1970 #else
1971         uint64_t avail:32;
1972         uint64_t fcnt:6;
1973         uint64_t reserved_38_63:26;
1974 #endif
1975     } s;
1976 };
1977
1978 union cvmx_npi_px_pair_cnts {
1979     uint64_t u64;
1980     struct cvmx_npi_px_pair_cnts_s {
1981 #ifdef __BIG_ENDIAN_BITFIELD
1982         uint64_t reserved_37_63:27;
1983         uint64_t fcnt:5;
1984         uint64_t avail:32;
1985 #else
1986         uint64_t avail:32;
1987         uint64_t fcnt:5;
1988         uint64_t reserved_37_63:27;
1989 #endif
1990     } s;
1991 };
1992
1993 union cvmx_npi_pci_burst_size {
1994     uint64_t u64;
1995     struct cvmx_npi_pci_burst_size_s {
1996 #ifdef __BIG_ENDIAN_BITFIELD
1997         uint64_t reserved_14_63:50;
1998         uint64_t wr_brst:7;
1999         uint64_t rd_brst:7;
2000 #else
2001         uint64_t rd_brst:7;
2002         uint64_t wr_brst:7;
2003         uint64_t reserved_14_63:50;
2004 #endif
2005     } s;
2006 };
2007
2008 union cvmx_npi_pci_int_arb_cfg {
2009     uint64_t u64;
2010     struct cvmx_npi_pci_int_arb_cfg_s {
2011 #ifdef __BIG_ENDIAN_BITFIELD
2012         uint64_t reserved_13_63:51;
2013         uint64_t hostmode:1;
2014         uint64_t pci_ovr:4;
2015         uint64_t reserved_5_7:3;
2016         uint64_t en:1;
2017         uint64_t park_mod:1;
2018         uint64_t park_dev:3;
2019 #else
2020         uint64_t park_dev:3;
2021         uint64_t park_mod:1;
2022         uint64_t en:1;
2023         uint64_t reserved_5_7:3;
2024         uint64_t pci_ovr:4;
2025         uint64_t hostmode:1;
2026         uint64_t reserved_13_63:51;
2027 #endif
2028     } s;
2029     struct cvmx_npi_pci_int_arb_cfg_cn30xx {
2030 #ifdef __BIG_ENDIAN_BITFIELD
2031         uint64_t reserved_5_63:59;
2032         uint64_t en:1;
2033         uint64_t park_mod:1;
2034         uint64_t park_dev:3;
2035 #else
2036         uint64_t park_dev:3;
2037         uint64_t park_mod:1;
2038         uint64_t en:1;
2039         uint64_t reserved_5_63:59;
2040 #endif
2041     } cn30xx;
2042 };
2043
2044 union cvmx_npi_pci_read_cmd {
2045     uint64_t u64;
2046     struct cvmx_npi_pci_read_cmd_s {
2047 #ifdef __BIG_ENDIAN_BITFIELD
2048         uint64_t reserved_11_63:53;
2049         uint64_t cmd_size:11;
2050 #else
2051         uint64_t cmd_size:11;
2052         uint64_t reserved_11_63:53;
2053 #endif
2054     } s;
2055 };
2056
2057 union cvmx_npi_port32_instr_hdr {
2058     uint64_t u64;
2059     struct cvmx_npi_port32_instr_hdr_s {
2060 #ifdef __BIG_ENDIAN_BITFIELD
2061         uint64_t reserved_44_63:20;
2062         uint64_t pbp:1;
2063         uint64_t rsv_f:5;
2064         uint64_t rparmode:2;
2065         uint64_t rsv_e:1;
2066         uint64_t rskp_len:7;
2067         uint64_t rsv_d:6;
2068         uint64_t use_ihdr:1;
2069         uint64_t rsv_c:5;
2070         uint64_t par_mode:2;
2071         uint64_t rsv_b:1;
2072         uint64_t skp_len:7;
2073         uint64_t rsv_a:6;
2074 #else
2075         uint64_t rsv_a:6;
2076         uint64_t skp_len:7;
2077         uint64_t rsv_b:1;
2078         uint64_t par_mode:2;
2079         uint64_t rsv_c:5;
2080         uint64_t use_ihdr:1;
2081         uint64_t rsv_d:6;
2082         uint64_t rskp_len:7;
2083         uint64_t rsv_e:1;
2084         uint64_t rparmode:2;
2085         uint64_t rsv_f:5;
2086         uint64_t pbp:1;
2087         uint64_t reserved_44_63:20;
2088 #endif
2089     } s;
2090 };
2091
2092 union cvmx_npi_port33_instr_hdr {
2093     uint64_t u64;
2094     struct cvmx_npi_port33_instr_hdr_s {
2095 #ifdef __BIG_ENDIAN_BITFIELD
2096         uint64_t reserved_44_63:20;
2097         uint64_t pbp:1;
2098         uint64_t rsv_f:5;
2099         uint64_t rparmode:2;
2100         uint64_t rsv_e:1;
2101         uint64_t rskp_len:7;
2102         uint64_t rsv_d:6;
2103         uint64_t use_ihdr:1;
2104         uint64_t rsv_c:5;
2105         uint64_t par_mode:2;
2106         uint64_t rsv_b:1;
2107         uint64_t skp_len:7;
2108         uint64_t rsv_a:6;
2109 #else
2110         uint64_t rsv_a:6;
2111         uint64_t skp_len:7;
2112         uint64_t rsv_b:1;
2113         uint64_t par_mode:2;
2114         uint64_t rsv_c:5;
2115         uint64_t use_ihdr:1;
2116         uint64_t rsv_d:6;
2117         uint64_t rskp_len:7;
2118         uint64_t rsv_e:1;
2119         uint64_t rparmode:2;
2120         uint64_t rsv_f:5;
2121         uint64_t pbp:1;
2122         uint64_t reserved_44_63:20;
2123 #endif
2124     } s;
2125 };
2126
2127 union cvmx_npi_port34_instr_hdr {
2128     uint64_t u64;
2129     struct cvmx_npi_port34_instr_hdr_s {
2130 #ifdef __BIG_ENDIAN_BITFIELD
2131         uint64_t reserved_44_63:20;
2132         uint64_t pbp:1;
2133         uint64_t rsv_f:5;
2134         uint64_t rparmode:2;
2135         uint64_t rsv_e:1;
2136         uint64_t rskp_len:7;
2137         uint64_t rsv_d:6;
2138         uint64_t use_ihdr:1;
2139         uint64_t rsv_c:5;
2140         uint64_t par_mode:2;
2141         uint64_t rsv_b:1;
2142         uint64_t skp_len:7;
2143         uint64_t rsv_a:6;
2144 #else
2145         uint64_t rsv_a:6;
2146         uint64_t skp_len:7;
2147         uint64_t rsv_b:1;
2148         uint64_t par_mode:2;
2149         uint64_t rsv_c:5;
2150         uint64_t use_ihdr:1;
2151         uint64_t rsv_d:6;
2152         uint64_t rskp_len:7;
2153         uint64_t rsv_e:1;
2154         uint64_t rparmode:2;
2155         uint64_t rsv_f:5;
2156         uint64_t pbp:1;
2157         uint64_t reserved_44_63:20;
2158 #endif
2159     } s;
2160 };
2161
2162 union cvmx_npi_port35_instr_hdr {
2163     uint64_t u64;
2164     struct cvmx_npi_port35_instr_hdr_s {
2165 #ifdef __BIG_ENDIAN_BITFIELD
2166         uint64_t reserved_44_63:20;
2167         uint64_t pbp:1;
2168         uint64_t rsv_f:5;
2169         uint64_t rparmode:2;
2170         uint64_t rsv_e:1;
2171         uint64_t rskp_len:7;
2172         uint64_t rsv_d:6;
2173         uint64_t use_ihdr:1;
2174         uint64_t rsv_c:5;
2175         uint64_t par_mode:2;
2176         uint64_t rsv_b:1;
2177         uint64_t skp_len:7;
2178         uint64_t rsv_a:6;
2179 #else
2180         uint64_t rsv_a:6;
2181         uint64_t skp_len:7;
2182         uint64_t rsv_b:1;
2183         uint64_t par_mode:2;
2184         uint64_t rsv_c:5;
2185         uint64_t use_ihdr:1;
2186         uint64_t rsv_d:6;
2187         uint64_t rskp_len:7;
2188         uint64_t rsv_e:1;
2189         uint64_t rparmode:2;
2190         uint64_t rsv_f:5;
2191         uint64_t pbp:1;
2192         uint64_t reserved_44_63:20;
2193 #endif
2194     } s;
2195 };
2196
2197 union cvmx_npi_port_bp_control {
2198     uint64_t u64;
2199     struct cvmx_npi_port_bp_control_s {
2200 #ifdef __BIG_ENDIAN_BITFIELD
2201         uint64_t reserved_8_63:56;
2202         uint64_t bp_on:4;
2203         uint64_t enb:4;
2204 #else
2205         uint64_t enb:4;
2206         uint64_t bp_on:4;
2207         uint64_t reserved_8_63:56;
2208 #endif
2209     } s;
2210 };
2211
2212 union cvmx_npi_rsl_int_blocks {
2213     uint64_t u64;
2214     struct cvmx_npi_rsl_int_blocks_s {
2215 #ifdef __BIG_ENDIAN_BITFIELD
2216         uint64_t reserved_32_63:32;
2217         uint64_t rint_31:1;
2218         uint64_t iob:1;
2219         uint64_t reserved_28_29:2;
2220         uint64_t rint_27:1;
2221         uint64_t rint_26:1;
2222         uint64_t rint_25:1;
2223         uint64_t rint_24:1;
2224         uint64_t asx1:1;
2225         uint64_t asx0:1;
2226         uint64_t rint_21:1;
2227         uint64_t pip:1;
2228         uint64_t spx1:1;
2229         uint64_t spx0:1;
2230         uint64_t lmc:1;
2231         uint64_t l2c:1;
2232         uint64_t rint_15:1;
2233         uint64_t reserved_13_14:2;
2234         uint64_t pow:1;
2235         uint64_t tim:1;
2236         uint64_t pko:1;
2237         uint64_t ipd:1;
2238         uint64_t rint_8:1;
2239         uint64_t zip:1;
2240         uint64_t dfa:1;
2241         uint64_t fpa:1;
2242         uint64_t key:1;
2243         uint64_t npi:1;
2244         uint64_t gmx1:1;
2245         uint64_t gmx0:1;
2246         uint64_t mio:1;
2247 #else
2248         uint64_t mio:1;
2249         uint64_t gmx0:1;
2250         uint64_t gmx1:1;
2251         uint64_t npi:1;
2252         uint64_t key:1;
2253         uint64_t fpa:1;
2254         uint64_t dfa:1;
2255         uint64_t zip:1;
2256         uint64_t rint_8:1;
2257         uint64_t ipd:1;
2258         uint64_t pko:1;
2259         uint64_t tim:1;
2260         uint64_t pow:1;
2261         uint64_t reserved_13_14:2;
2262         uint64_t rint_15:1;
2263         uint64_t l2c:1;
2264         uint64_t lmc:1;
2265         uint64_t spx0:1;
2266         uint64_t spx1:1;
2267         uint64_t pip:1;
2268         uint64_t rint_21:1;
2269         uint64_t asx0:1;
2270         uint64_t asx1:1;
2271         uint64_t rint_24:1;
2272         uint64_t rint_25:1;
2273         uint64_t rint_26:1;
2274         uint64_t rint_27:1;
2275         uint64_t reserved_28_29:2;
2276         uint64_t iob:1;
2277         uint64_t rint_31:1;
2278         uint64_t reserved_32_63:32;
2279 #endif
2280     } s;
2281     struct cvmx_npi_rsl_int_blocks_cn30xx {
2282 #ifdef __BIG_ENDIAN_BITFIELD
2283         uint64_t reserved_32_63:32;
2284         uint64_t rint_31:1;
2285         uint64_t iob:1;
2286         uint64_t rint_29:1;
2287         uint64_t rint_28:1;
2288         uint64_t rint_27:1;
2289         uint64_t rint_26:1;
2290         uint64_t rint_25:1;
2291         uint64_t rint_24:1;
2292         uint64_t asx1:1;
2293         uint64_t asx0:1;
2294         uint64_t rint_21:1;
2295         uint64_t pip:1;
2296         uint64_t spx1:1;
2297         uint64_t spx0:1;
2298         uint64_t lmc:1;
2299         uint64_t l2c:1;
2300         uint64_t rint_15:1;
2301         uint64_t rint_14:1;
2302         uint64_t usb:1;
2303         uint64_t pow:1;
2304         uint64_t tim:1;
2305         uint64_t pko:1;
2306         uint64_t ipd:1;
2307         uint64_t rint_8:1;
2308         uint64_t zip:1;
2309         uint64_t dfa:1;
2310         uint64_t fpa:1;
2311         uint64_t key:1;
2312         uint64_t npi:1;
2313         uint64_t gmx1:1;
2314         uint64_t gmx0:1;
2315         uint64_t mio:1;
2316 #else
2317         uint64_t mio:1;
2318         uint64_t gmx0:1;
2319         uint64_t gmx1:1;
2320         uint64_t npi:1;
2321         uint64_t key:1;
2322         uint64_t fpa:1;
2323         uint64_t dfa:1;
2324         uint64_t zip:1;
2325         uint64_t rint_8:1;
2326         uint64_t ipd:1;
2327         uint64_t pko:1;
2328         uint64_t tim:1;
2329         uint64_t pow:1;
2330         uint64_t usb:1;
2331         uint64_t rint_14:1;
2332         uint64_t rint_15:1;
2333         uint64_t l2c:1;
2334         uint64_t lmc:1;
2335         uint64_t spx0:1;
2336         uint64_t spx1:1;
2337         uint64_t pip:1;
2338         uint64_t rint_21:1;
2339         uint64_t asx0:1;
2340         uint64_t asx1:1;
2341         uint64_t rint_24:1;
2342         uint64_t rint_25:1;
2343         uint64_t rint_26:1;
2344         uint64_t rint_27:1;
2345         uint64_t rint_28:1;
2346         uint64_t rint_29:1;
2347         uint64_t iob:1;
2348         uint64_t rint_31:1;
2349         uint64_t reserved_32_63:32;
2350 #endif
2351     } cn30xx;
2352     struct cvmx_npi_rsl_int_blocks_cn38xx {
2353 #ifdef __BIG_ENDIAN_BITFIELD
2354         uint64_t reserved_32_63:32;
2355         uint64_t rint_31:1;
2356         uint64_t iob:1;
2357         uint64_t rint_29:1;
2358         uint64_t rint_28:1;
2359         uint64_t rint_27:1;
2360         uint64_t rint_26:1;
2361         uint64_t rint_25:1;
2362         uint64_t rint_24:1;
2363         uint64_t asx1:1;
2364         uint64_t asx0:1;
2365         uint64_t rint_21:1;
2366         uint64_t pip:1;
2367         uint64_t spx1:1;
2368         uint64_t spx0:1;
2369         uint64_t lmc:1;
2370         uint64_t l2c:1;
2371         uint64_t rint_15:1;
2372         uint64_t rint_14:1;
2373         uint64_t rint_13:1;
2374         uint64_t pow:1;
2375         uint64_t tim:1;
2376         uint64_t pko:1;
2377         uint64_t ipd:1;
2378         uint64_t rint_8:1;
2379         uint64_t zip:1;
2380         uint64_t dfa:1;
2381         uint64_t fpa:1;
2382         uint64_t key:1;
2383         uint64_t npi:1;
2384         uint64_t gmx1:1;
2385         uint64_t gmx0:1;
2386         uint64_t mio:1;
2387 #else
2388         uint64_t mio:1;
2389         uint64_t gmx0:1;
2390         uint64_t gmx1:1;
2391         uint64_t npi:1;
2392         uint64_t key:1;
2393         uint64_t fpa:1;
2394         uint64_t dfa:1;
2395         uint64_t zip:1;
2396         uint64_t rint_8:1;
2397         uint64_t ipd:1;
2398         uint64_t pko:1;
2399         uint64_t tim:1;
2400         uint64_t pow:1;
2401         uint64_t rint_13:1;
2402         uint64_t rint_14:1;
2403         uint64_t rint_15:1;
2404         uint64_t l2c:1;
2405         uint64_t lmc:1;
2406         uint64_t spx0:1;
2407         uint64_t spx1:1;
2408         uint64_t pip:1;
2409         uint64_t rint_21:1;
2410         uint64_t asx0:1;
2411         uint64_t asx1:1;
2412         uint64_t rint_24:1;
2413         uint64_t rint_25:1;
2414         uint64_t rint_26:1;
2415         uint64_t rint_27:1;
2416         uint64_t rint_28:1;
2417         uint64_t rint_29:1;
2418         uint64_t iob:1;
2419         uint64_t rint_31:1;
2420         uint64_t reserved_32_63:32;
2421 #endif
2422     } cn38xx;
2423     struct cvmx_npi_rsl_int_blocks_cn50xx {
2424 #ifdef __BIG_ENDIAN_BITFIELD
2425         uint64_t reserved_31_63:33;
2426         uint64_t iob:1;
2427         uint64_t lmc1:1;
2428         uint64_t agl:1;
2429         uint64_t reserved_24_27:4;
2430         uint64_t asx1:1;
2431         uint64_t asx0:1;
2432         uint64_t reserved_21_21:1;
2433         uint64_t pip:1;
2434         uint64_t spx1:1;
2435         uint64_t spx0:1;
2436         uint64_t lmc:1;
2437         uint64_t l2c:1;
2438         uint64_t reserved_15_15:1;
2439         uint64_t rad:1;
2440         uint64_t usb:1;
2441         uint64_t pow:1;
2442         uint64_t tim:1;
2443         uint64_t pko:1;
2444         uint64_t ipd:1;
2445         uint64_t reserved_8_8:1;
2446         uint64_t zip:1;
2447         uint64_t dfa:1;
2448         uint64_t fpa:1;
2449         uint64_t key:1;
2450         uint64_t npi:1;
2451         uint64_t gmx1:1;
2452         uint64_t gmx0:1;
2453         uint64_t mio:1;
2454 #else
2455         uint64_t mio:1;
2456         uint64_t gmx0:1;
2457         uint64_t gmx1:1;
2458         uint64_t npi:1;
2459         uint64_t key:1;
2460         uint64_t fpa:1;
2461         uint64_t dfa:1;
2462         uint64_t zip:1;
2463         uint64_t reserved_8_8:1;
2464         uint64_t ipd:1;
2465         uint64_t pko:1;
2466         uint64_t tim:1;
2467         uint64_t pow:1;
2468         uint64_t usb:1;
2469         uint64_t rad:1;
2470         uint64_t reserved_15_15:1;
2471         uint64_t l2c:1;
2472         uint64_t lmc:1;
2473         uint64_t spx0:1;
2474         uint64_t spx1:1;
2475         uint64_t pip:1;
2476         uint64_t reserved_21_21:1;
2477         uint64_t asx0:1;
2478         uint64_t asx1:1;
2479         uint64_t reserved_24_27:4;
2480         uint64_t agl:1;
2481         uint64_t lmc1:1;
2482         uint64_t iob:1;
2483         uint64_t reserved_31_63:33;
2484 #endif
2485     } cn50xx;
2486 };
2487
2488 union cvmx_npi_size_inputx {
2489     uint64_t u64;
2490     struct cvmx_npi_size_inputx_s {
2491 #ifdef __BIG_ENDIAN_BITFIELD
2492         uint64_t reserved_32_63:32;
2493         uint64_t size:32;
2494 #else
2495         uint64_t size:32;
2496         uint64_t reserved_32_63:32;
2497 #endif
2498     } s;
2499 };
2500
2501 union cvmx_npi_win_read_to {
2502     uint64_t u64;
2503     struct cvmx_npi_win_read_to_s {
2504 #ifdef __BIG_ENDIAN_BITFIELD
2505         uint64_t reserved_32_63:32;
2506         uint64_t time:32;
2507 #else
2508         uint64_t time:32;
2509         uint64_t reserved_32_63:32;
2510 #endif
2511     } s;
2512 };
2513
2514 #endif