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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_MIXX_DEFS_H__
0029 #define __CVMX_MIXX_DEFS_H__
0030 
0031 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
0032 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
0033 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
0034 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
0035 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
0036 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
0037 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
0038 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
0039 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
0040 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
0041 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
0042 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
0043 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
0044 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
0045 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
0046 
0047 union cvmx_mixx_bist {
0048     uint64_t u64;
0049     struct cvmx_mixx_bist_s {
0050 #ifdef __BIG_ENDIAN_BITFIELD
0051         uint64_t reserved_6_63:58;
0052         uint64_t opfdat:1;
0053         uint64_t mrgdat:1;
0054         uint64_t mrqdat:1;
0055         uint64_t ipfdat:1;
0056         uint64_t irfdat:1;
0057         uint64_t orfdat:1;
0058 #else
0059         uint64_t orfdat:1;
0060         uint64_t irfdat:1;
0061         uint64_t ipfdat:1;
0062         uint64_t mrqdat:1;
0063         uint64_t mrgdat:1;
0064         uint64_t opfdat:1;
0065         uint64_t reserved_6_63:58;
0066 #endif
0067     } s;
0068     struct cvmx_mixx_bist_cn52xx {
0069 #ifdef __BIG_ENDIAN_BITFIELD
0070         uint64_t reserved_4_63:60;
0071         uint64_t mrqdat:1;
0072         uint64_t ipfdat:1;
0073         uint64_t irfdat:1;
0074         uint64_t orfdat:1;
0075 #else
0076         uint64_t orfdat:1;
0077         uint64_t irfdat:1;
0078         uint64_t ipfdat:1;
0079         uint64_t mrqdat:1;
0080         uint64_t reserved_4_63:60;
0081 #endif
0082     } cn52xx;
0083 };
0084 
0085 union cvmx_mixx_ctl {
0086     uint64_t u64;
0087     struct cvmx_mixx_ctl_s {
0088 #ifdef __BIG_ENDIAN_BITFIELD
0089         uint64_t reserved_12_63:52;
0090         uint64_t ts_thresh:4;
0091         uint64_t crc_strip:1;
0092         uint64_t busy:1;
0093         uint64_t en:1;
0094         uint64_t reset:1;
0095         uint64_t lendian:1;
0096         uint64_t nbtarb:1;
0097         uint64_t mrq_hwm:2;
0098 #else
0099         uint64_t mrq_hwm:2;
0100         uint64_t nbtarb:1;
0101         uint64_t lendian:1;
0102         uint64_t reset:1;
0103         uint64_t en:1;
0104         uint64_t busy:1;
0105         uint64_t crc_strip:1;
0106         uint64_t ts_thresh:4;
0107         uint64_t reserved_12_63:52;
0108 #endif
0109     } s;
0110     struct cvmx_mixx_ctl_cn52xx {
0111 #ifdef __BIG_ENDIAN_BITFIELD
0112         uint64_t reserved_8_63:56;
0113         uint64_t crc_strip:1;
0114         uint64_t busy:1;
0115         uint64_t en:1;
0116         uint64_t reset:1;
0117         uint64_t lendian:1;
0118         uint64_t nbtarb:1;
0119         uint64_t mrq_hwm:2;
0120 #else
0121         uint64_t mrq_hwm:2;
0122         uint64_t nbtarb:1;
0123         uint64_t lendian:1;
0124         uint64_t reset:1;
0125         uint64_t en:1;
0126         uint64_t busy:1;
0127         uint64_t crc_strip:1;
0128         uint64_t reserved_8_63:56;
0129 #endif
0130     } cn52xx;
0131 };
0132 
0133 union cvmx_mixx_intena {
0134     uint64_t u64;
0135     struct cvmx_mixx_intena_s {
0136 #ifdef __BIG_ENDIAN_BITFIELD
0137         uint64_t reserved_8_63:56;
0138         uint64_t tsena:1;
0139         uint64_t orunena:1;
0140         uint64_t irunena:1;
0141         uint64_t data_drpena:1;
0142         uint64_t ithena:1;
0143         uint64_t othena:1;
0144         uint64_t ivfena:1;
0145         uint64_t ovfena:1;
0146 #else
0147         uint64_t ovfena:1;
0148         uint64_t ivfena:1;
0149         uint64_t othena:1;
0150         uint64_t ithena:1;
0151         uint64_t data_drpena:1;
0152         uint64_t irunena:1;
0153         uint64_t orunena:1;
0154         uint64_t tsena:1;
0155         uint64_t reserved_8_63:56;
0156 #endif
0157     } s;
0158     struct cvmx_mixx_intena_cn52xx {
0159 #ifdef __BIG_ENDIAN_BITFIELD
0160         uint64_t reserved_7_63:57;
0161         uint64_t orunena:1;
0162         uint64_t irunena:1;
0163         uint64_t data_drpena:1;
0164         uint64_t ithena:1;
0165         uint64_t othena:1;
0166         uint64_t ivfena:1;
0167         uint64_t ovfena:1;
0168 #else
0169         uint64_t ovfena:1;
0170         uint64_t ivfena:1;
0171         uint64_t othena:1;
0172         uint64_t ithena:1;
0173         uint64_t data_drpena:1;
0174         uint64_t irunena:1;
0175         uint64_t orunena:1;
0176         uint64_t reserved_7_63:57;
0177 #endif
0178     } cn52xx;
0179 };
0180 
0181 union cvmx_mixx_ircnt {
0182     uint64_t u64;
0183     struct cvmx_mixx_ircnt_s {
0184 #ifdef __BIG_ENDIAN_BITFIELD
0185         uint64_t reserved_20_63:44;
0186         uint64_t ircnt:20;
0187 #else
0188         uint64_t ircnt:20;
0189         uint64_t reserved_20_63:44;
0190 #endif
0191     } s;
0192 };
0193 
0194 union cvmx_mixx_irhwm {
0195     uint64_t u64;
0196     struct cvmx_mixx_irhwm_s {
0197 #ifdef __BIG_ENDIAN_BITFIELD
0198         uint64_t reserved_40_63:24;
0199         uint64_t ibplwm:20;
0200         uint64_t irhwm:20;
0201 #else
0202         uint64_t irhwm:20;
0203         uint64_t ibplwm:20;
0204         uint64_t reserved_40_63:24;
0205 #endif
0206     } s;
0207 };
0208 
0209 union cvmx_mixx_iring1 {
0210     uint64_t u64;
0211     struct cvmx_mixx_iring1_s {
0212 #ifdef __BIG_ENDIAN_BITFIELD
0213         uint64_t reserved_60_63:4;
0214         uint64_t isize:20;
0215         uint64_t ibase:37;
0216         uint64_t reserved_0_2:3;
0217 #else
0218         uint64_t reserved_0_2:3;
0219         uint64_t ibase:37;
0220         uint64_t isize:20;
0221         uint64_t reserved_60_63:4;
0222 #endif
0223     } s;
0224     struct cvmx_mixx_iring1_cn52xx {
0225 #ifdef __BIG_ENDIAN_BITFIELD
0226         uint64_t reserved_60_63:4;
0227         uint64_t isize:20;
0228         uint64_t reserved_36_39:4;
0229         uint64_t ibase:33;
0230         uint64_t reserved_0_2:3;
0231 #else
0232         uint64_t reserved_0_2:3;
0233         uint64_t ibase:33;
0234         uint64_t reserved_36_39:4;
0235         uint64_t isize:20;
0236         uint64_t reserved_60_63:4;
0237 #endif
0238     } cn52xx;
0239 };
0240 
0241 union cvmx_mixx_iring2 {
0242     uint64_t u64;
0243     struct cvmx_mixx_iring2_s {
0244 #ifdef __BIG_ENDIAN_BITFIELD
0245         uint64_t reserved_52_63:12;
0246         uint64_t itlptr:20;
0247         uint64_t reserved_20_31:12;
0248         uint64_t idbell:20;
0249 #else
0250         uint64_t idbell:20;
0251         uint64_t reserved_20_31:12;
0252         uint64_t itlptr:20;
0253         uint64_t reserved_52_63:12;
0254 #endif
0255     } s;
0256 };
0257 
0258 union cvmx_mixx_isr {
0259     uint64_t u64;
0260     struct cvmx_mixx_isr_s {
0261 #ifdef __BIG_ENDIAN_BITFIELD
0262         uint64_t reserved_8_63:56;
0263         uint64_t ts:1;
0264         uint64_t orun:1;
0265         uint64_t irun:1;
0266         uint64_t data_drp:1;
0267         uint64_t irthresh:1;
0268         uint64_t orthresh:1;
0269         uint64_t idblovf:1;
0270         uint64_t odblovf:1;
0271 #else
0272         uint64_t odblovf:1;
0273         uint64_t idblovf:1;
0274         uint64_t orthresh:1;
0275         uint64_t irthresh:1;
0276         uint64_t data_drp:1;
0277         uint64_t irun:1;
0278         uint64_t orun:1;
0279         uint64_t ts:1;
0280         uint64_t reserved_8_63:56;
0281 #endif
0282     } s;
0283     struct cvmx_mixx_isr_cn52xx {
0284 #ifdef __BIG_ENDIAN_BITFIELD
0285         uint64_t reserved_7_63:57;
0286         uint64_t orun:1;
0287         uint64_t irun:1;
0288         uint64_t data_drp:1;
0289         uint64_t irthresh:1;
0290         uint64_t orthresh:1;
0291         uint64_t idblovf:1;
0292         uint64_t odblovf:1;
0293 #else
0294         uint64_t odblovf:1;
0295         uint64_t idblovf:1;
0296         uint64_t orthresh:1;
0297         uint64_t irthresh:1;
0298         uint64_t data_drp:1;
0299         uint64_t irun:1;
0300         uint64_t orun:1;
0301         uint64_t reserved_7_63:57;
0302 #endif
0303     } cn52xx;
0304 };
0305 
0306 union cvmx_mixx_orcnt {
0307     uint64_t u64;
0308     struct cvmx_mixx_orcnt_s {
0309 #ifdef __BIG_ENDIAN_BITFIELD
0310         uint64_t reserved_20_63:44;
0311         uint64_t orcnt:20;
0312 #else
0313         uint64_t orcnt:20;
0314         uint64_t reserved_20_63:44;
0315 #endif
0316     } s;
0317 };
0318 
0319 union cvmx_mixx_orhwm {
0320     uint64_t u64;
0321     struct cvmx_mixx_orhwm_s {
0322 #ifdef __BIG_ENDIAN_BITFIELD
0323         uint64_t reserved_20_63:44;
0324         uint64_t orhwm:20;
0325 #else
0326         uint64_t orhwm:20;
0327         uint64_t reserved_20_63:44;
0328 #endif
0329     } s;
0330 };
0331 
0332 union cvmx_mixx_oring1 {
0333     uint64_t u64;
0334     struct cvmx_mixx_oring1_s {
0335 #ifdef __BIG_ENDIAN_BITFIELD
0336         uint64_t reserved_60_63:4;
0337         uint64_t osize:20;
0338         uint64_t obase:37;
0339         uint64_t reserved_0_2:3;
0340 #else
0341         uint64_t reserved_0_2:3;
0342         uint64_t obase:37;
0343         uint64_t osize:20;
0344         uint64_t reserved_60_63:4;
0345 #endif
0346     } s;
0347     struct cvmx_mixx_oring1_cn52xx {
0348 #ifdef __BIG_ENDIAN_BITFIELD
0349         uint64_t reserved_60_63:4;
0350         uint64_t osize:20;
0351         uint64_t reserved_36_39:4;
0352         uint64_t obase:33;
0353         uint64_t reserved_0_2:3;
0354 #else
0355         uint64_t reserved_0_2:3;
0356         uint64_t obase:33;
0357         uint64_t reserved_36_39:4;
0358         uint64_t osize:20;
0359         uint64_t reserved_60_63:4;
0360 #endif
0361     } cn52xx;
0362 };
0363 
0364 union cvmx_mixx_oring2 {
0365     uint64_t u64;
0366     struct cvmx_mixx_oring2_s {
0367 #ifdef __BIG_ENDIAN_BITFIELD
0368         uint64_t reserved_52_63:12;
0369         uint64_t otlptr:20;
0370         uint64_t reserved_20_31:12;
0371         uint64_t odbell:20;
0372 #else
0373         uint64_t odbell:20;
0374         uint64_t reserved_20_31:12;
0375         uint64_t otlptr:20;
0376         uint64_t reserved_52_63:12;
0377 #endif
0378     } s;
0379 };
0380 
0381 union cvmx_mixx_remcnt {
0382     uint64_t u64;
0383     struct cvmx_mixx_remcnt_s {
0384 #ifdef __BIG_ENDIAN_BITFIELD
0385         uint64_t reserved_52_63:12;
0386         uint64_t iremcnt:20;
0387         uint64_t reserved_20_31:12;
0388         uint64_t oremcnt:20;
0389 #else
0390         uint64_t oremcnt:20;
0391         uint64_t reserved_20_31:12;
0392         uint64_t iremcnt:20;
0393         uint64_t reserved_52_63:12;
0394 #endif
0395     } s;
0396 };
0397 
0398 union cvmx_mixx_tsctl {
0399     uint64_t u64;
0400     struct cvmx_mixx_tsctl_s {
0401 #ifdef __BIG_ENDIAN_BITFIELD
0402         uint64_t reserved_21_63:43;
0403         uint64_t tsavl:5;
0404         uint64_t reserved_13_15:3;
0405         uint64_t tstot:5;
0406         uint64_t reserved_5_7:3;
0407         uint64_t tscnt:5;
0408 #else
0409         uint64_t tscnt:5;
0410         uint64_t reserved_5_7:3;
0411         uint64_t tstot:5;
0412         uint64_t reserved_13_15:3;
0413         uint64_t tsavl:5;
0414         uint64_t reserved_21_63:43;
0415 #endif
0416     } s;
0417 };
0418 
0419 union cvmx_mixx_tstamp {
0420     uint64_t u64;
0421     struct cvmx_mixx_tstamp_s {
0422 #ifdef __BIG_ENDIAN_BITFIELD
0423         uint64_t tstamp:64;
0424 #else
0425         uint64_t tstamp:64;
0426 #endif
0427     } s;
0428 };
0429 
0430 #endif
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