asm/octeon/cvmx-led-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_LED_DEFS_H__
0029 #define __CVMX_LED_DEFS_H__
0030
0031 #define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
0032 #define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
0033 #define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
0034 #define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
0035 #define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
0036 #define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
0037 #define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
0038 #define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
0039 #define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
0040 #define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
0041 #define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
0042 #define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
0043 #define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
0044
0045 union cvmx_led_blink {
0046     uint64_t u64;
0047     struct cvmx_led_blink_s {
0048 #ifdef __BIG_ENDIAN_BITFIELD
0049         uint64_t reserved_8_63:56;
0050         uint64_t rate:8;
0051 #else
0052         uint64_t rate:8;
0053         uint64_t reserved_8_63:56;
0054 #endif
0055     } s;
0056 };
0057
0058 union cvmx_led_clk_phase {
0059     uint64_t u64;
0060     struct cvmx_led_clk_phase_s {
0061 #ifdef __BIG_ENDIAN_BITFIELD
0062         uint64_t reserved_7_63:57;
0063         uint64_t phase:7;
0064 #else
0065         uint64_t phase:7;
0066         uint64_t reserved_7_63:57;
0067 #endif
0068     } s;
0069 };
0070
0071 union cvmx_led_cylon {
0072     uint64_t u64;
0073     struct cvmx_led_cylon_s {
0074 #ifdef __BIG_ENDIAN_BITFIELD
0075         uint64_t reserved_16_63:48;
0076         uint64_t rate:16;
0077 #else
0078         uint64_t rate:16;
0079         uint64_t reserved_16_63:48;
0080 #endif
0081     } s;
0082 };
0083
0084 union cvmx_led_dbg {
0085     uint64_t u64;
0086     struct cvmx_led_dbg_s {
0087 #ifdef __BIG_ENDIAN_BITFIELD
0088         uint64_t reserved_1_63:63;
0089         uint64_t dbg_en:1;
0090 #else
0091         uint64_t dbg_en:1;
0092         uint64_t reserved_1_63:63;
0093 #endif
0094     } s;
0095 };
0096
0097 union cvmx_led_en {
0098     uint64_t u64;
0099     struct cvmx_led_en_s {
0100 #ifdef __BIG_ENDIAN_BITFIELD
0101         uint64_t reserved_1_63:63;
0102         uint64_t en:1;
0103 #else
0104         uint64_t en:1;
0105         uint64_t reserved_1_63:63;
0106 #endif
0107     } s;
0108 };
0109
0110 union cvmx_led_polarity {
0111     uint64_t u64;
0112     struct cvmx_led_polarity_s {
0113 #ifdef __BIG_ENDIAN_BITFIELD
0114         uint64_t reserved_1_63:63;
0115         uint64_t polarity:1;
0116 #else
0117         uint64_t polarity:1;
0118         uint64_t reserved_1_63:63;
0119 #endif
0120     } s;
0121 };
0122
0123 union cvmx_led_prt {
0124     uint64_t u64;
0125     struct cvmx_led_prt_s {
0126 #ifdef __BIG_ENDIAN_BITFIELD
0127         uint64_t reserved_8_63:56;
0128         uint64_t prt_en:8;
0129 #else
0130         uint64_t prt_en:8;
0131         uint64_t reserved_8_63:56;
0132 #endif
0133     } s;
0134 };
0135
0136 union cvmx_led_prt_fmt {
0137     uint64_t u64;
0138     struct cvmx_led_prt_fmt_s {
0139 #ifdef __BIG_ENDIAN_BITFIELD
0140         uint64_t reserved_4_63:60;
0141         uint64_t format:4;
0142 #else
0143         uint64_t format:4;
0144         uint64_t reserved_4_63:60;
0145 #endif
0146     } s;
0147 };
0148
0149 union cvmx_led_prt_statusx {
0150     uint64_t u64;
0151     struct cvmx_led_prt_statusx_s {
0152 #ifdef __BIG_ENDIAN_BITFIELD
0153         uint64_t reserved_6_63:58;
0154         uint64_t status:6;
0155 #else
0156         uint64_t status:6;
0157         uint64_t reserved_6_63:58;
0158 #endif
0159     } s;
0160 };
0161
0162 union cvmx_led_udd_cntx {
0163     uint64_t u64;
0164     struct cvmx_led_udd_cntx_s {
0165 #ifdef __BIG_ENDIAN_BITFIELD
0166         uint64_t reserved_6_63:58;
0167         uint64_t cnt:6;
0168 #else
0169         uint64_t cnt:6;
0170         uint64_t reserved_6_63:58;
0171 #endif
0172     } s;
0173 };
0174
0175 union cvmx_led_udd_datx {
0176     uint64_t u64;
0177     struct cvmx_led_udd_datx_s {
0178 #ifdef __BIG_ENDIAN_BITFIELD
0179         uint64_t reserved_32_63:32;
0180         uint64_t dat:32;
0181 #else
0182         uint64_t dat:32;
0183         uint64_t reserved_32_63:32;
0184 #endif
0185     } s;
0186 };
0187
0188 union cvmx_led_udd_dat_clrx {
0189     uint64_t u64;
0190     struct cvmx_led_udd_dat_clrx_s {
0191 #ifdef __BIG_ENDIAN_BITFIELD
0192         uint64_t reserved_32_63:32;
0193         uint64_t clr:32;
0194 #else
0195         uint64_t clr:32;
0196         uint64_t reserved_32_63:32;
0197 #endif
0198     } s;
0199 };
0200
0201 union cvmx_led_udd_dat_setx {
0202     uint64_t u64;
0203     struct cvmx_led_udd_dat_setx_s {
0204 #ifdef __BIG_ENDIAN_BITFIELD
0205         uint64_t reserved_32_63:32;
0206         uint64_t set:32;
0207 #else
0208         uint64_t set:32;
0209         uint64_t reserved_32_63:32;
0210 #endif
0211     } s;
0212 };
0213
0214 #endif