asm/octeon/cvmx-l2c.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2017 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /*
0029  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
0030  * facilities.
0031  */
0032
0033 #ifndef __CVMX_L2C_H__
0034 #define __CVMX_L2C_H__
0035
0036 #include <uapi/asm/bitfield.h>
0037
0038 #define CVMX_L2_ASSOC    cvmx_l2c_get_num_assoc()   /* Deprecated macro */
0039 #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()    /* Deprecated macro */
0040 #define CVMX_L2_SETS     cvmx_l2c_get_num_sets()    /* Deprecated macro */
0041
0042 /* Based on 128 byte cache line size */
0043 #define CVMX_L2C_IDX_ADDR_SHIFT 7
0044 #define CVMX_L2C_IDX_MASK   (cvmx_l2c_get_num_sets() - 1)
0045
0046 /* Defines for index aliasing computations */
0047 #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT +           \
0048         cvmx_l2c_get_set_bits())
0049 #define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
0050 #define CVMX_L2C_MEMBANK_SELECT_SIZE 4096
0051
0052 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
0053 #define CVMX_L2C_TADS  1
0054
0055 union cvmx_l2c_tag {
0056     uint64_t u64;
0057     struct {
0058         __BITFIELD_FIELD(uint64_t reserved:28,
0059         __BITFIELD_FIELD(uint64_t V:1,
0060         __BITFIELD_FIELD(uint64_t D:1,
0061         __BITFIELD_FIELD(uint64_t L:1,
0062         __BITFIELD_FIELD(uint64_t U:1,
0063         __BITFIELD_FIELD(uint64_t addr:32,
0064         ;))))))
0065     } s;
0066 };
0067
0068 /* L2C Performance Counter events. */
0069 enum cvmx_l2c_event {
0070     CVMX_L2C_EVENT_CYCLES       =  0,
0071     CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
0072     CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
0073     CVMX_L2C_EVENT_DATA_MISS    =  3,
0074     CVMX_L2C_EVENT_DATA_HIT     =  4,
0075     CVMX_L2C_EVENT_MISS     =  5,
0076     CVMX_L2C_EVENT_HIT      =  6,
0077     CVMX_L2C_EVENT_VICTIM_HIT   =  7,
0078     CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
0079     CVMX_L2C_EVENT_TAG_PROBE    =  9,
0080     CVMX_L2C_EVENT_TAG_UPDATE   = 10,
0081     CVMX_L2C_EVENT_TAG_COMPLETE = 11,
0082     CVMX_L2C_EVENT_TAG_DIRTY    = 12,
0083     CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
0084     CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
0085     CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
0086     CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
0087     CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
0088     CVMX_L2C_EVENT_READ_REQUEST = 18,
0089     CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
0090     CVMX_L2C_EVENT_XMC_NOP      = 20,
0091     CVMX_L2C_EVENT_XMC_LDT      = 21,
0092     CVMX_L2C_EVENT_XMC_LDI      = 22,
0093     CVMX_L2C_EVENT_XMC_LDD      = 23,
0094     CVMX_L2C_EVENT_XMC_STF      = 24,
0095     CVMX_L2C_EVENT_XMC_STT      = 25,
0096     CVMX_L2C_EVENT_XMC_STP      = 26,
0097     CVMX_L2C_EVENT_XMC_STC      = 27,
0098     CVMX_L2C_EVENT_XMC_DWB      = 28,
0099     CVMX_L2C_EVENT_XMC_PL2      = 29,
0100     CVMX_L2C_EVENT_XMC_PSL1     = 30,
0101     CVMX_L2C_EVENT_XMC_IOBLD    = 31,
0102     CVMX_L2C_EVENT_XMC_IOBST    = 32,
0103     CVMX_L2C_EVENT_XMC_IOBDMA   = 33,
0104     CVMX_L2C_EVENT_XMC_IOBRSP   = 34,
0105     CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
0106     CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
0107     CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
0108     CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
0109     CVMX_L2C_EVENT_RSC_NOP      = 39,
0110     CVMX_L2C_EVENT_RSC_STDN     = 40,
0111     CVMX_L2C_EVENT_RSC_FILL     = 41,
0112     CVMX_L2C_EVENT_RSC_REFL     = 42,
0113     CVMX_L2C_EVENT_RSC_STIN     = 43,
0114     CVMX_L2C_EVENT_RSC_SCIN     = 44,
0115     CVMX_L2C_EVENT_RSC_SCFL     = 45,
0116     CVMX_L2C_EVENT_RSC_SCDN     = 46,
0117     CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
0118     CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
0119     CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
0120     CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
0121     CVMX_L2C_EVENT_LRF_REQ      = 51,
0122     CVMX_L2C_EVENT_DT_RD_ALLOC  = 52,
0123     CVMX_L2C_EVENT_DT_WR_INVAL  = 53,
0124     CVMX_L2C_EVENT_MAX
0125 };
0126
0127 /* L2C Performance Counter events for Octeon2. */
0128 enum cvmx_l2c_tad_event {
0129     CVMX_L2C_TAD_EVENT_NONE      = 0,
0130     CVMX_L2C_TAD_EVENT_TAG_HIT   = 1,
0131     CVMX_L2C_TAD_EVENT_TAG_MISS  = 2,
0132     CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
0133     CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
0134     CVMX_L2C_TAD_EVENT_SC_FAIL   = 5,
0135     CVMX_L2C_TAD_EVENT_SC_PASS   = 6,
0136     CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
0137     CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
0138     CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
0139     CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
0140     CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
0141     CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
0142     CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
0143     CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
0144     CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
0145     CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
0146     CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
0147     CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
0148     CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
0149     CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
0150     CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
0151     CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
0152     CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
0153     CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
0154     CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,
0155     CVMX_L2C_TAD_EVENT_MAX
0156 };
0157
0158 /**
0159  * Configure one of the four L2 Cache performance counters to capture event
0160  * occurrences.
0161  *
0162  * @counter:        The counter to configure. Range 0..3.
0163  * @event:      The type of L2 Cache event occurrence to count.
0164  * @clear_on_read:  When asserted, any read of the performance counter
0165  *           clears the counter.
0166  *
0167  * @note The routine does not clear the counter.
0168  */
0169 void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
0170               uint32_t clear_on_read);
0171
0172 /**
0173  * Read the given L2 Cache performance counter. The counter must be configured
0174  * before reading, but this routine does not enforce this requirement.
0175  *
0176  * @counter:  The counter to configure. Range 0..3.
0177  *
0178  * Returns The current counter value.
0179  */
0180 uint64_t cvmx_l2c_read_perf(uint32_t counter);
0181
0182 /**
0183  * Return the L2 Cache way partitioning for a given core.
0184  *
0185  * @core:  The core processor of interest.
0186  *
0187  * Returns    The mask specifying the partitioning. 0 bits in mask indicates
0188  *      the cache 'ways' that a core can evict from.
0189  *        -1 on error
0190  */
0191 int cvmx_l2c_get_core_way_partition(uint32_t core);
0192
0193 /**
0194  * Partitions the L2 cache for a core
0195  *
0196  * @core: The core that the partitioning applies to.
0197  * @mask: The partitioning of the ways expressed as a binary
0198  *         mask. A 0 bit allows the core to evict cache lines from
0199  *         a way, while a 1 bit blocks the core from evicting any
0200  *         lines from that way. There must be at least one allowed
0201  *         way (0 bit) in the mask.
0202  *
0203
0204  * @note If any ways are blocked for all cores and the HW blocks, then
0205  *   those ways will never have any cache lines evicted from them.
0206  *   All cores and the hardware blocks are free to read from all
0207  *   ways regardless of the partitioning.
0208  */
0209 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
0210
0211 /**
0212  * Return the L2 Cache way partitioning for the hw blocks.
0213  *
0214  * Returns    The mask specifying the reserved way. 0 bits in mask indicates
0215  *      the cache 'ways' that a core can evict from.
0216  *        -1 on error
0217  */
0218 int cvmx_l2c_get_hw_way_partition(void);
0219
0220 /**
0221  * Partitions the L2 cache for the hardware blocks.
0222  *
0223  * @mask: The partitioning of the ways expressed as a binary
0224  *         mask. A 0 bit allows the core to evict cache lines from
0225  *         a way, while a 1 bit blocks the core from evicting any
0226  *         lines from that way. There must be at least one allowed
0227  *         way (0 bit) in the mask.
0228  *
0229
0230  * @note If any ways are blocked for all cores and the HW blocks, then
0231  *   those ways will never have any cache lines evicted from them.
0232  *   All cores and the hardware blocks are free to read from all
0233  *   ways regardless of the partitioning.
0234  */
0235 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
0236
0237
0238 /**
0239  * Locks a line in the L2 cache at the specified physical address
0240  *
0241  * @addr:   physical address of line to lock
0242  *
0243  * Returns 0 on success,
0244  *     1 if line not locked.
0245  */
0246 int cvmx_l2c_lock_line(uint64_t addr);
0247
0248 /**
0249  * Locks a specified memory region in the L2 cache.
0250  *
0251  * Note that if not all lines can be locked, that means that all
0252  * but one of the ways (associations) available to the locking
0253  * core are locked.  Having only 1 association available for
0254  * normal caching may have a significant adverse affect on performance.
0255  * Care should be taken to ensure that enough of the L2 cache is left
0256  * unlocked to allow for normal caching of DRAM.
0257  *
0258  * @start:  Physical address of the start of the region to lock
0259  * @len:    Length (in bytes) of region to lock
0260  *
0261  * Returns Number of requested lines that where not locked.
0262  *     0 on success (all locked)
0263  */
0264 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
0265
0266 /**
0267  * Unlock and flush a cache line from the L2 cache.
0268  * IMPORTANT: Must only be run by one core at a time due to use
0269  * of L2C debug features.
0270  * Note that this function will flush a matching but unlocked cache line.
0271  * (If address is not in L2, no lines are flushed.)
0272  *
0273  * @address: Physical address to unlock
0274  *
0275  * Returns 0: line not unlocked
0276  *     1: line unlocked
0277  */
0278 int cvmx_l2c_unlock_line(uint64_t address);
0279
0280 /**
0281  * Unlocks a region of memory that is locked in the L2 cache
0282  *
0283  * @start:  start physical address
0284  * @len:    length (in bytes) to unlock
0285  *
0286  * Returns Number of locked lines that the call unlocked
0287  */
0288 int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
0289
0290 /**
0291  * Read the L2 controller tag for a given location in L2
0292  *
0293  * @association:
0294  *       Which association to read line from
0295  * @index:  Which way to read from.
0296  *
0297  * Returns l2c tag structure for line requested.
0298  */
0299 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
0300
0301 /* Wrapper providing a deprecated old function name */
0302 static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
0303                           uint32_t index)
0304                           __attribute__((deprecated));
0305 static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
0306                           uint32_t index)
0307 {
0308     return cvmx_l2c_get_tag(association, index);
0309 }
0310
0311
0312 /**
0313  * Returns the cache index for a given physical address
0314  *
0315  * @addr:   physical address
0316  *
0317  * Returns L2 cache index
0318  */
0319 uint32_t cvmx_l2c_address_to_index(uint64_t addr);
0320
0321 /**
0322  * Flushes (and unlocks) the entire L2 cache.
0323  * IMPORTANT: Must only be run by one core at a time due to use
0324  * of L2C debug features.
0325  */
0326 void cvmx_l2c_flush(void);
0327
0328 /**
0329  *
0330  * Returns the size of the L2 cache in bytes,
0331  * -1 on error (unrecognized model)
0332  */
0333 int cvmx_l2c_get_cache_size_bytes(void);
0334
0335 /**
0336  * Return the number of sets in the L2 Cache
0337  *
0338  * Returns
0339  */
0340 int cvmx_l2c_get_num_sets(void);
0341
0342 /**
0343  * Return log base 2 of the number of sets in the L2 cache
0344  * Returns
0345  */
0346 int cvmx_l2c_get_set_bits(void);
0347 /**
0348  * Return the number of associations in the L2 Cache
0349  *
0350  * Returns
0351  */
0352 int cvmx_l2c_get_num_assoc(void);
0353
0354 /**
0355  * Flush a line from the L2 cache
0356  * This should only be called from one core at a time, as this routine
0357  * sets the core to the 'debug' core in order to flush the line.
0358  *
0359  * @assoc:  Association (or way) to flush
0360  * @index:  Index to flush
0361  */
0362 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
0363
0364 #endif /* __CVMX_L2C_H__ */