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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_IPD_DEFS_H__
0029 #define __CVMX_IPD_DEFS_H__
0030 
0031 #define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
0032 #define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
0033 #define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
0034 #define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
0035 #define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
0036 #define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
0037 #define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
0038 #define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
0039 #define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull))
0040 #define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
0041 #define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull))
0042 #define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull))
0043 #define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull))
0044 #define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull))
0045 #define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
0046 #define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
0047 #define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull))
0048 #define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull))
0049 #define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
0050 #define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull))
0051 #define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
0052 #define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull))
0053 #define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
0054 #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
0055 #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
0056 #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
0057 #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
0058 #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
0059 #define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
0060 #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
0061 #define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull))
0062 #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
0063 #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
0064 #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
0065 #define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull))
0066 #define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
0067 #define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
0068 #define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
0069 #define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
0070 #define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
0071 #define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
0072 #define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
0073 #define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
0074 #define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
0075 #define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
0076 #define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
0077 #define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
0078 #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
0079 #define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
0080 #define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull))
0081 #define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull))
0082 #define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
0083 #define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
0084 #define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
0085 #define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
0086 #define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
0087 #define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
0088 #define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
0089 #define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
0090 #define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
0091 #define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
0092 #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
0093 #define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull))
0094 #define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
0095 #define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
0096 #define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
0097 #define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
0098 #define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
0099 
0100 union cvmx_ipd_1st_mbuff_skip {
0101     uint64_t u64;
0102     struct cvmx_ipd_1st_mbuff_skip_s {
0103 #ifdef __BIG_ENDIAN_BITFIELD
0104         uint64_t reserved_6_63:58;
0105         uint64_t skip_sz:6;
0106 #else
0107         uint64_t skip_sz:6;
0108         uint64_t reserved_6_63:58;
0109 #endif
0110     } s;
0111 };
0112 
0113 union cvmx_ipd_1st_next_ptr_back {
0114     uint64_t u64;
0115     struct cvmx_ipd_1st_next_ptr_back_s {
0116 #ifdef __BIG_ENDIAN_BITFIELD
0117         uint64_t reserved_4_63:60;
0118         uint64_t back:4;
0119 #else
0120         uint64_t back:4;
0121         uint64_t reserved_4_63:60;
0122 #endif
0123     } s;
0124 };
0125 
0126 union cvmx_ipd_2nd_next_ptr_back {
0127     uint64_t u64;
0128     struct cvmx_ipd_2nd_next_ptr_back_s {
0129 #ifdef __BIG_ENDIAN_BITFIELD
0130         uint64_t reserved_4_63:60;
0131         uint64_t back:4;
0132 #else
0133         uint64_t back:4;
0134         uint64_t reserved_4_63:60;
0135 #endif
0136     } s;
0137 };
0138 
0139 union cvmx_ipd_bist_status {
0140     uint64_t u64;
0141     struct cvmx_ipd_bist_status_s {
0142 #ifdef __BIG_ENDIAN_BITFIELD
0143         uint64_t reserved_23_63:41;
0144         uint64_t iiwo1:1;
0145         uint64_t iiwo0:1;
0146         uint64_t iio1:1;
0147         uint64_t iio0:1;
0148         uint64_t pbm4:1;
0149         uint64_t csr_mem:1;
0150         uint64_t csr_ncmd:1;
0151         uint64_t pwq_wqed:1;
0152         uint64_t pwq_wp1:1;
0153         uint64_t pwq_pow:1;
0154         uint64_t ipq_pbe1:1;
0155         uint64_t ipq_pbe0:1;
0156         uint64_t pbm3:1;
0157         uint64_t pbm2:1;
0158         uint64_t pbm1:1;
0159         uint64_t pbm0:1;
0160         uint64_t pbm_word:1;
0161         uint64_t pwq1:1;
0162         uint64_t pwq0:1;
0163         uint64_t prc_off:1;
0164         uint64_t ipd_old:1;
0165         uint64_t ipd_new:1;
0166         uint64_t pwp:1;
0167 #else
0168         uint64_t pwp:1;
0169         uint64_t ipd_new:1;
0170         uint64_t ipd_old:1;
0171         uint64_t prc_off:1;
0172         uint64_t pwq0:1;
0173         uint64_t pwq1:1;
0174         uint64_t pbm_word:1;
0175         uint64_t pbm0:1;
0176         uint64_t pbm1:1;
0177         uint64_t pbm2:1;
0178         uint64_t pbm3:1;
0179         uint64_t ipq_pbe0:1;
0180         uint64_t ipq_pbe1:1;
0181         uint64_t pwq_pow:1;
0182         uint64_t pwq_wp1:1;
0183         uint64_t pwq_wqed:1;
0184         uint64_t csr_ncmd:1;
0185         uint64_t csr_mem:1;
0186         uint64_t pbm4:1;
0187         uint64_t iio0:1;
0188         uint64_t iio1:1;
0189         uint64_t iiwo0:1;
0190         uint64_t iiwo1:1;
0191         uint64_t reserved_23_63:41;
0192 #endif
0193     } s;
0194     struct cvmx_ipd_bist_status_cn30xx {
0195 #ifdef __BIG_ENDIAN_BITFIELD
0196         uint64_t reserved_16_63:48;
0197         uint64_t pwq_wqed:1;
0198         uint64_t pwq_wp1:1;
0199         uint64_t pwq_pow:1;
0200         uint64_t ipq_pbe1:1;
0201         uint64_t ipq_pbe0:1;
0202         uint64_t pbm3:1;
0203         uint64_t pbm2:1;
0204         uint64_t pbm1:1;
0205         uint64_t pbm0:1;
0206         uint64_t pbm_word:1;
0207         uint64_t pwq1:1;
0208         uint64_t pwq0:1;
0209         uint64_t prc_off:1;
0210         uint64_t ipd_old:1;
0211         uint64_t ipd_new:1;
0212         uint64_t pwp:1;
0213 #else
0214         uint64_t pwp:1;
0215         uint64_t ipd_new:1;
0216         uint64_t ipd_old:1;
0217         uint64_t prc_off:1;
0218         uint64_t pwq0:1;
0219         uint64_t pwq1:1;
0220         uint64_t pbm_word:1;
0221         uint64_t pbm0:1;
0222         uint64_t pbm1:1;
0223         uint64_t pbm2:1;
0224         uint64_t pbm3:1;
0225         uint64_t ipq_pbe0:1;
0226         uint64_t ipq_pbe1:1;
0227         uint64_t pwq_pow:1;
0228         uint64_t pwq_wp1:1;
0229         uint64_t pwq_wqed:1;
0230         uint64_t reserved_16_63:48;
0231 #endif
0232     } cn30xx;
0233     struct cvmx_ipd_bist_status_cn52xx {
0234 #ifdef __BIG_ENDIAN_BITFIELD
0235         uint64_t reserved_18_63:46;
0236         uint64_t csr_mem:1;
0237         uint64_t csr_ncmd:1;
0238         uint64_t pwq_wqed:1;
0239         uint64_t pwq_wp1:1;
0240         uint64_t pwq_pow:1;
0241         uint64_t ipq_pbe1:1;
0242         uint64_t ipq_pbe0:1;
0243         uint64_t pbm3:1;
0244         uint64_t pbm2:1;
0245         uint64_t pbm1:1;
0246         uint64_t pbm0:1;
0247         uint64_t pbm_word:1;
0248         uint64_t pwq1:1;
0249         uint64_t pwq0:1;
0250         uint64_t prc_off:1;
0251         uint64_t ipd_old:1;
0252         uint64_t ipd_new:1;
0253         uint64_t pwp:1;
0254 #else
0255         uint64_t pwp:1;
0256         uint64_t ipd_new:1;
0257         uint64_t ipd_old:1;
0258         uint64_t prc_off:1;
0259         uint64_t pwq0:1;
0260         uint64_t pwq1:1;
0261         uint64_t pbm_word:1;
0262         uint64_t pbm0:1;
0263         uint64_t pbm1:1;
0264         uint64_t pbm2:1;
0265         uint64_t pbm3:1;
0266         uint64_t ipq_pbe0:1;
0267         uint64_t ipq_pbe1:1;
0268         uint64_t pwq_pow:1;
0269         uint64_t pwq_wp1:1;
0270         uint64_t pwq_wqed:1;
0271         uint64_t csr_ncmd:1;
0272         uint64_t csr_mem:1;
0273         uint64_t reserved_18_63:46;
0274 #endif
0275     } cn52xx;
0276 };
0277 
0278 union cvmx_ipd_bp_prt_red_end {
0279     uint64_t u64;
0280     struct cvmx_ipd_bp_prt_red_end_s {
0281 #ifdef __BIG_ENDIAN_BITFIELD
0282         uint64_t reserved_48_63:16;
0283         uint64_t prt_enb:48;
0284 #else
0285         uint64_t prt_enb:48;
0286         uint64_t reserved_48_63:16;
0287 #endif
0288     } s;
0289     struct cvmx_ipd_bp_prt_red_end_cn30xx {
0290 #ifdef __BIG_ENDIAN_BITFIELD
0291         uint64_t reserved_36_63:28;
0292         uint64_t prt_enb:36;
0293 #else
0294         uint64_t prt_enb:36;
0295         uint64_t reserved_36_63:28;
0296 #endif
0297     } cn30xx;
0298     struct cvmx_ipd_bp_prt_red_end_cn52xx {
0299 #ifdef __BIG_ENDIAN_BITFIELD
0300         uint64_t reserved_40_63:24;
0301         uint64_t prt_enb:40;
0302 #else
0303         uint64_t prt_enb:40;
0304         uint64_t reserved_40_63:24;
0305 #endif
0306     } cn52xx;
0307     struct cvmx_ipd_bp_prt_red_end_cn63xx {
0308 #ifdef __BIG_ENDIAN_BITFIELD
0309         uint64_t reserved_44_63:20;
0310         uint64_t prt_enb:44;
0311 #else
0312         uint64_t prt_enb:44;
0313         uint64_t reserved_44_63:20;
0314 #endif
0315     } cn63xx;
0316 };
0317 
0318 union cvmx_ipd_bpidx_mbuf_th {
0319     uint64_t u64;
0320     struct cvmx_ipd_bpidx_mbuf_th_s {
0321 #ifdef __BIG_ENDIAN_BITFIELD
0322         uint64_t reserved_18_63:46;
0323         uint64_t bp_enb:1;
0324         uint64_t page_cnt:17;
0325 #else
0326         uint64_t page_cnt:17;
0327         uint64_t bp_enb:1;
0328         uint64_t reserved_18_63:46;
0329 #endif
0330     } s;
0331 };
0332 
0333 union cvmx_ipd_bpid_bp_counterx {
0334     uint64_t u64;
0335     struct cvmx_ipd_bpid_bp_counterx_s {
0336 #ifdef __BIG_ENDIAN_BITFIELD
0337         uint64_t reserved_25_63:39;
0338         uint64_t cnt_val:25;
0339 #else
0340         uint64_t cnt_val:25;
0341         uint64_t reserved_25_63:39;
0342 #endif
0343     } s;
0344 };
0345 
0346 union cvmx_ipd_clk_count {
0347     uint64_t u64;
0348     struct cvmx_ipd_clk_count_s {
0349 #ifdef __BIG_ENDIAN_BITFIELD
0350         uint64_t clk_cnt:64;
0351 #else
0352         uint64_t clk_cnt:64;
0353 #endif
0354     } s;
0355 };
0356 
0357 union cvmx_ipd_credits {
0358     uint64_t u64;
0359     struct cvmx_ipd_credits_s {
0360 #ifdef __BIG_ENDIAN_BITFIELD
0361         uint64_t reserved_16_63:48;
0362         uint64_t iob_wrc:8;
0363         uint64_t iob_wr:8;
0364 #else
0365         uint64_t iob_wr:8;
0366         uint64_t iob_wrc:8;
0367         uint64_t reserved_16_63:48;
0368 #endif
0369     } s;
0370 };
0371 
0372 union cvmx_ipd_ctl_status {
0373     uint64_t u64;
0374     struct cvmx_ipd_ctl_status_s {
0375 #ifdef __BIG_ENDIAN_BITFIELD
0376         uint64_t reserved_18_63:46;
0377         uint64_t use_sop:1;
0378         uint64_t rst_done:1;
0379         uint64_t clken:1;
0380         uint64_t no_wptr:1;
0381         uint64_t pq_apkt:1;
0382         uint64_t pq_nabuf:1;
0383         uint64_t ipd_full:1;
0384         uint64_t pkt_off:1;
0385         uint64_t len_m8:1;
0386         uint64_t reset:1;
0387         uint64_t addpkt:1;
0388         uint64_t naddbuf:1;
0389         uint64_t pkt_lend:1;
0390         uint64_t wqe_lend:1;
0391         uint64_t pbp_en:1;
0392         uint64_t opc_mode:2;
0393         uint64_t ipd_en:1;
0394 #else
0395         uint64_t ipd_en:1;
0396         uint64_t opc_mode:2;
0397         uint64_t pbp_en:1;
0398         uint64_t wqe_lend:1;
0399         uint64_t pkt_lend:1;
0400         uint64_t naddbuf:1;
0401         uint64_t addpkt:1;
0402         uint64_t reset:1;
0403         uint64_t len_m8:1;
0404         uint64_t pkt_off:1;
0405         uint64_t ipd_full:1;
0406         uint64_t pq_nabuf:1;
0407         uint64_t pq_apkt:1;
0408         uint64_t no_wptr:1;
0409         uint64_t clken:1;
0410         uint64_t rst_done:1;
0411         uint64_t use_sop:1;
0412         uint64_t reserved_18_63:46;
0413 #endif
0414     } s;
0415     struct cvmx_ipd_ctl_status_cn30xx {
0416 #ifdef __BIG_ENDIAN_BITFIELD
0417         uint64_t reserved_10_63:54;
0418         uint64_t len_m8:1;
0419         uint64_t reset:1;
0420         uint64_t addpkt:1;
0421         uint64_t naddbuf:1;
0422         uint64_t pkt_lend:1;
0423         uint64_t wqe_lend:1;
0424         uint64_t pbp_en:1;
0425         uint64_t opc_mode:2;
0426         uint64_t ipd_en:1;
0427 #else
0428         uint64_t ipd_en:1;
0429         uint64_t opc_mode:2;
0430         uint64_t pbp_en:1;
0431         uint64_t wqe_lend:1;
0432         uint64_t pkt_lend:1;
0433         uint64_t naddbuf:1;
0434         uint64_t addpkt:1;
0435         uint64_t reset:1;
0436         uint64_t len_m8:1;
0437         uint64_t reserved_10_63:54;
0438 #endif
0439     } cn30xx;
0440     struct cvmx_ipd_ctl_status_cn38xxp2 {
0441 #ifdef __BIG_ENDIAN_BITFIELD
0442         uint64_t reserved_9_63:55;
0443         uint64_t reset:1;
0444         uint64_t addpkt:1;
0445         uint64_t naddbuf:1;
0446         uint64_t pkt_lend:1;
0447         uint64_t wqe_lend:1;
0448         uint64_t pbp_en:1;
0449         uint64_t opc_mode:2;
0450         uint64_t ipd_en:1;
0451 #else
0452         uint64_t ipd_en:1;
0453         uint64_t opc_mode:2;
0454         uint64_t pbp_en:1;
0455         uint64_t wqe_lend:1;
0456         uint64_t pkt_lend:1;
0457         uint64_t naddbuf:1;
0458         uint64_t addpkt:1;
0459         uint64_t reset:1;
0460         uint64_t reserved_9_63:55;
0461 #endif
0462     } cn38xxp2;
0463     struct cvmx_ipd_ctl_status_cn50xx {
0464 #ifdef __BIG_ENDIAN_BITFIELD
0465         uint64_t reserved_15_63:49;
0466         uint64_t no_wptr:1;
0467         uint64_t pq_apkt:1;
0468         uint64_t pq_nabuf:1;
0469         uint64_t ipd_full:1;
0470         uint64_t pkt_off:1;
0471         uint64_t len_m8:1;
0472         uint64_t reset:1;
0473         uint64_t addpkt:1;
0474         uint64_t naddbuf:1;
0475         uint64_t pkt_lend:1;
0476         uint64_t wqe_lend:1;
0477         uint64_t pbp_en:1;
0478         uint64_t opc_mode:2;
0479         uint64_t ipd_en:1;
0480 #else
0481         uint64_t ipd_en:1;
0482         uint64_t opc_mode:2;
0483         uint64_t pbp_en:1;
0484         uint64_t wqe_lend:1;
0485         uint64_t pkt_lend:1;
0486         uint64_t naddbuf:1;
0487         uint64_t addpkt:1;
0488         uint64_t reset:1;
0489         uint64_t len_m8:1;
0490         uint64_t pkt_off:1;
0491         uint64_t ipd_full:1;
0492         uint64_t pq_nabuf:1;
0493         uint64_t pq_apkt:1;
0494         uint64_t no_wptr:1;
0495         uint64_t reserved_15_63:49;
0496 #endif
0497     } cn50xx;
0498     struct cvmx_ipd_ctl_status_cn58xx {
0499 #ifdef __BIG_ENDIAN_BITFIELD
0500         uint64_t reserved_12_63:52;
0501         uint64_t ipd_full:1;
0502         uint64_t pkt_off:1;
0503         uint64_t len_m8:1;
0504         uint64_t reset:1;
0505         uint64_t addpkt:1;
0506         uint64_t naddbuf:1;
0507         uint64_t pkt_lend:1;
0508         uint64_t wqe_lend:1;
0509         uint64_t pbp_en:1;
0510         uint64_t opc_mode:2;
0511         uint64_t ipd_en:1;
0512 #else
0513         uint64_t ipd_en:1;
0514         uint64_t opc_mode:2;
0515         uint64_t pbp_en:1;
0516         uint64_t wqe_lend:1;
0517         uint64_t pkt_lend:1;
0518         uint64_t naddbuf:1;
0519         uint64_t addpkt:1;
0520         uint64_t reset:1;
0521         uint64_t len_m8:1;
0522         uint64_t pkt_off:1;
0523         uint64_t ipd_full:1;
0524         uint64_t reserved_12_63:52;
0525 #endif
0526     } cn58xx;
0527     struct cvmx_ipd_ctl_status_cn63xxp1 {
0528 #ifdef __BIG_ENDIAN_BITFIELD
0529         uint64_t reserved_16_63:48;
0530         uint64_t clken:1;
0531         uint64_t no_wptr:1;
0532         uint64_t pq_apkt:1;
0533         uint64_t pq_nabuf:1;
0534         uint64_t ipd_full:1;
0535         uint64_t pkt_off:1;
0536         uint64_t len_m8:1;
0537         uint64_t reset:1;
0538         uint64_t addpkt:1;
0539         uint64_t naddbuf:1;
0540         uint64_t pkt_lend:1;
0541         uint64_t wqe_lend:1;
0542         uint64_t pbp_en:1;
0543         uint64_t opc_mode:2;
0544         uint64_t ipd_en:1;
0545 #else
0546         uint64_t ipd_en:1;
0547         uint64_t opc_mode:2;
0548         uint64_t pbp_en:1;
0549         uint64_t wqe_lend:1;
0550         uint64_t pkt_lend:1;
0551         uint64_t naddbuf:1;
0552         uint64_t addpkt:1;
0553         uint64_t reset:1;
0554         uint64_t len_m8:1;
0555         uint64_t pkt_off:1;
0556         uint64_t ipd_full:1;
0557         uint64_t pq_nabuf:1;
0558         uint64_t pq_apkt:1;
0559         uint64_t no_wptr:1;
0560         uint64_t clken:1;
0561         uint64_t reserved_16_63:48;
0562 #endif
0563     } cn63xxp1;
0564 };
0565 
0566 union cvmx_ipd_ecc_ctl {
0567     uint64_t u64;
0568     struct cvmx_ipd_ecc_ctl_s {
0569 #ifdef __BIG_ENDIAN_BITFIELD
0570         uint64_t reserved_8_63:56;
0571         uint64_t pm3_syn:2;
0572         uint64_t pm2_syn:2;
0573         uint64_t pm1_syn:2;
0574         uint64_t pm0_syn:2;
0575 #else
0576         uint64_t pm0_syn:2;
0577         uint64_t pm1_syn:2;
0578         uint64_t pm2_syn:2;
0579         uint64_t pm3_syn:2;
0580         uint64_t reserved_8_63:56;
0581 #endif
0582     } s;
0583 };
0584 
0585 union cvmx_ipd_free_ptr_fifo_ctl {
0586     uint64_t u64;
0587     struct cvmx_ipd_free_ptr_fifo_ctl_s {
0588 #ifdef __BIG_ENDIAN_BITFIELD
0589         uint64_t reserved_32_63:32;
0590         uint64_t max_cnts:7;
0591         uint64_t wraddr:8;
0592         uint64_t praddr:8;
0593         uint64_t cena:1;
0594         uint64_t raddr:8;
0595 #else
0596         uint64_t raddr:8;
0597         uint64_t cena:1;
0598         uint64_t praddr:8;
0599         uint64_t wraddr:8;
0600         uint64_t max_cnts:7;
0601         uint64_t reserved_32_63:32;
0602 #endif
0603     } s;
0604 };
0605 
0606 union cvmx_ipd_free_ptr_value {
0607     uint64_t u64;
0608     struct cvmx_ipd_free_ptr_value_s {
0609 #ifdef __BIG_ENDIAN_BITFIELD
0610         uint64_t reserved_33_63:31;
0611         uint64_t ptr:33;
0612 #else
0613         uint64_t ptr:33;
0614         uint64_t reserved_33_63:31;
0615 #endif
0616     } s;
0617 };
0618 
0619 union cvmx_ipd_hold_ptr_fifo_ctl {
0620     uint64_t u64;
0621     struct cvmx_ipd_hold_ptr_fifo_ctl_s {
0622 #ifdef __BIG_ENDIAN_BITFIELD
0623         uint64_t reserved_43_63:21;
0624         uint64_t ptr:33;
0625         uint64_t max_pkt:3;
0626         uint64_t praddr:3;
0627         uint64_t cena:1;
0628         uint64_t raddr:3;
0629 #else
0630         uint64_t raddr:3;
0631         uint64_t cena:1;
0632         uint64_t praddr:3;
0633         uint64_t max_pkt:3;
0634         uint64_t ptr:33;
0635         uint64_t reserved_43_63:21;
0636 #endif
0637     } s;
0638 };
0639 
0640 union cvmx_ipd_int_enb {
0641     uint64_t u64;
0642     struct cvmx_ipd_int_enb_s {
0643 #ifdef __BIG_ENDIAN_BITFIELD
0644         uint64_t reserved_23_63:41;
0645         uint64_t pw3_dbe:1;
0646         uint64_t pw3_sbe:1;
0647         uint64_t pw2_dbe:1;
0648         uint64_t pw2_sbe:1;
0649         uint64_t pw1_dbe:1;
0650         uint64_t pw1_sbe:1;
0651         uint64_t pw0_dbe:1;
0652         uint64_t pw0_sbe:1;
0653         uint64_t dat:1;
0654         uint64_t eop:1;
0655         uint64_t sop:1;
0656         uint64_t pq_sub:1;
0657         uint64_t pq_add:1;
0658         uint64_t bc_ovr:1;
0659         uint64_t d_coll:1;
0660         uint64_t c_coll:1;
0661         uint64_t cc_ovr:1;
0662         uint64_t dc_ovr:1;
0663         uint64_t bp_sub:1;
0664         uint64_t prc_par3:1;
0665         uint64_t prc_par2:1;
0666         uint64_t prc_par1:1;
0667         uint64_t prc_par0:1;
0668 #else
0669         uint64_t prc_par0:1;
0670         uint64_t prc_par1:1;
0671         uint64_t prc_par2:1;
0672         uint64_t prc_par3:1;
0673         uint64_t bp_sub:1;
0674         uint64_t dc_ovr:1;
0675         uint64_t cc_ovr:1;
0676         uint64_t c_coll:1;
0677         uint64_t d_coll:1;
0678         uint64_t bc_ovr:1;
0679         uint64_t pq_add:1;
0680         uint64_t pq_sub:1;
0681         uint64_t sop:1;
0682         uint64_t eop:1;
0683         uint64_t dat:1;
0684         uint64_t pw0_sbe:1;
0685         uint64_t pw0_dbe:1;
0686         uint64_t pw1_sbe:1;
0687         uint64_t pw1_dbe:1;
0688         uint64_t pw2_sbe:1;
0689         uint64_t pw2_dbe:1;
0690         uint64_t pw3_sbe:1;
0691         uint64_t pw3_dbe:1;
0692         uint64_t reserved_23_63:41;
0693 #endif
0694     } s;
0695     struct cvmx_ipd_int_enb_cn30xx {
0696 #ifdef __BIG_ENDIAN_BITFIELD
0697         uint64_t reserved_5_63:59;
0698         uint64_t bp_sub:1;
0699         uint64_t prc_par3:1;
0700         uint64_t prc_par2:1;
0701         uint64_t prc_par1:1;
0702         uint64_t prc_par0:1;
0703 #else
0704         uint64_t prc_par0:1;
0705         uint64_t prc_par1:1;
0706         uint64_t prc_par2:1;
0707         uint64_t prc_par3:1;
0708         uint64_t bp_sub:1;
0709         uint64_t reserved_5_63:59;
0710 #endif
0711     } cn30xx;
0712     struct cvmx_ipd_int_enb_cn38xx {
0713 #ifdef __BIG_ENDIAN_BITFIELD
0714         uint64_t reserved_10_63:54;
0715         uint64_t bc_ovr:1;
0716         uint64_t d_coll:1;
0717         uint64_t c_coll:1;
0718         uint64_t cc_ovr:1;
0719         uint64_t dc_ovr:1;
0720         uint64_t bp_sub:1;
0721         uint64_t prc_par3:1;
0722         uint64_t prc_par2:1;
0723         uint64_t prc_par1:1;
0724         uint64_t prc_par0:1;
0725 #else
0726         uint64_t prc_par0:1;
0727         uint64_t prc_par1:1;
0728         uint64_t prc_par2:1;
0729         uint64_t prc_par3:1;
0730         uint64_t bp_sub:1;
0731         uint64_t dc_ovr:1;
0732         uint64_t cc_ovr:1;
0733         uint64_t c_coll:1;
0734         uint64_t d_coll:1;
0735         uint64_t bc_ovr:1;
0736         uint64_t reserved_10_63:54;
0737 #endif
0738     } cn38xx;
0739     struct cvmx_ipd_int_enb_cn52xx {
0740 #ifdef __BIG_ENDIAN_BITFIELD
0741         uint64_t reserved_12_63:52;
0742         uint64_t pq_sub:1;
0743         uint64_t pq_add:1;
0744         uint64_t bc_ovr:1;
0745         uint64_t d_coll:1;
0746         uint64_t c_coll:1;
0747         uint64_t cc_ovr:1;
0748         uint64_t dc_ovr:1;
0749         uint64_t bp_sub:1;
0750         uint64_t prc_par3:1;
0751         uint64_t prc_par2:1;
0752         uint64_t prc_par1:1;
0753         uint64_t prc_par0:1;
0754 #else
0755         uint64_t prc_par0:1;
0756         uint64_t prc_par1:1;
0757         uint64_t prc_par2:1;
0758         uint64_t prc_par3:1;
0759         uint64_t bp_sub:1;
0760         uint64_t dc_ovr:1;
0761         uint64_t cc_ovr:1;
0762         uint64_t c_coll:1;
0763         uint64_t d_coll:1;
0764         uint64_t bc_ovr:1;
0765         uint64_t pq_add:1;
0766         uint64_t pq_sub:1;
0767         uint64_t reserved_12_63:52;
0768 #endif
0769     } cn52xx;
0770 };
0771 
0772 union cvmx_ipd_int_sum {
0773     uint64_t u64;
0774     struct cvmx_ipd_int_sum_s {
0775 #ifdef __BIG_ENDIAN_BITFIELD
0776         uint64_t reserved_23_63:41;
0777         uint64_t pw3_dbe:1;
0778         uint64_t pw3_sbe:1;
0779         uint64_t pw2_dbe:1;
0780         uint64_t pw2_sbe:1;
0781         uint64_t pw1_dbe:1;
0782         uint64_t pw1_sbe:1;
0783         uint64_t pw0_dbe:1;
0784         uint64_t pw0_sbe:1;
0785         uint64_t dat:1;
0786         uint64_t eop:1;
0787         uint64_t sop:1;
0788         uint64_t pq_sub:1;
0789         uint64_t pq_add:1;
0790         uint64_t bc_ovr:1;
0791         uint64_t d_coll:1;
0792         uint64_t c_coll:1;
0793         uint64_t cc_ovr:1;
0794         uint64_t dc_ovr:1;
0795         uint64_t bp_sub:1;
0796         uint64_t prc_par3:1;
0797         uint64_t prc_par2:1;
0798         uint64_t prc_par1:1;
0799         uint64_t prc_par0:1;
0800 #else
0801         uint64_t prc_par0:1;
0802         uint64_t prc_par1:1;
0803         uint64_t prc_par2:1;
0804         uint64_t prc_par3:1;
0805         uint64_t bp_sub:1;
0806         uint64_t dc_ovr:1;
0807         uint64_t cc_ovr:1;
0808         uint64_t c_coll:1;
0809         uint64_t d_coll:1;
0810         uint64_t bc_ovr:1;
0811         uint64_t pq_add:1;
0812         uint64_t pq_sub:1;
0813         uint64_t sop:1;
0814         uint64_t eop:1;
0815         uint64_t dat:1;
0816         uint64_t pw0_sbe:1;
0817         uint64_t pw0_dbe:1;
0818         uint64_t pw1_sbe:1;
0819         uint64_t pw1_dbe:1;
0820         uint64_t pw2_sbe:1;
0821         uint64_t pw2_dbe:1;
0822         uint64_t pw3_sbe:1;
0823         uint64_t pw3_dbe:1;
0824         uint64_t reserved_23_63:41;
0825 #endif
0826     } s;
0827     struct cvmx_ipd_int_sum_cn30xx {
0828 #ifdef __BIG_ENDIAN_BITFIELD
0829         uint64_t reserved_5_63:59;
0830         uint64_t bp_sub:1;
0831         uint64_t prc_par3:1;
0832         uint64_t prc_par2:1;
0833         uint64_t prc_par1:1;
0834         uint64_t prc_par0:1;
0835 #else
0836         uint64_t prc_par0:1;
0837         uint64_t prc_par1:1;
0838         uint64_t prc_par2:1;
0839         uint64_t prc_par3:1;
0840         uint64_t bp_sub:1;
0841         uint64_t reserved_5_63:59;
0842 #endif
0843     } cn30xx;
0844     struct cvmx_ipd_int_sum_cn38xx {
0845 #ifdef __BIG_ENDIAN_BITFIELD
0846         uint64_t reserved_10_63:54;
0847         uint64_t bc_ovr:1;
0848         uint64_t d_coll:1;
0849         uint64_t c_coll:1;
0850         uint64_t cc_ovr:1;
0851         uint64_t dc_ovr:1;
0852         uint64_t bp_sub:1;
0853         uint64_t prc_par3:1;
0854         uint64_t prc_par2:1;
0855         uint64_t prc_par1:1;
0856         uint64_t prc_par0:1;
0857 #else
0858         uint64_t prc_par0:1;
0859         uint64_t prc_par1:1;
0860         uint64_t prc_par2:1;
0861         uint64_t prc_par3:1;
0862         uint64_t bp_sub:1;
0863         uint64_t dc_ovr:1;
0864         uint64_t cc_ovr:1;
0865         uint64_t c_coll:1;
0866         uint64_t d_coll:1;
0867         uint64_t bc_ovr:1;
0868         uint64_t reserved_10_63:54;
0869 #endif
0870     } cn38xx;
0871     struct cvmx_ipd_int_sum_cn52xx {
0872 #ifdef __BIG_ENDIAN_BITFIELD
0873         uint64_t reserved_12_63:52;
0874         uint64_t pq_sub:1;
0875         uint64_t pq_add:1;
0876         uint64_t bc_ovr:1;
0877         uint64_t d_coll:1;
0878         uint64_t c_coll:1;
0879         uint64_t cc_ovr:1;
0880         uint64_t dc_ovr:1;
0881         uint64_t bp_sub:1;
0882         uint64_t prc_par3:1;
0883         uint64_t prc_par2:1;
0884         uint64_t prc_par1:1;
0885         uint64_t prc_par0:1;
0886 #else
0887         uint64_t prc_par0:1;
0888         uint64_t prc_par1:1;
0889         uint64_t prc_par2:1;
0890         uint64_t prc_par3:1;
0891         uint64_t bp_sub:1;
0892         uint64_t dc_ovr:1;
0893         uint64_t cc_ovr:1;
0894         uint64_t c_coll:1;
0895         uint64_t d_coll:1;
0896         uint64_t bc_ovr:1;
0897         uint64_t pq_add:1;
0898         uint64_t pq_sub:1;
0899         uint64_t reserved_12_63:52;
0900 #endif
0901     } cn52xx;
0902 };
0903 
0904 union cvmx_ipd_next_pkt_ptr {
0905     uint64_t u64;
0906     struct cvmx_ipd_next_pkt_ptr_s {
0907 #ifdef __BIG_ENDIAN_BITFIELD
0908         uint64_t reserved_33_63:31;
0909         uint64_t ptr:33;
0910 #else
0911         uint64_t ptr:33;
0912         uint64_t reserved_33_63:31;
0913 #endif
0914     } s;
0915 };
0916 
0917 union cvmx_ipd_next_wqe_ptr {
0918     uint64_t u64;
0919     struct cvmx_ipd_next_wqe_ptr_s {
0920 #ifdef __BIG_ENDIAN_BITFIELD
0921         uint64_t reserved_33_63:31;
0922         uint64_t ptr:33;
0923 #else
0924         uint64_t ptr:33;
0925         uint64_t reserved_33_63:31;
0926 #endif
0927     } s;
0928 };
0929 
0930 union cvmx_ipd_not_1st_mbuff_skip {
0931     uint64_t u64;
0932     struct cvmx_ipd_not_1st_mbuff_skip_s {
0933 #ifdef __BIG_ENDIAN_BITFIELD
0934         uint64_t reserved_6_63:58;
0935         uint64_t skip_sz:6;
0936 #else
0937         uint64_t skip_sz:6;
0938         uint64_t reserved_6_63:58;
0939 #endif
0940     } s;
0941 };
0942 
0943 union cvmx_ipd_on_bp_drop_pktx {
0944     uint64_t u64;
0945     struct cvmx_ipd_on_bp_drop_pktx_s {
0946 #ifdef __BIG_ENDIAN_BITFIELD
0947         uint64_t prt_enb:64;
0948 #else
0949         uint64_t prt_enb:64;
0950 #endif
0951     } s;
0952 };
0953 
0954 union cvmx_ipd_packet_mbuff_size {
0955     uint64_t u64;
0956     struct cvmx_ipd_packet_mbuff_size_s {
0957 #ifdef __BIG_ENDIAN_BITFIELD
0958         uint64_t reserved_12_63:52;
0959         uint64_t mb_size:12;
0960 #else
0961         uint64_t mb_size:12;
0962         uint64_t reserved_12_63:52;
0963 #endif
0964     } s;
0965 };
0966 
0967 union cvmx_ipd_pkt_err {
0968     uint64_t u64;
0969     struct cvmx_ipd_pkt_err_s {
0970 #ifdef __BIG_ENDIAN_BITFIELD
0971         uint64_t reserved_6_63:58;
0972         uint64_t reasm:6;
0973 #else
0974         uint64_t reasm:6;
0975         uint64_t reserved_6_63:58;
0976 #endif
0977     } s;
0978 };
0979 
0980 union cvmx_ipd_pkt_ptr_valid {
0981     uint64_t u64;
0982     struct cvmx_ipd_pkt_ptr_valid_s {
0983 #ifdef __BIG_ENDIAN_BITFIELD
0984         uint64_t reserved_29_63:35;
0985         uint64_t ptr:29;
0986 #else
0987         uint64_t ptr:29;
0988         uint64_t reserved_29_63:35;
0989 #endif
0990     } s;
0991 };
0992 
0993 union cvmx_ipd_portx_bp_page_cnt {
0994     uint64_t u64;
0995     struct cvmx_ipd_portx_bp_page_cnt_s {
0996 #ifdef __BIG_ENDIAN_BITFIELD
0997         uint64_t reserved_18_63:46;
0998         uint64_t bp_enb:1;
0999         uint64_t page_cnt:17;
1000 #else
1001         uint64_t page_cnt:17;
1002         uint64_t bp_enb:1;
1003         uint64_t reserved_18_63:46;
1004 #endif
1005     } s;
1006 };
1007 
1008 union cvmx_ipd_portx_bp_page_cnt2 {
1009     uint64_t u64;
1010     struct cvmx_ipd_portx_bp_page_cnt2_s {
1011 #ifdef __BIG_ENDIAN_BITFIELD
1012         uint64_t reserved_18_63:46;
1013         uint64_t bp_enb:1;
1014         uint64_t page_cnt:17;
1015 #else
1016         uint64_t page_cnt:17;
1017         uint64_t bp_enb:1;
1018         uint64_t reserved_18_63:46;
1019 #endif
1020     } s;
1021 };
1022 
1023 union cvmx_ipd_portx_bp_page_cnt3 {
1024     uint64_t u64;
1025     struct cvmx_ipd_portx_bp_page_cnt3_s {
1026 #ifdef __BIG_ENDIAN_BITFIELD
1027         uint64_t reserved_18_63:46;
1028         uint64_t bp_enb:1;
1029         uint64_t page_cnt:17;
1030 #else
1031         uint64_t page_cnt:17;
1032         uint64_t bp_enb:1;
1033         uint64_t reserved_18_63:46;
1034 #endif
1035     } s;
1036 };
1037 
1038 union cvmx_ipd_port_bp_counters2_pairx {
1039     uint64_t u64;
1040     struct cvmx_ipd_port_bp_counters2_pairx_s {
1041 #ifdef __BIG_ENDIAN_BITFIELD
1042         uint64_t reserved_25_63:39;
1043         uint64_t cnt_val:25;
1044 #else
1045         uint64_t cnt_val:25;
1046         uint64_t reserved_25_63:39;
1047 #endif
1048     } s;
1049 };
1050 
1051 union cvmx_ipd_port_bp_counters3_pairx {
1052     uint64_t u64;
1053     struct cvmx_ipd_port_bp_counters3_pairx_s {
1054 #ifdef __BIG_ENDIAN_BITFIELD
1055         uint64_t reserved_25_63:39;
1056         uint64_t cnt_val:25;
1057 #else
1058         uint64_t cnt_val:25;
1059         uint64_t reserved_25_63:39;
1060 #endif
1061     } s;
1062 };
1063 
1064 union cvmx_ipd_port_bp_counters4_pairx {
1065     uint64_t u64;
1066     struct cvmx_ipd_port_bp_counters4_pairx_s {
1067 #ifdef __BIG_ENDIAN_BITFIELD
1068         uint64_t reserved_25_63:39;
1069         uint64_t cnt_val:25;
1070 #else
1071         uint64_t cnt_val:25;
1072         uint64_t reserved_25_63:39;
1073 #endif
1074     } s;
1075 };
1076 
1077 union cvmx_ipd_port_bp_counters_pairx {
1078     uint64_t u64;
1079     struct cvmx_ipd_port_bp_counters_pairx_s {
1080 #ifdef __BIG_ENDIAN_BITFIELD
1081         uint64_t reserved_25_63:39;
1082         uint64_t cnt_val:25;
1083 #else
1084         uint64_t cnt_val:25;
1085         uint64_t reserved_25_63:39;
1086 #endif
1087     } s;
1088 };
1089 
1090 union cvmx_ipd_port_ptr_fifo_ctl {
1091     uint64_t u64;
1092     struct cvmx_ipd_port_ptr_fifo_ctl_s {
1093 #ifdef __BIG_ENDIAN_BITFIELD
1094         uint64_t reserved_48_63:16;
1095         uint64_t ptr:33;
1096         uint64_t max_pkt:7;
1097         uint64_t cena:1;
1098         uint64_t raddr:7;
1099 #else
1100         uint64_t raddr:7;
1101         uint64_t cena:1;
1102         uint64_t max_pkt:7;
1103         uint64_t ptr:33;
1104         uint64_t reserved_48_63:16;
1105 #endif
1106     } s;
1107 };
1108 
1109 union cvmx_ipd_port_qos_x_cnt {
1110     uint64_t u64;
1111     struct cvmx_ipd_port_qos_x_cnt_s {
1112 #ifdef __BIG_ENDIAN_BITFIELD
1113         uint64_t wmark:32;
1114         uint64_t cnt:32;
1115 #else
1116         uint64_t cnt:32;
1117         uint64_t wmark:32;
1118 #endif
1119     } s;
1120 };
1121 
1122 union cvmx_ipd_port_qos_intx {
1123     uint64_t u64;
1124     struct cvmx_ipd_port_qos_intx_s {
1125 #ifdef __BIG_ENDIAN_BITFIELD
1126         uint64_t intr:64;
1127 #else
1128         uint64_t intr:64;
1129 #endif
1130     } s;
1131 };
1132 
1133 union cvmx_ipd_port_qos_int_enbx {
1134     uint64_t u64;
1135     struct cvmx_ipd_port_qos_int_enbx_s {
1136 #ifdef __BIG_ENDIAN_BITFIELD
1137         uint64_t enb:64;
1138 #else
1139         uint64_t enb:64;
1140 #endif
1141     } s;
1142 };
1143 
1144 union cvmx_ipd_port_sopx {
1145     uint64_t u64;
1146     struct cvmx_ipd_port_sopx_s {
1147 #ifdef __BIG_ENDIAN_BITFIELD
1148         uint64_t sop:64;
1149 #else
1150         uint64_t sop:64;
1151 #endif
1152     } s;
1153 };
1154 
1155 union cvmx_ipd_prc_hold_ptr_fifo_ctl {
1156     uint64_t u64;
1157     struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
1158 #ifdef __BIG_ENDIAN_BITFIELD
1159         uint64_t reserved_39_63:25;
1160         uint64_t max_pkt:3;
1161         uint64_t praddr:3;
1162         uint64_t ptr:29;
1163         uint64_t cena:1;
1164         uint64_t raddr:3;
1165 #else
1166         uint64_t raddr:3;
1167         uint64_t cena:1;
1168         uint64_t ptr:29;
1169         uint64_t praddr:3;
1170         uint64_t max_pkt:3;
1171         uint64_t reserved_39_63:25;
1172 #endif
1173     } s;
1174 };
1175 
1176 union cvmx_ipd_prc_port_ptr_fifo_ctl {
1177     uint64_t u64;
1178     struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
1179 #ifdef __BIG_ENDIAN_BITFIELD
1180         uint64_t reserved_44_63:20;
1181         uint64_t max_pkt:7;
1182         uint64_t ptr:29;
1183         uint64_t cena:1;
1184         uint64_t raddr:7;
1185 #else
1186         uint64_t raddr:7;
1187         uint64_t cena:1;
1188         uint64_t ptr:29;
1189         uint64_t max_pkt:7;
1190         uint64_t reserved_44_63:20;
1191 #endif
1192     } s;
1193 };
1194 
1195 union cvmx_ipd_ptr_count {
1196     uint64_t u64;
1197     struct cvmx_ipd_ptr_count_s {
1198 #ifdef __BIG_ENDIAN_BITFIELD
1199         uint64_t reserved_19_63:45;
1200         uint64_t pktv_cnt:1;
1201         uint64_t wqev_cnt:1;
1202         uint64_t pfif_cnt:3;
1203         uint64_t pkt_pcnt:7;
1204         uint64_t wqe_pcnt:7;
1205 #else
1206         uint64_t wqe_pcnt:7;
1207         uint64_t pkt_pcnt:7;
1208         uint64_t pfif_cnt:3;
1209         uint64_t wqev_cnt:1;
1210         uint64_t pktv_cnt:1;
1211         uint64_t reserved_19_63:45;
1212 #endif
1213     } s;
1214 };
1215 
1216 union cvmx_ipd_pwp_ptr_fifo_ctl {
1217     uint64_t u64;
1218     struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220         uint64_t reserved_61_63:3;
1221         uint64_t max_cnts:7;
1222         uint64_t wraddr:8;
1223         uint64_t praddr:8;
1224         uint64_t ptr:29;
1225         uint64_t cena:1;
1226         uint64_t raddr:8;
1227 #else
1228         uint64_t raddr:8;
1229         uint64_t cena:1;
1230         uint64_t ptr:29;
1231         uint64_t praddr:8;
1232         uint64_t wraddr:8;
1233         uint64_t max_cnts:7;
1234         uint64_t reserved_61_63:3;
1235 #endif
1236     } s;
1237 };
1238 
1239 union cvmx_ipd_qosx_red_marks {
1240     uint64_t u64;
1241     struct cvmx_ipd_qosx_red_marks_s {
1242 #ifdef __BIG_ENDIAN_BITFIELD
1243         uint64_t drop:32;
1244         uint64_t pass:32;
1245 #else
1246         uint64_t pass:32;
1247         uint64_t drop:32;
1248 #endif
1249     } s;
1250 };
1251 
1252 union cvmx_ipd_que0_free_page_cnt {
1253     uint64_t u64;
1254     struct cvmx_ipd_que0_free_page_cnt_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256         uint64_t reserved_32_63:32;
1257         uint64_t q0_pcnt:32;
1258 #else
1259         uint64_t q0_pcnt:32;
1260         uint64_t reserved_32_63:32;
1261 #endif
1262     } s;
1263 };
1264 
1265 union cvmx_ipd_red_bpid_enablex {
1266     uint64_t u64;
1267     struct cvmx_ipd_red_bpid_enablex_s {
1268 #ifdef __BIG_ENDIAN_BITFIELD
1269         uint64_t prt_enb:64;
1270 #else
1271         uint64_t prt_enb:64;
1272 #endif
1273     } s;
1274 };
1275 
1276 union cvmx_ipd_red_delay {
1277     uint64_t u64;
1278     struct cvmx_ipd_red_delay_s {
1279 #ifdef __BIG_ENDIAN_BITFIELD
1280         uint64_t reserved_28_63:36;
1281         uint64_t prb_dly:14;
1282         uint64_t avg_dly:14;
1283 #else
1284         uint64_t avg_dly:14;
1285         uint64_t prb_dly:14;
1286         uint64_t reserved_28_63:36;
1287 #endif
1288     } s;
1289 };
1290 
1291 union cvmx_ipd_red_port_enable {
1292     uint64_t u64;
1293     struct cvmx_ipd_red_port_enable_s {
1294 #ifdef __BIG_ENDIAN_BITFIELD
1295         uint64_t prb_dly:14;
1296         uint64_t avg_dly:14;
1297         uint64_t prt_enb:36;
1298 #else
1299         uint64_t prt_enb:36;
1300         uint64_t avg_dly:14;
1301         uint64_t prb_dly:14;
1302 #endif
1303     } s;
1304 };
1305 
1306 union cvmx_ipd_red_port_enable2 {
1307     uint64_t u64;
1308     struct cvmx_ipd_red_port_enable2_s {
1309 #ifdef __BIG_ENDIAN_BITFIELD
1310         uint64_t reserved_12_63:52;
1311         uint64_t prt_enb:12;
1312 #else
1313         uint64_t prt_enb:12;
1314         uint64_t reserved_12_63:52;
1315 #endif
1316     } s;
1317     struct cvmx_ipd_red_port_enable2_cn52xx {
1318 #ifdef __BIG_ENDIAN_BITFIELD
1319         uint64_t reserved_4_63:60;
1320         uint64_t prt_enb:4;
1321 #else
1322         uint64_t prt_enb:4;
1323         uint64_t reserved_4_63:60;
1324 #endif
1325     } cn52xx;
1326     struct cvmx_ipd_red_port_enable2_cn63xx {
1327 #ifdef __BIG_ENDIAN_BITFIELD
1328         uint64_t reserved_8_63:56;
1329         uint64_t prt_enb:8;
1330 #else
1331         uint64_t prt_enb:8;
1332         uint64_t reserved_8_63:56;
1333 #endif
1334     } cn63xx;
1335 };
1336 
1337 union cvmx_ipd_red_quex_param {
1338     uint64_t u64;
1339     struct cvmx_ipd_red_quex_param_s {
1340 #ifdef __BIG_ENDIAN_BITFIELD
1341         uint64_t reserved_49_63:15;
1342         uint64_t use_pcnt:1;
1343         uint64_t new_con:8;
1344         uint64_t avg_con:8;
1345         uint64_t prb_con:32;
1346 #else
1347         uint64_t prb_con:32;
1348         uint64_t avg_con:8;
1349         uint64_t new_con:8;
1350         uint64_t use_pcnt:1;
1351         uint64_t reserved_49_63:15;
1352 #endif
1353     } s;
1354 };
1355 
1356 union cvmx_ipd_req_wgt {
1357     uint64_t u64;
1358     struct cvmx_ipd_req_wgt_s {
1359 #ifdef __BIG_ENDIAN_BITFIELD
1360         uint64_t wgt7:8;
1361         uint64_t wgt6:8;
1362         uint64_t wgt5:8;
1363         uint64_t wgt4:8;
1364         uint64_t wgt3:8;
1365         uint64_t wgt2:8;
1366         uint64_t wgt1:8;
1367         uint64_t wgt0:8;
1368 #else
1369         uint64_t wgt0:8;
1370         uint64_t wgt1:8;
1371         uint64_t wgt2:8;
1372         uint64_t wgt3:8;
1373         uint64_t wgt4:8;
1374         uint64_t wgt5:8;
1375         uint64_t wgt6:8;
1376         uint64_t wgt7:8;
1377 #endif
1378     } s;
1379 };
1380 
1381 union cvmx_ipd_sub_port_bp_page_cnt {
1382     uint64_t u64;
1383     struct cvmx_ipd_sub_port_bp_page_cnt_s {
1384 #ifdef __BIG_ENDIAN_BITFIELD
1385         uint64_t reserved_31_63:33;
1386         uint64_t port:6;
1387         uint64_t page_cnt:25;
1388 #else
1389         uint64_t page_cnt:25;
1390         uint64_t port:6;
1391         uint64_t reserved_31_63:33;
1392 #endif
1393     } s;
1394 };
1395 
1396 union cvmx_ipd_sub_port_fcs {
1397     uint64_t u64;
1398     struct cvmx_ipd_sub_port_fcs_s {
1399 #ifdef __BIG_ENDIAN_BITFIELD
1400         uint64_t reserved_40_63:24;
1401         uint64_t port_bit2:4;
1402         uint64_t reserved_32_35:4;
1403         uint64_t port_bit:32;
1404 #else
1405         uint64_t port_bit:32;
1406         uint64_t reserved_32_35:4;
1407         uint64_t port_bit2:4;
1408         uint64_t reserved_40_63:24;
1409 #endif
1410     } s;
1411     struct cvmx_ipd_sub_port_fcs_cn30xx {
1412 #ifdef __BIG_ENDIAN_BITFIELD
1413         uint64_t reserved_3_63:61;
1414         uint64_t port_bit:3;
1415 #else
1416         uint64_t port_bit:3;
1417         uint64_t reserved_3_63:61;
1418 #endif
1419     } cn30xx;
1420     struct cvmx_ipd_sub_port_fcs_cn38xx {
1421 #ifdef __BIG_ENDIAN_BITFIELD
1422         uint64_t reserved_32_63:32;
1423         uint64_t port_bit:32;
1424 #else
1425         uint64_t port_bit:32;
1426         uint64_t reserved_32_63:32;
1427 #endif
1428     } cn38xx;
1429 };
1430 
1431 union cvmx_ipd_sub_port_qos_cnt {
1432     uint64_t u64;
1433     struct cvmx_ipd_sub_port_qos_cnt_s {
1434 #ifdef __BIG_ENDIAN_BITFIELD
1435         uint64_t reserved_41_63:23;
1436         uint64_t port_qos:9;
1437         uint64_t cnt:32;
1438 #else
1439         uint64_t cnt:32;
1440         uint64_t port_qos:9;
1441         uint64_t reserved_41_63:23;
1442 #endif
1443     } s;
1444 };
1445 
1446 union cvmx_ipd_wqe_fpa_queue {
1447     uint64_t u64;
1448     struct cvmx_ipd_wqe_fpa_queue_s {
1449 #ifdef __BIG_ENDIAN_BITFIELD
1450         uint64_t reserved_3_63:61;
1451         uint64_t wqe_pool:3;
1452 #else
1453         uint64_t wqe_pool:3;
1454         uint64_t reserved_3_63:61;
1455 #endif
1456     } s;
1457 };
1458 
1459 union cvmx_ipd_wqe_ptr_valid {
1460     uint64_t u64;
1461     struct cvmx_ipd_wqe_ptr_valid_s {
1462 #ifdef __BIG_ENDIAN_BITFIELD
1463         uint64_t reserved_29_63:35;
1464         uint64_t ptr:29;
1465 #else
1466         uint64_t ptr:29;
1467         uint64_t reserved_29_63:35;
1468 #endif
1469     } s;
1470 };
1471 
1472 #endif
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