asm/octeon/cvmx-iob-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_IOB_DEFS_H__
0029 #define __CVMX_IOB_DEFS_H__
0030
0031 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
0032 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
0033 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
0034 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
0035 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
0036 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
0037 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
0038 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
0039 #define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
0040 #define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
0041 #define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
0042 #define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
0043 #define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
0044 #define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
0045 #define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
0046 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
0047 #define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
0048 #define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
0049 #define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
0050 #define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
0051 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
0052 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
0053 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
0054 #define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
0055 #define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
0056 #define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
0057 #define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
0058 #define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
0059 #define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
0060 #define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
0061 #define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
0062 #define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
0063 #define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
0064 #define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
0065
0066 union cvmx_iob_bist_status {
0067     uint64_t u64;
0068     struct cvmx_iob_bist_status_s {
0069 #ifdef __BIG_ENDIAN_BITFIELD
0070         uint64_t reserved_2_63:62;
0071         uint64_t ibd:1;
0072         uint64_t icd:1;
0073 #else
0074         uint64_t icd:1;
0075         uint64_t ibd:1;
0076         uint64_t reserved_2_63:62;
0077 #endif
0078     } s;
0079     struct cvmx_iob_bist_status_cn30xx {
0080 #ifdef __BIG_ENDIAN_BITFIELD
0081         uint64_t reserved_18_63:46;
0082         uint64_t icnrcb:1;
0083         uint64_t icr0:1;
0084         uint64_t icr1:1;
0085         uint64_t icnr1:1;
0086         uint64_t icnr0:1;
0087         uint64_t ibdr0:1;
0088         uint64_t ibdr1:1;
0089         uint64_t ibr0:1;
0090         uint64_t ibr1:1;
0091         uint64_t icnrt:1;
0092         uint64_t ibrq0:1;
0093         uint64_t ibrq1:1;
0094         uint64_t icrn0:1;
0095         uint64_t icrn1:1;
0096         uint64_t icrp0:1;
0097         uint64_t icrp1:1;
0098         uint64_t ibd:1;
0099         uint64_t icd:1;
0100 #else
0101         uint64_t icd:1;
0102         uint64_t ibd:1;
0103         uint64_t icrp1:1;
0104         uint64_t icrp0:1;
0105         uint64_t icrn1:1;
0106         uint64_t icrn0:1;
0107         uint64_t ibrq1:1;
0108         uint64_t ibrq0:1;
0109         uint64_t icnrt:1;
0110         uint64_t ibr1:1;
0111         uint64_t ibr0:1;
0112         uint64_t ibdr1:1;
0113         uint64_t ibdr0:1;
0114         uint64_t icnr0:1;
0115         uint64_t icnr1:1;
0116         uint64_t icr1:1;
0117         uint64_t icr0:1;
0118         uint64_t icnrcb:1;
0119         uint64_t reserved_18_63:46;
0120 #endif
0121     } cn30xx;
0122     struct cvmx_iob_bist_status_cn61xx {
0123 #ifdef __BIG_ENDIAN_BITFIELD
0124         uint64_t reserved_23_63:41;
0125         uint64_t xmdfif:1;
0126         uint64_t xmcfif:1;
0127         uint64_t iorfif:1;
0128         uint64_t rsdfif:1;
0129         uint64_t iocfif:1;
0130         uint64_t icnrcb:1;
0131         uint64_t icr0:1;
0132         uint64_t icr1:1;
0133         uint64_t icnr1:1;
0134         uint64_t icnr0:1;
0135         uint64_t ibdr0:1;
0136         uint64_t ibdr1:1;
0137         uint64_t ibr0:1;
0138         uint64_t ibr1:1;
0139         uint64_t icnrt:1;
0140         uint64_t ibrq0:1;
0141         uint64_t ibrq1:1;
0142         uint64_t icrn0:1;
0143         uint64_t icrn1:1;
0144         uint64_t icrp0:1;
0145         uint64_t icrp1:1;
0146         uint64_t ibd:1;
0147         uint64_t icd:1;
0148 #else
0149         uint64_t icd:1;
0150         uint64_t ibd:1;
0151         uint64_t icrp1:1;
0152         uint64_t icrp0:1;
0153         uint64_t icrn1:1;
0154         uint64_t icrn0:1;
0155         uint64_t ibrq1:1;
0156         uint64_t ibrq0:1;
0157         uint64_t icnrt:1;
0158         uint64_t ibr1:1;
0159         uint64_t ibr0:1;
0160         uint64_t ibdr1:1;
0161         uint64_t ibdr0:1;
0162         uint64_t icnr0:1;
0163         uint64_t icnr1:1;
0164         uint64_t icr1:1;
0165         uint64_t icr0:1;
0166         uint64_t icnrcb:1;
0167         uint64_t iocfif:1;
0168         uint64_t rsdfif:1;
0169         uint64_t iorfif:1;
0170         uint64_t xmcfif:1;
0171         uint64_t xmdfif:1;
0172         uint64_t reserved_23_63:41;
0173 #endif
0174     } cn61xx;
0175     struct cvmx_iob_bist_status_cn68xx {
0176 #ifdef __BIG_ENDIAN_BITFIELD
0177         uint64_t reserved_18_63:46;
0178         uint64_t xmdfif:1;
0179         uint64_t xmcfif:1;
0180         uint64_t iorfif:1;
0181         uint64_t rsdfif:1;
0182         uint64_t iocfif:1;
0183         uint64_t icnrcb:1;
0184         uint64_t icr0:1;
0185         uint64_t icr1:1;
0186         uint64_t icnr0:1;
0187         uint64_t ibr0:1;
0188         uint64_t ibr1:1;
0189         uint64_t icnrt:1;
0190         uint64_t ibrq0:1;
0191         uint64_t ibrq1:1;
0192         uint64_t icrn0:1;
0193         uint64_t icrn1:1;
0194         uint64_t ibd:1;
0195         uint64_t icd:1;
0196 #else
0197         uint64_t icd:1;
0198         uint64_t ibd:1;
0199         uint64_t icrn1:1;
0200         uint64_t icrn0:1;
0201         uint64_t ibrq1:1;
0202         uint64_t ibrq0:1;
0203         uint64_t icnrt:1;
0204         uint64_t ibr1:1;
0205         uint64_t ibr0:1;
0206         uint64_t icnr0:1;
0207         uint64_t icr1:1;
0208         uint64_t icr0:1;
0209         uint64_t icnrcb:1;
0210         uint64_t iocfif:1;
0211         uint64_t rsdfif:1;
0212         uint64_t iorfif:1;
0213         uint64_t xmcfif:1;
0214         uint64_t xmdfif:1;
0215         uint64_t reserved_18_63:46;
0216 #endif
0217     } cn68xx;
0218 };
0219
0220 union cvmx_iob_ctl_status {
0221     uint64_t u64;
0222     struct cvmx_iob_ctl_status_s {
0223 #ifdef __BIG_ENDIAN_BITFIELD
0224         uint64_t reserved_11_63:53;
0225         uint64_t fif_dly:1;
0226         uint64_t xmc_per:4;
0227         uint64_t reserved_5_5:1;
0228         uint64_t outb_mat:1;
0229         uint64_t inb_mat:1;
0230         uint64_t pko_enb:1;
0231         uint64_t dwb_enb:1;
0232         uint64_t fau_end:1;
0233 #else
0234         uint64_t fau_end:1;
0235         uint64_t dwb_enb:1;
0236         uint64_t pko_enb:1;
0237         uint64_t inb_mat:1;
0238         uint64_t outb_mat:1;
0239         uint64_t reserved_5_5:1;
0240         uint64_t xmc_per:4;
0241         uint64_t fif_dly:1;
0242         uint64_t reserved_11_63:53;
0243 #endif
0244     } s;
0245     struct cvmx_iob_ctl_status_cn30xx {
0246 #ifdef __BIG_ENDIAN_BITFIELD
0247         uint64_t reserved_5_63:59;
0248         uint64_t outb_mat:1;
0249         uint64_t inb_mat:1;
0250         uint64_t pko_enb:1;
0251         uint64_t dwb_enb:1;
0252         uint64_t fau_end:1;
0253 #else
0254         uint64_t fau_end:1;
0255         uint64_t dwb_enb:1;
0256         uint64_t pko_enb:1;
0257         uint64_t inb_mat:1;
0258         uint64_t outb_mat:1;
0259         uint64_t reserved_5_63:59;
0260 #endif
0261     } cn30xx;
0262     struct cvmx_iob_ctl_status_cn52xx {
0263 #ifdef __BIG_ENDIAN_BITFIELD
0264         uint64_t reserved_6_63:58;
0265         uint64_t rr_mode:1;
0266         uint64_t outb_mat:1;
0267         uint64_t inb_mat:1;
0268         uint64_t pko_enb:1;
0269         uint64_t dwb_enb:1;
0270         uint64_t fau_end:1;
0271 #else
0272         uint64_t fau_end:1;
0273         uint64_t dwb_enb:1;
0274         uint64_t pko_enb:1;
0275         uint64_t inb_mat:1;
0276         uint64_t outb_mat:1;
0277         uint64_t rr_mode:1;
0278         uint64_t reserved_6_63:58;
0279 #endif
0280     } cn52xx;
0281     struct cvmx_iob_ctl_status_cn61xx {
0282 #ifdef __BIG_ENDIAN_BITFIELD
0283         uint64_t reserved_11_63:53;
0284         uint64_t fif_dly:1;
0285         uint64_t xmc_per:4;
0286         uint64_t rr_mode:1;
0287         uint64_t outb_mat:1;
0288         uint64_t inb_mat:1;
0289         uint64_t pko_enb:1;
0290         uint64_t dwb_enb:1;
0291         uint64_t fau_end:1;
0292 #else
0293         uint64_t fau_end:1;
0294         uint64_t dwb_enb:1;
0295         uint64_t pko_enb:1;
0296         uint64_t inb_mat:1;
0297         uint64_t outb_mat:1;
0298         uint64_t rr_mode:1;
0299         uint64_t xmc_per:4;
0300         uint64_t fif_dly:1;
0301         uint64_t reserved_11_63:53;
0302 #endif
0303     } cn61xx;
0304     struct cvmx_iob_ctl_status_cn63xx {
0305 #ifdef __BIG_ENDIAN_BITFIELD
0306         uint64_t reserved_10_63:54;
0307         uint64_t xmc_per:4;
0308         uint64_t rr_mode:1;
0309         uint64_t outb_mat:1;
0310         uint64_t inb_mat:1;
0311         uint64_t pko_enb:1;
0312         uint64_t dwb_enb:1;
0313         uint64_t fau_end:1;
0314 #else
0315         uint64_t fau_end:1;
0316         uint64_t dwb_enb:1;
0317         uint64_t pko_enb:1;
0318         uint64_t inb_mat:1;
0319         uint64_t outb_mat:1;
0320         uint64_t rr_mode:1;
0321         uint64_t xmc_per:4;
0322         uint64_t reserved_10_63:54;
0323 #endif
0324     } cn63xx;
0325     struct cvmx_iob_ctl_status_cn68xx {
0326 #ifdef __BIG_ENDIAN_BITFIELD
0327         uint64_t reserved_11_63:53;
0328         uint64_t fif_dly:1;
0329         uint64_t xmc_per:4;
0330         uint64_t rsvr5:1;
0331         uint64_t outb_mat:1;
0332         uint64_t inb_mat:1;
0333         uint64_t pko_enb:1;
0334         uint64_t dwb_enb:1;
0335         uint64_t fau_end:1;
0336 #else
0337         uint64_t fau_end:1;
0338         uint64_t dwb_enb:1;
0339         uint64_t pko_enb:1;
0340         uint64_t inb_mat:1;
0341         uint64_t outb_mat:1;
0342         uint64_t rsvr5:1;
0343         uint64_t xmc_per:4;
0344         uint64_t fif_dly:1;
0345         uint64_t reserved_11_63:53;
0346 #endif
0347     } cn68xx;
0348 };
0349
0350 union cvmx_iob_dwb_pri_cnt {
0351     uint64_t u64;
0352     struct cvmx_iob_dwb_pri_cnt_s {
0353 #ifdef __BIG_ENDIAN_BITFIELD
0354         uint64_t reserved_16_63:48;
0355         uint64_t cnt_enb:1;
0356         uint64_t cnt_val:15;
0357 #else
0358         uint64_t cnt_val:15;
0359         uint64_t cnt_enb:1;
0360         uint64_t reserved_16_63:48;
0361 #endif
0362     } s;
0363 };
0364
0365 union cvmx_iob_fau_timeout {
0366     uint64_t u64;
0367     struct cvmx_iob_fau_timeout_s {
0368 #ifdef __BIG_ENDIAN_BITFIELD
0369         uint64_t reserved_13_63:51;
0370         uint64_t tout_enb:1;
0371         uint64_t tout_val:12;
0372 #else
0373         uint64_t tout_val:12;
0374         uint64_t tout_enb:1;
0375         uint64_t reserved_13_63:51;
0376 #endif
0377     } s;
0378 };
0379
0380 union cvmx_iob_i2c_pri_cnt {
0381     uint64_t u64;
0382     struct cvmx_iob_i2c_pri_cnt_s {
0383 #ifdef __BIG_ENDIAN_BITFIELD
0384         uint64_t reserved_16_63:48;
0385         uint64_t cnt_enb:1;
0386         uint64_t cnt_val:15;
0387 #else
0388         uint64_t cnt_val:15;
0389         uint64_t cnt_enb:1;
0390         uint64_t reserved_16_63:48;
0391 #endif
0392     } s;
0393 };
0394
0395 union cvmx_iob_inb_control_match {
0396     uint64_t u64;
0397     struct cvmx_iob_inb_control_match_s {
0398 #ifdef __BIG_ENDIAN_BITFIELD
0399         uint64_t reserved_29_63:35;
0400         uint64_t mask:8;
0401         uint64_t opc:4;
0402         uint64_t dst:9;
0403         uint64_t src:8;
0404 #else
0405         uint64_t src:8;
0406         uint64_t dst:9;
0407         uint64_t opc:4;
0408         uint64_t mask:8;
0409         uint64_t reserved_29_63:35;
0410 #endif
0411     } s;
0412 };
0413
0414 union cvmx_iob_inb_control_match_enb {
0415     uint64_t u64;
0416     struct cvmx_iob_inb_control_match_enb_s {
0417 #ifdef __BIG_ENDIAN_BITFIELD
0418         uint64_t reserved_29_63:35;
0419         uint64_t mask:8;
0420         uint64_t opc:4;
0421         uint64_t dst:9;
0422         uint64_t src:8;
0423 #else
0424         uint64_t src:8;
0425         uint64_t dst:9;
0426         uint64_t opc:4;
0427         uint64_t mask:8;
0428         uint64_t reserved_29_63:35;
0429 #endif
0430     } s;
0431 };
0432
0433 union cvmx_iob_inb_data_match {
0434     uint64_t u64;
0435     struct cvmx_iob_inb_data_match_s {
0436 #ifdef __BIG_ENDIAN_BITFIELD
0437         uint64_t data:64;
0438 #else
0439         uint64_t data:64;
0440 #endif
0441     } s;
0442 };
0443
0444 union cvmx_iob_inb_data_match_enb {
0445     uint64_t u64;
0446     struct cvmx_iob_inb_data_match_enb_s {
0447 #ifdef __BIG_ENDIAN_BITFIELD
0448         uint64_t data:64;
0449 #else
0450         uint64_t data:64;
0451 #endif
0452     } s;
0453 };
0454
0455 union cvmx_iob_int_enb {
0456     uint64_t u64;
0457     struct cvmx_iob_int_enb_s {
0458 #ifdef __BIG_ENDIAN_BITFIELD
0459         uint64_t reserved_6_63:58;
0460         uint64_t p_dat:1;
0461         uint64_t np_dat:1;
0462         uint64_t p_eop:1;
0463         uint64_t p_sop:1;
0464         uint64_t np_eop:1;
0465         uint64_t np_sop:1;
0466 #else
0467         uint64_t np_sop:1;
0468         uint64_t np_eop:1;
0469         uint64_t p_sop:1;
0470         uint64_t p_eop:1;
0471         uint64_t np_dat:1;
0472         uint64_t p_dat:1;
0473         uint64_t reserved_6_63:58;
0474 #endif
0475     } s;
0476     struct cvmx_iob_int_enb_cn30xx {
0477 #ifdef __BIG_ENDIAN_BITFIELD
0478         uint64_t reserved_4_63:60;
0479         uint64_t p_eop:1;
0480         uint64_t p_sop:1;
0481         uint64_t np_eop:1;
0482         uint64_t np_sop:1;
0483 #else
0484         uint64_t np_sop:1;
0485         uint64_t np_eop:1;
0486         uint64_t p_sop:1;
0487         uint64_t p_eop:1;
0488         uint64_t reserved_4_63:60;
0489 #endif
0490     } cn30xx;
0491     struct cvmx_iob_int_enb_cn68xx {
0492 #ifdef __BIG_ENDIAN_BITFIELD
0493         uint64_t reserved_0_63:64;
0494 #else
0495         uint64_t reserved_0_63:64;
0496 #endif
0497     } cn68xx;
0498 };
0499
0500 union cvmx_iob_int_sum {
0501     uint64_t u64;
0502     struct cvmx_iob_int_sum_s {
0503 #ifdef __BIG_ENDIAN_BITFIELD
0504         uint64_t reserved_6_63:58;
0505         uint64_t p_dat:1;
0506         uint64_t np_dat:1;
0507         uint64_t p_eop:1;
0508         uint64_t p_sop:1;
0509         uint64_t np_eop:1;
0510         uint64_t np_sop:1;
0511 #else
0512         uint64_t np_sop:1;
0513         uint64_t np_eop:1;
0514         uint64_t p_sop:1;
0515         uint64_t p_eop:1;
0516         uint64_t np_dat:1;
0517         uint64_t p_dat:1;
0518         uint64_t reserved_6_63:58;
0519 #endif
0520     } s;
0521     struct cvmx_iob_int_sum_cn30xx {
0522 #ifdef __BIG_ENDIAN_BITFIELD
0523         uint64_t reserved_4_63:60;
0524         uint64_t p_eop:1;
0525         uint64_t p_sop:1;
0526         uint64_t np_eop:1;
0527         uint64_t np_sop:1;
0528 #else
0529         uint64_t np_sop:1;
0530         uint64_t np_eop:1;
0531         uint64_t p_sop:1;
0532         uint64_t p_eop:1;
0533         uint64_t reserved_4_63:60;
0534 #endif
0535     } cn30xx;
0536     struct cvmx_iob_int_sum_cn68xx {
0537 #ifdef __BIG_ENDIAN_BITFIELD
0538         uint64_t reserved_0_63:64;
0539 #else
0540         uint64_t reserved_0_63:64;
0541 #endif
0542     } cn68xx;
0543 };
0544
0545 union cvmx_iob_n2c_l2c_pri_cnt {
0546     uint64_t u64;
0547     struct cvmx_iob_n2c_l2c_pri_cnt_s {
0548 #ifdef __BIG_ENDIAN_BITFIELD
0549         uint64_t reserved_16_63:48;
0550         uint64_t cnt_enb:1;
0551         uint64_t cnt_val:15;
0552 #else
0553         uint64_t cnt_val:15;
0554         uint64_t cnt_enb:1;
0555         uint64_t reserved_16_63:48;
0556 #endif
0557     } s;
0558 };
0559
0560 union cvmx_iob_n2c_rsp_pri_cnt {
0561     uint64_t u64;
0562     struct cvmx_iob_n2c_rsp_pri_cnt_s {
0563 #ifdef __BIG_ENDIAN_BITFIELD
0564         uint64_t reserved_16_63:48;
0565         uint64_t cnt_enb:1;
0566         uint64_t cnt_val:15;
0567 #else
0568         uint64_t cnt_val:15;
0569         uint64_t cnt_enb:1;
0570         uint64_t reserved_16_63:48;
0571 #endif
0572     } s;
0573 };
0574
0575 union cvmx_iob_outb_com_pri_cnt {
0576     uint64_t u64;
0577     struct cvmx_iob_outb_com_pri_cnt_s {
0578 #ifdef __BIG_ENDIAN_BITFIELD
0579         uint64_t reserved_16_63:48;
0580         uint64_t cnt_enb:1;
0581         uint64_t cnt_val:15;
0582 #else
0583         uint64_t cnt_val:15;
0584         uint64_t cnt_enb:1;
0585         uint64_t reserved_16_63:48;
0586 #endif
0587     } s;
0588 };
0589
0590 union cvmx_iob_outb_control_match {
0591     uint64_t u64;
0592     struct cvmx_iob_outb_control_match_s {
0593 #ifdef __BIG_ENDIAN_BITFIELD
0594         uint64_t reserved_26_63:38;
0595         uint64_t mask:8;
0596         uint64_t eot:1;
0597         uint64_t dst:8;
0598         uint64_t src:9;
0599 #else
0600         uint64_t src:9;
0601         uint64_t dst:8;
0602         uint64_t eot:1;
0603         uint64_t mask:8;
0604         uint64_t reserved_26_63:38;
0605 #endif
0606     } s;
0607 };
0608
0609 union cvmx_iob_outb_control_match_enb {
0610     uint64_t u64;
0611     struct cvmx_iob_outb_control_match_enb_s {
0612 #ifdef __BIG_ENDIAN_BITFIELD
0613         uint64_t reserved_26_63:38;
0614         uint64_t mask:8;
0615         uint64_t eot:1;
0616         uint64_t dst:8;
0617         uint64_t src:9;
0618 #else
0619         uint64_t src:9;
0620         uint64_t dst:8;
0621         uint64_t eot:1;
0622         uint64_t mask:8;
0623         uint64_t reserved_26_63:38;
0624 #endif
0625     } s;
0626 };
0627
0628 union cvmx_iob_outb_data_match {
0629     uint64_t u64;
0630     struct cvmx_iob_outb_data_match_s {
0631 #ifdef __BIG_ENDIAN_BITFIELD
0632         uint64_t data:64;
0633 #else
0634         uint64_t data:64;
0635 #endif
0636     } s;
0637 };
0638
0639 union cvmx_iob_outb_data_match_enb {
0640     uint64_t u64;
0641     struct cvmx_iob_outb_data_match_enb_s {
0642 #ifdef __BIG_ENDIAN_BITFIELD
0643         uint64_t data:64;
0644 #else
0645         uint64_t data:64;
0646 #endif
0647     } s;
0648 };
0649
0650 union cvmx_iob_outb_fpa_pri_cnt {
0651     uint64_t u64;
0652     struct cvmx_iob_outb_fpa_pri_cnt_s {
0653 #ifdef __BIG_ENDIAN_BITFIELD
0654         uint64_t reserved_16_63:48;
0655         uint64_t cnt_enb:1;
0656         uint64_t cnt_val:15;
0657 #else
0658         uint64_t cnt_val:15;
0659         uint64_t cnt_enb:1;
0660         uint64_t reserved_16_63:48;
0661 #endif
0662     } s;
0663 };
0664
0665 union cvmx_iob_outb_req_pri_cnt {
0666     uint64_t u64;
0667     struct cvmx_iob_outb_req_pri_cnt_s {
0668 #ifdef __BIG_ENDIAN_BITFIELD
0669         uint64_t reserved_16_63:48;
0670         uint64_t cnt_enb:1;
0671         uint64_t cnt_val:15;
0672 #else
0673         uint64_t cnt_val:15;
0674         uint64_t cnt_enb:1;
0675         uint64_t reserved_16_63:48;
0676 #endif
0677     } s;
0678 };
0679
0680 union cvmx_iob_p2c_req_pri_cnt {
0681     uint64_t u64;
0682     struct cvmx_iob_p2c_req_pri_cnt_s {
0683 #ifdef __BIG_ENDIAN_BITFIELD
0684         uint64_t reserved_16_63:48;
0685         uint64_t cnt_enb:1;
0686         uint64_t cnt_val:15;
0687 #else
0688         uint64_t cnt_val:15;
0689         uint64_t cnt_enb:1;
0690         uint64_t reserved_16_63:48;
0691 #endif
0692     } s;
0693 };
0694
0695 union cvmx_iob_pkt_err {
0696     uint64_t u64;
0697     struct cvmx_iob_pkt_err_s {
0698 #ifdef __BIG_ENDIAN_BITFIELD
0699         uint64_t reserved_12_63:52;
0700         uint64_t vport:6;
0701         uint64_t port:6;
0702 #else
0703         uint64_t port:6;
0704         uint64_t vport:6;
0705         uint64_t reserved_12_63:52;
0706 #endif
0707     } s;
0708     struct cvmx_iob_pkt_err_cn30xx {
0709 #ifdef __BIG_ENDIAN_BITFIELD
0710         uint64_t reserved_6_63:58;
0711         uint64_t port:6;
0712 #else
0713         uint64_t port:6;
0714         uint64_t reserved_6_63:58;
0715 #endif
0716     } cn30xx;
0717 };
0718
0719 union cvmx_iob_to_cmb_credits {
0720     uint64_t u64;
0721     struct cvmx_iob_to_cmb_credits_s {
0722 #ifdef __BIG_ENDIAN_BITFIELD
0723         uint64_t reserved_6_63:58;
0724         uint64_t ncb_rd:3;
0725         uint64_t ncb_wr:3;
0726 #else
0727         uint64_t ncb_wr:3;
0728         uint64_t ncb_rd:3;
0729         uint64_t reserved_6_63:58;
0730 #endif
0731     } s;
0732     struct cvmx_iob_to_cmb_credits_cn52xx {
0733 #ifdef __BIG_ENDIAN_BITFIELD
0734         uint64_t reserved_9_63:55;
0735         uint64_t pko_rd:3;
0736         uint64_t ncb_rd:3;
0737         uint64_t ncb_wr:3;
0738 #else
0739         uint64_t ncb_wr:3;
0740         uint64_t ncb_rd:3;
0741         uint64_t pko_rd:3;
0742         uint64_t reserved_9_63:55;
0743 #endif
0744     } cn52xx;
0745     struct cvmx_iob_to_cmb_credits_cn68xx {
0746 #ifdef __BIG_ENDIAN_BITFIELD
0747         uint64_t reserved_9_63:55;
0748         uint64_t dwb:3;
0749         uint64_t ncb_rd:3;
0750         uint64_t ncb_wr:3;
0751 #else
0752         uint64_t ncb_wr:3;
0753         uint64_t ncb_rd:3;
0754         uint64_t dwb:3;
0755         uint64_t reserved_9_63:55;
0756 #endif
0757     } cn68xx;
0758 };
0759
0760 union cvmx_iob_to_ncb_did_00_credits {
0761     uint64_t u64;
0762     struct cvmx_iob_to_ncb_did_00_credits_s {
0763 #ifdef __BIG_ENDIAN_BITFIELD
0764         uint64_t reserved_7_63:57;
0765         uint64_t crd:7;
0766 #else
0767         uint64_t crd:7;
0768         uint64_t reserved_7_63:57;
0769 #endif
0770     } s;
0771 };
0772
0773 union cvmx_iob_to_ncb_did_111_credits {
0774     uint64_t u64;
0775     struct cvmx_iob_to_ncb_did_111_credits_s {
0776 #ifdef __BIG_ENDIAN_BITFIELD
0777         uint64_t reserved_7_63:57;
0778         uint64_t crd:7;
0779 #else
0780         uint64_t crd:7;
0781         uint64_t reserved_7_63:57;
0782 #endif
0783     } s;
0784 };
0785
0786 union cvmx_iob_to_ncb_did_223_credits {
0787     uint64_t u64;
0788     struct cvmx_iob_to_ncb_did_223_credits_s {
0789 #ifdef __BIG_ENDIAN_BITFIELD
0790         uint64_t reserved_7_63:57;
0791         uint64_t crd:7;
0792 #else
0793         uint64_t crd:7;
0794         uint64_t reserved_7_63:57;
0795 #endif
0796     } s;
0797 };
0798
0799 union cvmx_iob_to_ncb_did_24_credits {
0800     uint64_t u64;
0801     struct cvmx_iob_to_ncb_did_24_credits_s {
0802 #ifdef __BIG_ENDIAN_BITFIELD
0803         uint64_t reserved_7_63:57;
0804         uint64_t crd:7;
0805 #else
0806         uint64_t crd:7;
0807         uint64_t reserved_7_63:57;
0808 #endif
0809     } s;
0810 };
0811
0812 union cvmx_iob_to_ncb_did_32_credits {
0813     uint64_t u64;
0814     struct cvmx_iob_to_ncb_did_32_credits_s {
0815 #ifdef __BIG_ENDIAN_BITFIELD
0816         uint64_t reserved_7_63:57;
0817         uint64_t crd:7;
0818 #else
0819         uint64_t crd:7;
0820         uint64_t reserved_7_63:57;
0821 #endif
0822     } s;
0823 };
0824
0825 union cvmx_iob_to_ncb_did_40_credits {
0826     uint64_t u64;
0827     struct cvmx_iob_to_ncb_did_40_credits_s {
0828 #ifdef __BIG_ENDIAN_BITFIELD
0829         uint64_t reserved_7_63:57;
0830         uint64_t crd:7;
0831 #else
0832         uint64_t crd:7;
0833         uint64_t reserved_7_63:57;
0834 #endif
0835     } s;
0836 };
0837
0838 union cvmx_iob_to_ncb_did_55_credits {
0839     uint64_t u64;
0840     struct cvmx_iob_to_ncb_did_55_credits_s {
0841 #ifdef __BIG_ENDIAN_BITFIELD
0842         uint64_t reserved_7_63:57;
0843         uint64_t crd:7;
0844 #else
0845         uint64_t crd:7;
0846         uint64_t reserved_7_63:57;
0847 #endif
0848     } s;
0849 };
0850
0851 union cvmx_iob_to_ncb_did_64_credits {
0852     uint64_t u64;
0853     struct cvmx_iob_to_ncb_did_64_credits_s {
0854 #ifdef __BIG_ENDIAN_BITFIELD
0855         uint64_t reserved_7_63:57;
0856         uint64_t crd:7;
0857 #else
0858         uint64_t crd:7;
0859         uint64_t reserved_7_63:57;
0860 #endif
0861     } s;
0862 };
0863
0864 union cvmx_iob_to_ncb_did_79_credits {
0865     uint64_t u64;
0866     struct cvmx_iob_to_ncb_did_79_credits_s {
0867 #ifdef __BIG_ENDIAN_BITFIELD
0868         uint64_t reserved_7_63:57;
0869         uint64_t crd:7;
0870 #else
0871         uint64_t crd:7;
0872         uint64_t reserved_7_63:57;
0873 #endif
0874     } s;
0875 };
0876
0877 union cvmx_iob_to_ncb_did_96_credits {
0878     uint64_t u64;
0879     struct cvmx_iob_to_ncb_did_96_credits_s {
0880 #ifdef __BIG_ENDIAN_BITFIELD
0881         uint64_t reserved_7_63:57;
0882         uint64_t crd:7;
0883 #else
0884         uint64_t crd:7;
0885         uint64_t reserved_7_63:57;
0886 #endif
0887     } s;
0888 };
0889
0890 union cvmx_iob_to_ncb_did_98_credits {
0891     uint64_t u64;
0892     struct cvmx_iob_to_ncb_did_98_credits_s {
0893 #ifdef __BIG_ENDIAN_BITFIELD
0894         uint64_t reserved_7_63:57;
0895         uint64_t crd:7;
0896 #else
0897         uint64_t crd:7;
0898         uint64_t reserved_7_63:57;
0899 #endif
0900     } s;
0901 };
0902
0903 #endif