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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_GPIO_DEFS_H__
0029 #define __CVMX_GPIO_DEFS_H__
0030 
0031 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
0032 #define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
0033 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
0034 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
0035 #define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
0036 #define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
0037 #define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
0038 #define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
0039 #define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
0040 #define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
0041 #define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
0042 #define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
0043 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
0044 
0045 union cvmx_gpio_bit_cfgx {
0046     uint64_t u64;
0047     struct cvmx_gpio_bit_cfgx_s {
0048 #ifdef __BIG_ENDIAN_BITFIELD
0049         uint64_t reserved_21_63:42;
0050         uint64_t output_sel:5;
0051         uint64_t synce_sel:2;
0052         uint64_t clk_gen:1;
0053         uint64_t clk_sel:2;
0054         uint64_t fil_sel:4;
0055         uint64_t fil_cnt:4;
0056         uint64_t int_type:1;
0057         uint64_t int_en:1;
0058         uint64_t rx_xor:1;
0059         uint64_t tx_oe:1;
0060 #else
0061         uint64_t tx_oe:1;
0062         uint64_t rx_xor:1;
0063         uint64_t int_en:1;
0064         uint64_t int_type:1;
0065         uint64_t fil_cnt:4;
0066         uint64_t fil_sel:4;
0067         uint64_t clk_sel:2;
0068         uint64_t clk_gen:1;
0069         uint64_t synce_sel:2;
0070         uint64_t output_sel:5;
0071         uint64_t reserved_21_63:42;
0072 #endif
0073     } s;
0074     struct cvmx_gpio_bit_cfgx_cn30xx {
0075 #ifdef __BIG_ENDIAN_BITFIELD
0076         uint64_t reserved_12_63:52;
0077         uint64_t fil_sel:4;
0078         uint64_t fil_cnt:4;
0079         uint64_t int_type:1;
0080         uint64_t int_en:1;
0081         uint64_t rx_xor:1;
0082         uint64_t tx_oe:1;
0083 #else
0084         uint64_t tx_oe:1;
0085         uint64_t rx_xor:1;
0086         uint64_t int_en:1;
0087         uint64_t int_type:1;
0088         uint64_t fil_cnt:4;
0089         uint64_t fil_sel:4;
0090         uint64_t reserved_12_63:52;
0091 #endif
0092     } cn30xx;
0093     struct cvmx_gpio_bit_cfgx_cn52xx {
0094 #ifdef __BIG_ENDIAN_BITFIELD
0095         uint64_t reserved_15_63:49;
0096         uint64_t clk_gen:1;
0097         uint64_t clk_sel:2;
0098         uint64_t fil_sel:4;
0099         uint64_t fil_cnt:4;
0100         uint64_t int_type:1;
0101         uint64_t int_en:1;
0102         uint64_t rx_xor:1;
0103         uint64_t tx_oe:1;
0104 #else
0105         uint64_t tx_oe:1;
0106         uint64_t rx_xor:1;
0107         uint64_t int_en:1;
0108         uint64_t int_type:1;
0109         uint64_t fil_cnt:4;
0110         uint64_t fil_sel:4;
0111         uint64_t clk_sel:2;
0112         uint64_t clk_gen:1;
0113         uint64_t reserved_15_63:49;
0114 #endif
0115     } cn52xx;
0116 };
0117 
0118 union cvmx_gpio_boot_ena {
0119     uint64_t u64;
0120     struct cvmx_gpio_boot_ena_s {
0121 #ifdef __BIG_ENDIAN_BITFIELD
0122         uint64_t reserved_12_63:52;
0123         uint64_t boot_ena:4;
0124         uint64_t reserved_0_7:8;
0125 #else
0126         uint64_t reserved_0_7:8;
0127         uint64_t boot_ena:4;
0128         uint64_t reserved_12_63:52;
0129 #endif
0130     } s;
0131 };
0132 
0133 union cvmx_gpio_clk_genx {
0134     uint64_t u64;
0135     struct cvmx_gpio_clk_genx_s {
0136 #ifdef __BIG_ENDIAN_BITFIELD
0137         uint64_t reserved_32_63:32;
0138         uint64_t n:32;
0139 #else
0140         uint64_t n:32;
0141         uint64_t reserved_32_63:32;
0142 #endif
0143     } s;
0144 };
0145 
0146 union cvmx_gpio_clk_qlmx {
0147     uint64_t u64;
0148     struct cvmx_gpio_clk_qlmx_s {
0149 #ifdef __BIG_ENDIAN_BITFIELD
0150         uint64_t reserved_11_63:53;
0151         uint64_t qlm_sel:3;
0152         uint64_t reserved_3_7:5;
0153         uint64_t div:1;
0154         uint64_t lane_sel:2;
0155 #else
0156         uint64_t lane_sel:2;
0157         uint64_t div:1;
0158         uint64_t reserved_3_7:5;
0159         uint64_t qlm_sel:3;
0160         uint64_t reserved_11_63:53;
0161 #endif
0162     } s;
0163     struct cvmx_gpio_clk_qlmx_cn61xx {
0164 #ifdef __BIG_ENDIAN_BITFIELD
0165         uint64_t reserved_10_63:54;
0166         uint64_t qlm_sel:2;
0167         uint64_t reserved_3_7:5;
0168         uint64_t div:1;
0169         uint64_t lane_sel:2;
0170 #else
0171         uint64_t lane_sel:2;
0172         uint64_t div:1;
0173         uint64_t reserved_3_7:5;
0174         uint64_t qlm_sel:2;
0175         uint64_t reserved_10_63:54;
0176 #endif
0177     } cn61xx;
0178     struct cvmx_gpio_clk_qlmx_cn63xx {
0179 #ifdef __BIG_ENDIAN_BITFIELD
0180         uint64_t reserved_3_63:61;
0181         uint64_t div:1;
0182         uint64_t lane_sel:2;
0183 #else
0184         uint64_t lane_sel:2;
0185         uint64_t div:1;
0186         uint64_t reserved_3_63:61;
0187 #endif
0188     } cn63xx;
0189 };
0190 
0191 union cvmx_gpio_dbg_ena {
0192     uint64_t u64;
0193     struct cvmx_gpio_dbg_ena_s {
0194 #ifdef __BIG_ENDIAN_BITFIELD
0195         uint64_t reserved_21_63:43;
0196         uint64_t dbg_ena:21;
0197 #else
0198         uint64_t dbg_ena:21;
0199         uint64_t reserved_21_63:43;
0200 #endif
0201     } s;
0202 };
0203 
0204 union cvmx_gpio_int_clr {
0205     uint64_t u64;
0206     struct cvmx_gpio_int_clr_s {
0207 #ifdef __BIG_ENDIAN_BITFIELD
0208         uint64_t reserved_16_63:48;
0209         uint64_t type:16;
0210 #else
0211         uint64_t type:16;
0212         uint64_t reserved_16_63:48;
0213 #endif
0214     } s;
0215 };
0216 
0217 union cvmx_gpio_multi_cast {
0218     uint64_t u64;
0219     struct cvmx_gpio_multi_cast_s {
0220 #ifdef __BIG_ENDIAN_BITFIELD
0221         uint64_t reserved_1_63:63;
0222         uint64_t en:1;
0223 #else
0224         uint64_t en:1;
0225         uint64_t reserved_1_63:63;
0226 #endif
0227     } s;
0228 };
0229 
0230 union cvmx_gpio_pin_ena {
0231     uint64_t u64;
0232     struct cvmx_gpio_pin_ena_s {
0233 #ifdef __BIG_ENDIAN_BITFIELD
0234         uint64_t reserved_20_63:44;
0235         uint64_t ena19:1;
0236         uint64_t ena18:1;
0237         uint64_t reserved_0_17:18;
0238 #else
0239         uint64_t reserved_0_17:18;
0240         uint64_t ena18:1;
0241         uint64_t ena19:1;
0242         uint64_t reserved_20_63:44;
0243 #endif
0244     } s;
0245 };
0246 
0247 union cvmx_gpio_rx_dat {
0248     uint64_t u64;
0249     struct cvmx_gpio_rx_dat_s {
0250 #ifdef __BIG_ENDIAN_BITFIELD
0251         uint64_t reserved_24_63:40;
0252         uint64_t dat:24;
0253 #else
0254         uint64_t dat:24;
0255         uint64_t reserved_24_63:40;
0256 #endif
0257     } s;
0258     struct cvmx_gpio_rx_dat_cn38xx {
0259 #ifdef __BIG_ENDIAN_BITFIELD
0260         uint64_t reserved_16_63:48;
0261         uint64_t dat:16;
0262 #else
0263         uint64_t dat:16;
0264         uint64_t reserved_16_63:48;
0265 #endif
0266     } cn38xx;
0267     struct cvmx_gpio_rx_dat_cn61xx {
0268 #ifdef __BIG_ENDIAN_BITFIELD
0269         uint64_t reserved_20_63:44;
0270         uint64_t dat:20;
0271 #else
0272         uint64_t dat:20;
0273         uint64_t reserved_20_63:44;
0274 #endif
0275     } cn61xx;
0276 };
0277 
0278 union cvmx_gpio_tim_ctl {
0279     uint64_t u64;
0280     struct cvmx_gpio_tim_ctl_s {
0281 #ifdef __BIG_ENDIAN_BITFIELD
0282         uint64_t reserved_4_63:60;
0283         uint64_t sel:4;
0284 #else
0285         uint64_t sel:4;
0286         uint64_t reserved_4_63:60;
0287 #endif
0288     } s;
0289 };
0290 
0291 union cvmx_gpio_tx_clr {
0292     uint64_t u64;
0293     struct cvmx_gpio_tx_clr_s {
0294 #ifdef __BIG_ENDIAN_BITFIELD
0295         uint64_t reserved_24_63:40;
0296         uint64_t clr:24;
0297 #else
0298         uint64_t clr:24;
0299         uint64_t reserved_24_63:40;
0300 #endif
0301     } s;
0302     struct cvmx_gpio_tx_clr_cn38xx {
0303 #ifdef __BIG_ENDIAN_BITFIELD
0304         uint64_t reserved_16_63:48;
0305         uint64_t clr:16;
0306 #else
0307         uint64_t clr:16;
0308         uint64_t reserved_16_63:48;
0309 #endif
0310     } cn38xx;
0311     struct cvmx_gpio_tx_clr_cn61xx {
0312 #ifdef __BIG_ENDIAN_BITFIELD
0313         uint64_t reserved_20_63:44;
0314         uint64_t clr:20;
0315 #else
0316         uint64_t clr:20;
0317         uint64_t reserved_20_63:44;
0318 #endif
0319     } cn61xx;
0320 };
0321 
0322 union cvmx_gpio_tx_set {
0323     uint64_t u64;
0324     struct cvmx_gpio_tx_set_s {
0325 #ifdef __BIG_ENDIAN_BITFIELD
0326         uint64_t reserved_24_63:40;
0327         uint64_t set:24;
0328 #else
0329         uint64_t set:24;
0330         uint64_t reserved_24_63:40;
0331 #endif
0332     } s;
0333     struct cvmx_gpio_tx_set_cn38xx {
0334 #ifdef __BIG_ENDIAN_BITFIELD
0335         uint64_t reserved_16_63:48;
0336         uint64_t set:16;
0337 #else
0338         uint64_t set:16;
0339         uint64_t reserved_16_63:48;
0340 #endif
0341     } cn38xx;
0342     struct cvmx_gpio_tx_set_cn61xx {
0343 #ifdef __BIG_ENDIAN_BITFIELD
0344         uint64_t reserved_20_63:44;
0345         uint64_t set:20;
0346 #else
0347         uint64_t set:20;
0348         uint64_t reserved_20_63:44;
0349 #endif
0350     } cn61xx;
0351 };
0352 
0353 union cvmx_gpio_xbit_cfgx {
0354     uint64_t u64;
0355     struct cvmx_gpio_xbit_cfgx_s {
0356 #ifdef __BIG_ENDIAN_BITFIELD
0357         uint64_t reserved_17_63:47;
0358         uint64_t synce_sel:2;
0359         uint64_t clk_gen:1;
0360         uint64_t clk_sel:2;
0361         uint64_t fil_sel:4;
0362         uint64_t fil_cnt:4;
0363         uint64_t int_type:1;
0364         uint64_t int_en:1;
0365         uint64_t rx_xor:1;
0366         uint64_t tx_oe:1;
0367 #else
0368         uint64_t tx_oe:1;
0369         uint64_t rx_xor:1;
0370         uint64_t int_en:1;
0371         uint64_t int_type:1;
0372         uint64_t fil_cnt:4;
0373         uint64_t fil_sel:4;
0374         uint64_t clk_sel:2;
0375         uint64_t clk_gen:1;
0376         uint64_t synce_sel:2;
0377         uint64_t reserved_17_63:47;
0378 #endif
0379     } s;
0380     struct cvmx_gpio_xbit_cfgx_cn30xx {
0381 #ifdef __BIG_ENDIAN_BITFIELD
0382         uint64_t reserved_12_63:52;
0383         uint64_t fil_sel:4;
0384         uint64_t fil_cnt:4;
0385         uint64_t reserved_2_3:2;
0386         uint64_t rx_xor:1;
0387         uint64_t tx_oe:1;
0388 #else
0389         uint64_t tx_oe:1;
0390         uint64_t rx_xor:1;
0391         uint64_t reserved_2_3:2;
0392         uint64_t fil_cnt:4;
0393         uint64_t fil_sel:4;
0394         uint64_t reserved_12_63:52;
0395 #endif
0396     } cn30xx;
0397 };
0398 
0399 #endif
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