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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_GMXX_DEFS_H__
0029 #define __CVMX_GMXX_DEFS_H__
0030 
0031 static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
0032 {
0033     switch (cvmx_get_octeon_family()) {
0034     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0035         return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
0036     }
0037     return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
0038 }
0039 
0040 static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
0041 {
0042     switch (cvmx_get_octeon_family()) {
0043     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0044         return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
0045     }
0046     return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
0047 }
0048 
0049 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
0050 {
0051     switch (cvmx_get_octeon_family()) {
0052     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0053         return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0054     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0055         return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0056     }
0057     return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0058 }
0059 
0060 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
0061 {
0062     switch (cvmx_get_octeon_family()) {
0063     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0064         return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0065     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0066         return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0067     }
0068     return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0069 }
0070 
0071 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
0072 {
0073     switch (cvmx_get_octeon_family()) {
0074     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0075         return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0076     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0077         return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0078     }
0079     return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0080 }
0081 
0082 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
0083 {
0084     switch (cvmx_get_octeon_family()) {
0085     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0086         return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0087     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0088         return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0089     }
0090     return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0091 }
0092 
0093 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
0094 {
0095     switch (cvmx_get_octeon_family()) {
0096     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0097         return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0098     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0099         return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0100     }
0101     return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0102 }
0103 
0104 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
0105 {
0106     switch (cvmx_get_octeon_family()) {
0107     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0108         return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0109     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0110         return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0111     }
0112     return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0113 }
0114 
0115 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
0116 {
0117     switch (cvmx_get_octeon_family()) {
0118     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0119         return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0120     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0121         return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0122     }
0123     return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0124 }
0125 
0126 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
0127 {
0128     switch (cvmx_get_octeon_family()) {
0129     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0130         return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0131     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0132         return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0133     }
0134     return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0135 }
0136 
0137 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
0138 {
0139     switch (cvmx_get_octeon_family()) {
0140     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0141         return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0142     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0143         return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0144     }
0145     return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0146 }
0147 
0148 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
0149 {
0150     switch (cvmx_get_octeon_family()) {
0151     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0152         return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0153     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0154         return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0155     }
0156     return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0157 }
0158 
0159 #define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
0160 #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
0161 
0162 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
0163 {
0164     switch (cvmx_get_octeon_family()) {
0165     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0166         return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0167     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0168         return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0169     }
0170     return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0171 }
0172 
0173 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
0174 {
0175     switch (cvmx_get_octeon_family()) {
0176     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0177         return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0178     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0179         return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0180     }
0181     return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0182 }
0183 
0184 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
0185 {
0186     switch (cvmx_get_octeon_family()) {
0187     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0188         return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0189     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0190         return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0191     }
0192     return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0193 }
0194 
0195 #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
0196 
0197 static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
0198 {
0199     switch (cvmx_get_octeon_family()) {
0200     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0201         return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
0202     }
0203     return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
0204 }
0205 
0206 static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
0207 {
0208     switch (cvmx_get_octeon_family()) {
0209     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0210         return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
0211     }
0212     return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
0213 }
0214 
0215 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
0216 {
0217     switch (cvmx_get_octeon_family()) {
0218     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0219         return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0220     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0221         return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0222     }
0223     return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0224 }
0225 
0226 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
0227 {
0228     switch (cvmx_get_octeon_family()) {
0229     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0230         return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0231     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0232         return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0233     }
0234     return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0235 }
0236 
0237 #define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
0238 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
0239 {
0240     switch (cvmx_get_octeon_family()) {
0241     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0242         return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0243     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0244         return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0245     }
0246     return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0247 }
0248 
0249 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
0250 {
0251     switch (cvmx_get_octeon_family()) {
0252     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0253         return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0254     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0255         return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0256     }
0257     return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0258 }
0259 
0260 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
0261 {
0262     switch (cvmx_get_octeon_family()) {
0263     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0264         return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0265     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0266         return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0267     }
0268     return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0269 }
0270 
0271 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
0272 {
0273     switch (cvmx_get_octeon_family()) {
0274     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0275         return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0276     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0277         return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0278     }
0279     return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0280 }
0281 
0282 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
0283 {
0284     switch (cvmx_get_octeon_family()) {
0285     case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
0286         return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
0287     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0288         return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
0289     }
0290     return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
0291 }
0292 
0293 static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
0294 {
0295     switch (cvmx_get_octeon_family()) {
0296     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0297         return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
0298     }
0299     return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
0300 }
0301 
0302 static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
0303 {
0304     switch (cvmx_get_octeon_family()) {
0305     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0306         return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
0307     }
0308     return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
0309 }
0310 
0311 static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
0312 {
0313     switch (cvmx_get_octeon_family()) {
0314     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0315         return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
0316     }
0317     return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
0318 }
0319 
0320 static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
0321 {
0322     switch (cvmx_get_octeon_family()) {
0323     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0324         return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
0325     }
0326     return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
0327 }
0328 
0329 #define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
0330 #define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
0331 #define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
0332 static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
0333 {
0334     switch (cvmx_get_octeon_family()) {
0335     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0336         return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
0337     }
0338     return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
0339 }
0340 
0341 void __cvmx_interrupt_gmxx_enable(int interface);
0342 
0343 union cvmx_gmxx_hg2_control {
0344     uint64_t u64;
0345     struct cvmx_gmxx_hg2_control_s {
0346 #ifdef __BIG_ENDIAN_BITFIELD
0347         uint64_t reserved_19_63:45;
0348         uint64_t hg2tx_en:1;
0349         uint64_t hg2rx_en:1;
0350         uint64_t phys_en:1;
0351         uint64_t logl_en:16;
0352 #else
0353         uint64_t logl_en:16;
0354         uint64_t phys_en:1;
0355         uint64_t hg2rx_en:1;
0356         uint64_t hg2tx_en:1;
0357         uint64_t reserved_19_63:45;
0358 #endif
0359     } s;
0360 };
0361 
0362 union cvmx_gmxx_inf_mode {
0363     uint64_t u64;
0364     struct cvmx_gmxx_inf_mode_s {
0365 #ifdef __BIG_ENDIAN_BITFIELD
0366         uint64_t reserved_20_63:44;
0367         uint64_t rate:4;
0368         uint64_t reserved_12_15:4;
0369         uint64_t speed:4;
0370         uint64_t reserved_7_7:1;
0371         uint64_t mode:3;
0372         uint64_t reserved_3_3:1;
0373         uint64_t p0mii:1;
0374         uint64_t en:1;
0375         uint64_t type:1;
0376 #else
0377         uint64_t type:1;
0378         uint64_t en:1;
0379         uint64_t p0mii:1;
0380         uint64_t reserved_3_3:1;
0381         uint64_t mode:3;
0382         uint64_t reserved_7_7:1;
0383         uint64_t speed:4;
0384         uint64_t reserved_12_15:4;
0385         uint64_t rate:4;
0386         uint64_t reserved_20_63:44;
0387 #endif
0388     } s;
0389     struct cvmx_gmxx_inf_mode_cn30xx {
0390 #ifdef __BIG_ENDIAN_BITFIELD
0391         uint64_t reserved_3_63:61;
0392         uint64_t p0mii:1;
0393         uint64_t en:1;
0394         uint64_t type:1;
0395 #else
0396         uint64_t type:1;
0397         uint64_t en:1;
0398         uint64_t p0mii:1;
0399         uint64_t reserved_3_63:61;
0400 #endif
0401     } cn30xx;
0402     struct cvmx_gmxx_inf_mode_cn31xx {
0403 #ifdef __BIG_ENDIAN_BITFIELD
0404         uint64_t reserved_2_63:62;
0405         uint64_t en:1;
0406         uint64_t type:1;
0407 #else
0408         uint64_t type:1;
0409         uint64_t en:1;
0410         uint64_t reserved_2_63:62;
0411 #endif
0412     } cn31xx;
0413     struct cvmx_gmxx_inf_mode_cn52xx {
0414 #ifdef __BIG_ENDIAN_BITFIELD
0415         uint64_t reserved_10_63:54;
0416         uint64_t speed:2;
0417         uint64_t reserved_6_7:2;
0418         uint64_t mode:2;
0419         uint64_t reserved_2_3:2;
0420         uint64_t en:1;
0421         uint64_t type:1;
0422 #else
0423         uint64_t type:1;
0424         uint64_t en:1;
0425         uint64_t reserved_2_3:2;
0426         uint64_t mode:2;
0427         uint64_t reserved_6_7:2;
0428         uint64_t speed:2;
0429         uint64_t reserved_10_63:54;
0430 #endif
0431     } cn52xx;
0432     struct cvmx_gmxx_inf_mode_cn61xx {
0433 #ifdef __BIG_ENDIAN_BITFIELD
0434         uint64_t reserved_12_63:52;
0435         uint64_t speed:4;
0436         uint64_t reserved_5_7:3;
0437         uint64_t mode:1;
0438         uint64_t reserved_2_3:2;
0439         uint64_t en:1;
0440         uint64_t type:1;
0441 #else
0442         uint64_t type:1;
0443         uint64_t en:1;
0444         uint64_t reserved_2_3:2;
0445         uint64_t mode:1;
0446         uint64_t reserved_5_7:3;
0447         uint64_t speed:4;
0448         uint64_t reserved_12_63:52;
0449 #endif
0450     } cn61xx;
0451     struct cvmx_gmxx_inf_mode_cn66xx {
0452 #ifdef __BIG_ENDIAN_BITFIELD
0453         uint64_t reserved_20_63:44;
0454         uint64_t rate:4;
0455         uint64_t reserved_12_15:4;
0456         uint64_t speed:4;
0457         uint64_t reserved_5_7:3;
0458         uint64_t mode:1;
0459         uint64_t reserved_2_3:2;
0460         uint64_t en:1;
0461         uint64_t type:1;
0462 #else
0463         uint64_t type:1;
0464         uint64_t en:1;
0465         uint64_t reserved_2_3:2;
0466         uint64_t mode:1;
0467         uint64_t reserved_5_7:3;
0468         uint64_t speed:4;
0469         uint64_t reserved_12_15:4;
0470         uint64_t rate:4;
0471         uint64_t reserved_20_63:44;
0472 #endif
0473     } cn66xx;
0474     struct cvmx_gmxx_inf_mode_cn68xx {
0475 #ifdef __BIG_ENDIAN_BITFIELD
0476         uint64_t reserved_12_63:52;
0477         uint64_t speed:4;
0478         uint64_t reserved_7_7:1;
0479         uint64_t mode:3;
0480         uint64_t reserved_2_3:2;
0481         uint64_t en:1;
0482         uint64_t type:1;
0483 #else
0484         uint64_t type:1;
0485         uint64_t en:1;
0486         uint64_t reserved_2_3:2;
0487         uint64_t mode:3;
0488         uint64_t reserved_7_7:1;
0489         uint64_t speed:4;
0490         uint64_t reserved_12_63:52;
0491 #endif
0492     } cn68xx;
0493 };
0494 
0495 union cvmx_gmxx_prtx_cfg {
0496     uint64_t u64;
0497     struct cvmx_gmxx_prtx_cfg_s {
0498 #ifdef __BIG_ENDIAN_BITFIELD
0499         uint64_t reserved_22_63:42;
0500         uint64_t pknd:6;
0501         uint64_t reserved_14_15:2;
0502         uint64_t tx_idle:1;
0503         uint64_t rx_idle:1;
0504         uint64_t reserved_9_11:3;
0505         uint64_t speed_msb:1;
0506         uint64_t reserved_4_7:4;
0507         uint64_t slottime:1;
0508         uint64_t duplex:1;
0509         uint64_t speed:1;
0510         uint64_t en:1;
0511 #else
0512         uint64_t en:1;
0513         uint64_t speed:1;
0514         uint64_t duplex:1;
0515         uint64_t slottime:1;
0516         uint64_t reserved_4_7:4;
0517         uint64_t speed_msb:1;
0518         uint64_t reserved_9_11:3;
0519         uint64_t rx_idle:1;
0520         uint64_t tx_idle:1;
0521         uint64_t reserved_14_15:2;
0522         uint64_t pknd:6;
0523         uint64_t reserved_22_63:42;
0524 #endif
0525     } s;
0526     struct cvmx_gmxx_prtx_cfg_cn30xx {
0527 #ifdef __BIG_ENDIAN_BITFIELD
0528         uint64_t reserved_4_63:60;
0529         uint64_t slottime:1;
0530         uint64_t duplex:1;
0531         uint64_t speed:1;
0532         uint64_t en:1;
0533 #else
0534         uint64_t en:1;
0535         uint64_t speed:1;
0536         uint64_t duplex:1;
0537         uint64_t slottime:1;
0538         uint64_t reserved_4_63:60;
0539 #endif
0540     } cn30xx;
0541     struct cvmx_gmxx_prtx_cfg_cn52xx {
0542 #ifdef __BIG_ENDIAN_BITFIELD
0543         uint64_t reserved_14_63:50;
0544         uint64_t tx_idle:1;
0545         uint64_t rx_idle:1;
0546         uint64_t reserved_9_11:3;
0547         uint64_t speed_msb:1;
0548         uint64_t reserved_4_7:4;
0549         uint64_t slottime:1;
0550         uint64_t duplex:1;
0551         uint64_t speed:1;
0552         uint64_t en:1;
0553 #else
0554         uint64_t en:1;
0555         uint64_t speed:1;
0556         uint64_t duplex:1;
0557         uint64_t slottime:1;
0558         uint64_t reserved_4_7:4;
0559         uint64_t speed_msb:1;
0560         uint64_t reserved_9_11:3;
0561         uint64_t rx_idle:1;
0562         uint64_t tx_idle:1;
0563         uint64_t reserved_14_63:50;
0564 #endif
0565     } cn52xx;
0566 };
0567 
0568 union cvmx_gmxx_rxx_adr_ctl {
0569     uint64_t u64;
0570     struct cvmx_gmxx_rxx_adr_ctl_s {
0571 #ifdef __BIG_ENDIAN_BITFIELD
0572         uint64_t reserved_4_63:60;
0573         uint64_t cam_mode:1;
0574         uint64_t mcst:2;
0575         uint64_t bcst:1;
0576 #else
0577         uint64_t bcst:1;
0578         uint64_t mcst:2;
0579         uint64_t cam_mode:1;
0580         uint64_t reserved_4_63:60;
0581 #endif
0582     } s;
0583 };
0584 
0585 union cvmx_gmxx_rxx_frm_ctl {
0586     uint64_t u64;
0587     struct cvmx_gmxx_rxx_frm_ctl_s {
0588 #ifdef __BIG_ENDIAN_BITFIELD
0589         uint64_t reserved_13_63:51;
0590         uint64_t ptp_mode:1;
0591         uint64_t reserved_11_11:1;
0592         uint64_t null_dis:1;
0593         uint64_t pre_align:1;
0594         uint64_t pad_len:1;
0595         uint64_t vlan_len:1;
0596         uint64_t pre_free:1;
0597         uint64_t ctl_smac:1;
0598         uint64_t ctl_mcst:1;
0599         uint64_t ctl_bck:1;
0600         uint64_t ctl_drp:1;
0601         uint64_t pre_strp:1;
0602         uint64_t pre_chk:1;
0603 #else
0604         uint64_t pre_chk:1;
0605         uint64_t pre_strp:1;
0606         uint64_t ctl_drp:1;
0607         uint64_t ctl_bck:1;
0608         uint64_t ctl_mcst:1;
0609         uint64_t ctl_smac:1;
0610         uint64_t pre_free:1;
0611         uint64_t vlan_len:1;
0612         uint64_t pad_len:1;
0613         uint64_t pre_align:1;
0614         uint64_t null_dis:1;
0615         uint64_t reserved_11_11:1;
0616         uint64_t ptp_mode:1;
0617         uint64_t reserved_13_63:51;
0618 #endif
0619     } s;
0620     struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
0621 #ifdef __BIG_ENDIAN_BITFIELD
0622         uint64_t reserved_9_63:55;
0623         uint64_t pad_len:1;
0624         uint64_t vlan_len:1;
0625         uint64_t pre_free:1;
0626         uint64_t ctl_smac:1;
0627         uint64_t ctl_mcst:1;
0628         uint64_t ctl_bck:1;
0629         uint64_t ctl_drp:1;
0630         uint64_t pre_strp:1;
0631         uint64_t pre_chk:1;
0632 #else
0633         uint64_t pre_chk:1;
0634         uint64_t pre_strp:1;
0635         uint64_t ctl_drp:1;
0636         uint64_t ctl_bck:1;
0637         uint64_t ctl_mcst:1;
0638         uint64_t ctl_smac:1;
0639         uint64_t pre_free:1;
0640         uint64_t vlan_len:1;
0641         uint64_t pad_len:1;
0642         uint64_t reserved_9_63:55;
0643 #endif
0644     } cn30xx;
0645     struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
0646 #ifdef __BIG_ENDIAN_BITFIELD
0647         uint64_t reserved_8_63:56;
0648         uint64_t vlan_len:1;
0649         uint64_t pre_free:1;
0650         uint64_t ctl_smac:1;
0651         uint64_t ctl_mcst:1;
0652         uint64_t ctl_bck:1;
0653         uint64_t ctl_drp:1;
0654         uint64_t pre_strp:1;
0655         uint64_t pre_chk:1;
0656 #else
0657         uint64_t pre_chk:1;
0658         uint64_t pre_strp:1;
0659         uint64_t ctl_drp:1;
0660         uint64_t ctl_bck:1;
0661         uint64_t ctl_mcst:1;
0662         uint64_t ctl_smac:1;
0663         uint64_t pre_free:1;
0664         uint64_t vlan_len:1;
0665         uint64_t reserved_8_63:56;
0666 #endif
0667     } cn31xx;
0668     struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
0669 #ifdef __BIG_ENDIAN_BITFIELD
0670         uint64_t reserved_11_63:53;
0671         uint64_t null_dis:1;
0672         uint64_t pre_align:1;
0673         uint64_t reserved_7_8:2;
0674         uint64_t pre_free:1;
0675         uint64_t ctl_smac:1;
0676         uint64_t ctl_mcst:1;
0677         uint64_t ctl_bck:1;
0678         uint64_t ctl_drp:1;
0679         uint64_t pre_strp:1;
0680         uint64_t pre_chk:1;
0681 #else
0682         uint64_t pre_chk:1;
0683         uint64_t pre_strp:1;
0684         uint64_t ctl_drp:1;
0685         uint64_t ctl_bck:1;
0686         uint64_t ctl_mcst:1;
0687         uint64_t ctl_smac:1;
0688         uint64_t pre_free:1;
0689         uint64_t reserved_7_8:2;
0690         uint64_t pre_align:1;
0691         uint64_t null_dis:1;
0692         uint64_t reserved_11_63:53;
0693 #endif
0694     } cn50xx;
0695     struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
0696 #ifdef __BIG_ENDIAN_BITFIELD
0697         uint64_t reserved_10_63:54;
0698         uint64_t pre_align:1;
0699         uint64_t reserved_7_8:2;
0700         uint64_t pre_free:1;
0701         uint64_t ctl_smac:1;
0702         uint64_t ctl_mcst:1;
0703         uint64_t ctl_bck:1;
0704         uint64_t ctl_drp:1;
0705         uint64_t pre_strp:1;
0706         uint64_t pre_chk:1;
0707 #else
0708         uint64_t pre_chk:1;
0709         uint64_t pre_strp:1;
0710         uint64_t ctl_drp:1;
0711         uint64_t ctl_bck:1;
0712         uint64_t ctl_mcst:1;
0713         uint64_t ctl_smac:1;
0714         uint64_t pre_free:1;
0715         uint64_t reserved_7_8:2;
0716         uint64_t pre_align:1;
0717         uint64_t reserved_10_63:54;
0718 #endif
0719     } cn56xxp1;
0720     struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
0721 #ifdef __BIG_ENDIAN_BITFIELD
0722         uint64_t reserved_11_63:53;
0723         uint64_t null_dis:1;
0724         uint64_t pre_align:1;
0725         uint64_t pad_len:1;
0726         uint64_t vlan_len:1;
0727         uint64_t pre_free:1;
0728         uint64_t ctl_smac:1;
0729         uint64_t ctl_mcst:1;
0730         uint64_t ctl_bck:1;
0731         uint64_t ctl_drp:1;
0732         uint64_t pre_strp:1;
0733         uint64_t pre_chk:1;
0734 #else
0735         uint64_t pre_chk:1;
0736         uint64_t pre_strp:1;
0737         uint64_t ctl_drp:1;
0738         uint64_t ctl_bck:1;
0739         uint64_t ctl_mcst:1;
0740         uint64_t ctl_smac:1;
0741         uint64_t pre_free:1;
0742         uint64_t vlan_len:1;
0743         uint64_t pad_len:1;
0744         uint64_t pre_align:1;
0745         uint64_t null_dis:1;
0746         uint64_t reserved_11_63:53;
0747 #endif
0748     } cn58xx;
0749     struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
0750 #ifdef __BIG_ENDIAN_BITFIELD
0751         uint64_t reserved_13_63:51;
0752         uint64_t ptp_mode:1;
0753         uint64_t reserved_11_11:1;
0754         uint64_t null_dis:1;
0755         uint64_t pre_align:1;
0756         uint64_t reserved_7_8:2;
0757         uint64_t pre_free:1;
0758         uint64_t ctl_smac:1;
0759         uint64_t ctl_mcst:1;
0760         uint64_t ctl_bck:1;
0761         uint64_t ctl_drp:1;
0762         uint64_t pre_strp:1;
0763         uint64_t pre_chk:1;
0764 #else
0765         uint64_t pre_chk:1;
0766         uint64_t pre_strp:1;
0767         uint64_t ctl_drp:1;
0768         uint64_t ctl_bck:1;
0769         uint64_t ctl_mcst:1;
0770         uint64_t ctl_smac:1;
0771         uint64_t pre_free:1;
0772         uint64_t reserved_7_8:2;
0773         uint64_t pre_align:1;
0774         uint64_t null_dis:1;
0775         uint64_t reserved_11_11:1;
0776         uint64_t ptp_mode:1;
0777         uint64_t reserved_13_63:51;
0778 #endif
0779     } cn61xx;
0780 };
0781 
0782 union cvmx_gmxx_rxx_frm_max {
0783     uint64_t u64;
0784     struct cvmx_gmxx_rxx_frm_max_s {
0785 #ifdef __BIG_ENDIAN_BITFIELD
0786         uint64_t reserved_16_63:48;
0787         uint64_t len:16;
0788 #else
0789         uint64_t len:16;
0790         uint64_t reserved_16_63:48;
0791 #endif
0792     } s;
0793 };
0794 
0795 union cvmx_gmxx_rxx_frm_min {
0796     uint64_t u64;
0797     struct cvmx_gmxx_rxx_frm_min_s {
0798 #ifdef __BIG_ENDIAN_BITFIELD
0799         uint64_t reserved_16_63:48;
0800         uint64_t len:16;
0801 #else
0802         uint64_t len:16;
0803         uint64_t reserved_16_63:48;
0804 #endif
0805     } s;
0806 };
0807 
0808 union cvmx_gmxx_rxx_int_en {
0809     uint64_t u64;
0810     struct cvmx_gmxx_rxx_int_en_s {
0811 #ifdef __BIG_ENDIAN_BITFIELD
0812         uint64_t reserved_29_63:35;
0813         uint64_t hg2cc:1;
0814         uint64_t hg2fld:1;
0815         uint64_t undat:1;
0816         uint64_t uneop:1;
0817         uint64_t unsop:1;
0818         uint64_t bad_term:1;
0819         uint64_t bad_seq:1;
0820         uint64_t rem_fault:1;
0821         uint64_t loc_fault:1;
0822         uint64_t pause_drp:1;
0823         uint64_t phy_dupx:1;
0824         uint64_t phy_spd:1;
0825         uint64_t phy_link:1;
0826         uint64_t ifgerr:1;
0827         uint64_t coldet:1;
0828         uint64_t falerr:1;
0829         uint64_t rsverr:1;
0830         uint64_t pcterr:1;
0831         uint64_t ovrerr:1;
0832         uint64_t niberr:1;
0833         uint64_t skperr:1;
0834         uint64_t rcverr:1;
0835         uint64_t lenerr:1;
0836         uint64_t alnerr:1;
0837         uint64_t fcserr:1;
0838         uint64_t jabber:1;
0839         uint64_t maxerr:1;
0840         uint64_t carext:1;
0841         uint64_t minerr:1;
0842 #else
0843         uint64_t minerr:1;
0844         uint64_t carext:1;
0845         uint64_t maxerr:1;
0846         uint64_t jabber:1;
0847         uint64_t fcserr:1;
0848         uint64_t alnerr:1;
0849         uint64_t lenerr:1;
0850         uint64_t rcverr:1;
0851         uint64_t skperr:1;
0852         uint64_t niberr:1;
0853         uint64_t ovrerr:1;
0854         uint64_t pcterr:1;
0855         uint64_t rsverr:1;
0856         uint64_t falerr:1;
0857         uint64_t coldet:1;
0858         uint64_t ifgerr:1;
0859         uint64_t phy_link:1;
0860         uint64_t phy_spd:1;
0861         uint64_t phy_dupx:1;
0862         uint64_t pause_drp:1;
0863         uint64_t loc_fault:1;
0864         uint64_t rem_fault:1;
0865         uint64_t bad_seq:1;
0866         uint64_t bad_term:1;
0867         uint64_t unsop:1;
0868         uint64_t uneop:1;
0869         uint64_t undat:1;
0870         uint64_t hg2fld:1;
0871         uint64_t hg2cc:1;
0872         uint64_t reserved_29_63:35;
0873 #endif
0874     } s;
0875     struct cvmx_gmxx_rxx_int_en_cn30xx {
0876 #ifdef __BIG_ENDIAN_BITFIELD
0877         uint64_t reserved_19_63:45;
0878         uint64_t phy_dupx:1;
0879         uint64_t phy_spd:1;
0880         uint64_t phy_link:1;
0881         uint64_t ifgerr:1;
0882         uint64_t coldet:1;
0883         uint64_t falerr:1;
0884         uint64_t rsverr:1;
0885         uint64_t pcterr:1;
0886         uint64_t ovrerr:1;
0887         uint64_t niberr:1;
0888         uint64_t skperr:1;
0889         uint64_t rcverr:1;
0890         uint64_t lenerr:1;
0891         uint64_t alnerr:1;
0892         uint64_t fcserr:1;
0893         uint64_t jabber:1;
0894         uint64_t maxerr:1;
0895         uint64_t carext:1;
0896         uint64_t minerr:1;
0897 #else
0898         uint64_t minerr:1;
0899         uint64_t carext:1;
0900         uint64_t maxerr:1;
0901         uint64_t jabber:1;
0902         uint64_t fcserr:1;
0903         uint64_t alnerr:1;
0904         uint64_t lenerr:1;
0905         uint64_t rcverr:1;
0906         uint64_t skperr:1;
0907         uint64_t niberr:1;
0908         uint64_t ovrerr:1;
0909         uint64_t pcterr:1;
0910         uint64_t rsverr:1;
0911         uint64_t falerr:1;
0912         uint64_t coldet:1;
0913         uint64_t ifgerr:1;
0914         uint64_t phy_link:1;
0915         uint64_t phy_spd:1;
0916         uint64_t phy_dupx:1;
0917         uint64_t reserved_19_63:45;
0918 #endif
0919     } cn30xx;
0920     struct cvmx_gmxx_rxx_int_en_cn50xx {
0921 #ifdef __BIG_ENDIAN_BITFIELD
0922         uint64_t reserved_20_63:44;
0923         uint64_t pause_drp:1;
0924         uint64_t phy_dupx:1;
0925         uint64_t phy_spd:1;
0926         uint64_t phy_link:1;
0927         uint64_t ifgerr:1;
0928         uint64_t coldet:1;
0929         uint64_t falerr:1;
0930         uint64_t rsverr:1;
0931         uint64_t pcterr:1;
0932         uint64_t ovrerr:1;
0933         uint64_t niberr:1;
0934         uint64_t skperr:1;
0935         uint64_t rcverr:1;
0936         uint64_t reserved_6_6:1;
0937         uint64_t alnerr:1;
0938         uint64_t fcserr:1;
0939         uint64_t jabber:1;
0940         uint64_t reserved_2_2:1;
0941         uint64_t carext:1;
0942         uint64_t reserved_0_0:1;
0943 #else
0944         uint64_t reserved_0_0:1;
0945         uint64_t carext:1;
0946         uint64_t reserved_2_2:1;
0947         uint64_t jabber:1;
0948         uint64_t fcserr:1;
0949         uint64_t alnerr:1;
0950         uint64_t reserved_6_6:1;
0951         uint64_t rcverr:1;
0952         uint64_t skperr:1;
0953         uint64_t niberr:1;
0954         uint64_t ovrerr:1;
0955         uint64_t pcterr:1;
0956         uint64_t rsverr:1;
0957         uint64_t falerr:1;
0958         uint64_t coldet:1;
0959         uint64_t ifgerr:1;
0960         uint64_t phy_link:1;
0961         uint64_t phy_spd:1;
0962         uint64_t phy_dupx:1;
0963         uint64_t pause_drp:1;
0964         uint64_t reserved_20_63:44;
0965 #endif
0966     } cn50xx;
0967     struct cvmx_gmxx_rxx_int_en_cn52xx {
0968 #ifdef __BIG_ENDIAN_BITFIELD
0969         uint64_t reserved_29_63:35;
0970         uint64_t hg2cc:1;
0971         uint64_t hg2fld:1;
0972         uint64_t undat:1;
0973         uint64_t uneop:1;
0974         uint64_t unsop:1;
0975         uint64_t bad_term:1;
0976         uint64_t bad_seq:1;
0977         uint64_t rem_fault:1;
0978         uint64_t loc_fault:1;
0979         uint64_t pause_drp:1;
0980         uint64_t reserved_16_18:3;
0981         uint64_t ifgerr:1;
0982         uint64_t coldet:1;
0983         uint64_t falerr:1;
0984         uint64_t rsverr:1;
0985         uint64_t pcterr:1;
0986         uint64_t ovrerr:1;
0987         uint64_t reserved_9_9:1;
0988         uint64_t skperr:1;
0989         uint64_t rcverr:1;
0990         uint64_t reserved_5_6:2;
0991         uint64_t fcserr:1;
0992         uint64_t jabber:1;
0993         uint64_t reserved_2_2:1;
0994         uint64_t carext:1;
0995         uint64_t reserved_0_0:1;
0996 #else
0997         uint64_t reserved_0_0:1;
0998         uint64_t carext:1;
0999         uint64_t reserved_2_2:1;
1000         uint64_t jabber:1;
1001         uint64_t fcserr:1;
1002         uint64_t reserved_5_6:2;
1003         uint64_t rcverr:1;
1004         uint64_t skperr:1;
1005         uint64_t reserved_9_9:1;
1006         uint64_t ovrerr:1;
1007         uint64_t pcterr:1;
1008         uint64_t rsverr:1;
1009         uint64_t falerr:1;
1010         uint64_t coldet:1;
1011         uint64_t ifgerr:1;
1012         uint64_t reserved_16_18:3;
1013         uint64_t pause_drp:1;
1014         uint64_t loc_fault:1;
1015         uint64_t rem_fault:1;
1016         uint64_t bad_seq:1;
1017         uint64_t bad_term:1;
1018         uint64_t unsop:1;
1019         uint64_t uneop:1;
1020         uint64_t undat:1;
1021         uint64_t hg2fld:1;
1022         uint64_t hg2cc:1;
1023         uint64_t reserved_29_63:35;
1024 #endif
1025     } cn52xx;
1026     struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028         uint64_t reserved_27_63:37;
1029         uint64_t undat:1;
1030         uint64_t uneop:1;
1031         uint64_t unsop:1;
1032         uint64_t bad_term:1;
1033         uint64_t bad_seq:1;
1034         uint64_t rem_fault:1;
1035         uint64_t loc_fault:1;
1036         uint64_t pause_drp:1;
1037         uint64_t reserved_16_18:3;
1038         uint64_t ifgerr:1;
1039         uint64_t coldet:1;
1040         uint64_t falerr:1;
1041         uint64_t rsverr:1;
1042         uint64_t pcterr:1;
1043         uint64_t ovrerr:1;
1044         uint64_t reserved_9_9:1;
1045         uint64_t skperr:1;
1046         uint64_t rcverr:1;
1047         uint64_t reserved_5_6:2;
1048         uint64_t fcserr:1;
1049         uint64_t jabber:1;
1050         uint64_t reserved_2_2:1;
1051         uint64_t carext:1;
1052         uint64_t reserved_0_0:1;
1053 #else
1054         uint64_t reserved_0_0:1;
1055         uint64_t carext:1;
1056         uint64_t reserved_2_2:1;
1057         uint64_t jabber:1;
1058         uint64_t fcserr:1;
1059         uint64_t reserved_5_6:2;
1060         uint64_t rcverr:1;
1061         uint64_t skperr:1;
1062         uint64_t reserved_9_9:1;
1063         uint64_t ovrerr:1;
1064         uint64_t pcterr:1;
1065         uint64_t rsverr:1;
1066         uint64_t falerr:1;
1067         uint64_t coldet:1;
1068         uint64_t ifgerr:1;
1069         uint64_t reserved_16_18:3;
1070         uint64_t pause_drp:1;
1071         uint64_t loc_fault:1;
1072         uint64_t rem_fault:1;
1073         uint64_t bad_seq:1;
1074         uint64_t bad_term:1;
1075         uint64_t unsop:1;
1076         uint64_t uneop:1;
1077         uint64_t undat:1;
1078         uint64_t reserved_27_63:37;
1079 #endif
1080     } cn56xxp1;
1081     struct cvmx_gmxx_rxx_int_en_cn58xx {
1082 #ifdef __BIG_ENDIAN_BITFIELD
1083         uint64_t reserved_20_63:44;
1084         uint64_t pause_drp:1;
1085         uint64_t phy_dupx:1;
1086         uint64_t phy_spd:1;
1087         uint64_t phy_link:1;
1088         uint64_t ifgerr:1;
1089         uint64_t coldet:1;
1090         uint64_t falerr:1;
1091         uint64_t rsverr:1;
1092         uint64_t pcterr:1;
1093         uint64_t ovrerr:1;
1094         uint64_t niberr:1;
1095         uint64_t skperr:1;
1096         uint64_t rcverr:1;
1097         uint64_t lenerr:1;
1098         uint64_t alnerr:1;
1099         uint64_t fcserr:1;
1100         uint64_t jabber:1;
1101         uint64_t maxerr:1;
1102         uint64_t carext:1;
1103         uint64_t minerr:1;
1104 #else
1105         uint64_t minerr:1;
1106         uint64_t carext:1;
1107         uint64_t maxerr:1;
1108         uint64_t jabber:1;
1109         uint64_t fcserr:1;
1110         uint64_t alnerr:1;
1111         uint64_t lenerr:1;
1112         uint64_t rcverr:1;
1113         uint64_t skperr:1;
1114         uint64_t niberr:1;
1115         uint64_t ovrerr:1;
1116         uint64_t pcterr:1;
1117         uint64_t rsverr:1;
1118         uint64_t falerr:1;
1119         uint64_t coldet:1;
1120         uint64_t ifgerr:1;
1121         uint64_t phy_link:1;
1122         uint64_t phy_spd:1;
1123         uint64_t phy_dupx:1;
1124         uint64_t pause_drp:1;
1125         uint64_t reserved_20_63:44;
1126 #endif
1127     } cn58xx;
1128     struct cvmx_gmxx_rxx_int_en_cn61xx {
1129 #ifdef __BIG_ENDIAN_BITFIELD
1130         uint64_t reserved_29_63:35;
1131         uint64_t hg2cc:1;
1132         uint64_t hg2fld:1;
1133         uint64_t undat:1;
1134         uint64_t uneop:1;
1135         uint64_t unsop:1;
1136         uint64_t bad_term:1;
1137         uint64_t bad_seq:1;
1138         uint64_t rem_fault:1;
1139         uint64_t loc_fault:1;
1140         uint64_t pause_drp:1;
1141         uint64_t reserved_16_18:3;
1142         uint64_t ifgerr:1;
1143         uint64_t coldet:1;
1144         uint64_t falerr:1;
1145         uint64_t rsverr:1;
1146         uint64_t pcterr:1;
1147         uint64_t ovrerr:1;
1148         uint64_t reserved_9_9:1;
1149         uint64_t skperr:1;
1150         uint64_t rcverr:1;
1151         uint64_t reserved_5_6:2;
1152         uint64_t fcserr:1;
1153         uint64_t jabber:1;
1154         uint64_t reserved_2_2:1;
1155         uint64_t carext:1;
1156         uint64_t minerr:1;
1157 #else
1158         uint64_t minerr:1;
1159         uint64_t carext:1;
1160         uint64_t reserved_2_2:1;
1161         uint64_t jabber:1;
1162         uint64_t fcserr:1;
1163         uint64_t reserved_5_6:2;
1164         uint64_t rcverr:1;
1165         uint64_t skperr:1;
1166         uint64_t reserved_9_9:1;
1167         uint64_t ovrerr:1;
1168         uint64_t pcterr:1;
1169         uint64_t rsverr:1;
1170         uint64_t falerr:1;
1171         uint64_t coldet:1;
1172         uint64_t ifgerr:1;
1173         uint64_t reserved_16_18:3;
1174         uint64_t pause_drp:1;
1175         uint64_t loc_fault:1;
1176         uint64_t rem_fault:1;
1177         uint64_t bad_seq:1;
1178         uint64_t bad_term:1;
1179         uint64_t unsop:1;
1180         uint64_t uneop:1;
1181         uint64_t undat:1;
1182         uint64_t hg2fld:1;
1183         uint64_t hg2cc:1;
1184         uint64_t reserved_29_63:35;
1185 #endif
1186     } cn61xx;
1187 };
1188 
1189 union cvmx_gmxx_rxx_int_reg {
1190     uint64_t u64;
1191     struct cvmx_gmxx_rxx_int_reg_s {
1192 #ifdef __BIG_ENDIAN_BITFIELD
1193         uint64_t reserved_29_63:35;
1194         uint64_t hg2cc:1;
1195         uint64_t hg2fld:1;
1196         uint64_t undat:1;
1197         uint64_t uneop:1;
1198         uint64_t unsop:1;
1199         uint64_t bad_term:1;
1200         uint64_t bad_seq:1;
1201         uint64_t rem_fault:1;
1202         uint64_t loc_fault:1;
1203         uint64_t pause_drp:1;
1204         uint64_t phy_dupx:1;
1205         uint64_t phy_spd:1;
1206         uint64_t phy_link:1;
1207         uint64_t ifgerr:1;
1208         uint64_t coldet:1;
1209         uint64_t falerr:1;
1210         uint64_t rsverr:1;
1211         uint64_t pcterr:1;
1212         uint64_t ovrerr:1;
1213         uint64_t niberr:1;
1214         uint64_t skperr:1;
1215         uint64_t rcverr:1;
1216         uint64_t lenerr:1;
1217         uint64_t alnerr:1;
1218         uint64_t fcserr:1;
1219         uint64_t jabber:1;
1220         uint64_t maxerr:1;
1221         uint64_t carext:1;
1222         uint64_t minerr:1;
1223 #else
1224         uint64_t minerr:1;
1225         uint64_t carext:1;
1226         uint64_t maxerr:1;
1227         uint64_t jabber:1;
1228         uint64_t fcserr:1;
1229         uint64_t alnerr:1;
1230         uint64_t lenerr:1;
1231         uint64_t rcverr:1;
1232         uint64_t skperr:1;
1233         uint64_t niberr:1;
1234         uint64_t ovrerr:1;
1235         uint64_t pcterr:1;
1236         uint64_t rsverr:1;
1237         uint64_t falerr:1;
1238         uint64_t coldet:1;
1239         uint64_t ifgerr:1;
1240         uint64_t phy_link:1;
1241         uint64_t phy_spd:1;
1242         uint64_t phy_dupx:1;
1243         uint64_t pause_drp:1;
1244         uint64_t loc_fault:1;
1245         uint64_t rem_fault:1;
1246         uint64_t bad_seq:1;
1247         uint64_t bad_term:1;
1248         uint64_t unsop:1;
1249         uint64_t uneop:1;
1250         uint64_t undat:1;
1251         uint64_t hg2fld:1;
1252         uint64_t hg2cc:1;
1253         uint64_t reserved_29_63:35;
1254 #endif
1255     } s;
1256     struct cvmx_gmxx_rxx_int_reg_cn30xx {
1257 #ifdef __BIG_ENDIAN_BITFIELD
1258         uint64_t reserved_19_63:45;
1259         uint64_t phy_dupx:1;
1260         uint64_t phy_spd:1;
1261         uint64_t phy_link:1;
1262         uint64_t ifgerr:1;
1263         uint64_t coldet:1;
1264         uint64_t falerr:1;
1265         uint64_t rsverr:1;
1266         uint64_t pcterr:1;
1267         uint64_t ovrerr:1;
1268         uint64_t niberr:1;
1269         uint64_t skperr:1;
1270         uint64_t rcverr:1;
1271         uint64_t lenerr:1;
1272         uint64_t alnerr:1;
1273         uint64_t fcserr:1;
1274         uint64_t jabber:1;
1275         uint64_t maxerr:1;
1276         uint64_t carext:1;
1277         uint64_t minerr:1;
1278 #else
1279         uint64_t minerr:1;
1280         uint64_t carext:1;
1281         uint64_t maxerr:1;
1282         uint64_t jabber:1;
1283         uint64_t fcserr:1;
1284         uint64_t alnerr:1;
1285         uint64_t lenerr:1;
1286         uint64_t rcverr:1;
1287         uint64_t skperr:1;
1288         uint64_t niberr:1;
1289         uint64_t ovrerr:1;
1290         uint64_t pcterr:1;
1291         uint64_t rsverr:1;
1292         uint64_t falerr:1;
1293         uint64_t coldet:1;
1294         uint64_t ifgerr:1;
1295         uint64_t phy_link:1;
1296         uint64_t phy_spd:1;
1297         uint64_t phy_dupx:1;
1298         uint64_t reserved_19_63:45;
1299 #endif
1300     } cn30xx;
1301     struct cvmx_gmxx_rxx_int_reg_cn50xx {
1302 #ifdef __BIG_ENDIAN_BITFIELD
1303         uint64_t reserved_20_63:44;
1304         uint64_t pause_drp:1;
1305         uint64_t phy_dupx:1;
1306         uint64_t phy_spd:1;
1307         uint64_t phy_link:1;
1308         uint64_t ifgerr:1;
1309         uint64_t coldet:1;
1310         uint64_t falerr:1;
1311         uint64_t rsverr:1;
1312         uint64_t pcterr:1;
1313         uint64_t ovrerr:1;
1314         uint64_t niberr:1;
1315         uint64_t skperr:1;
1316         uint64_t rcverr:1;
1317         uint64_t reserved_6_6:1;
1318         uint64_t alnerr:1;
1319         uint64_t fcserr:1;
1320         uint64_t jabber:1;
1321         uint64_t reserved_2_2:1;
1322         uint64_t carext:1;
1323         uint64_t reserved_0_0:1;
1324 #else
1325         uint64_t reserved_0_0:1;
1326         uint64_t carext:1;
1327         uint64_t reserved_2_2:1;
1328         uint64_t jabber:1;
1329         uint64_t fcserr:1;
1330         uint64_t alnerr:1;
1331         uint64_t reserved_6_6:1;
1332         uint64_t rcverr:1;
1333         uint64_t skperr:1;
1334         uint64_t niberr:1;
1335         uint64_t ovrerr:1;
1336         uint64_t pcterr:1;
1337         uint64_t rsverr:1;
1338         uint64_t falerr:1;
1339         uint64_t coldet:1;
1340         uint64_t ifgerr:1;
1341         uint64_t phy_link:1;
1342         uint64_t phy_spd:1;
1343         uint64_t phy_dupx:1;
1344         uint64_t pause_drp:1;
1345         uint64_t reserved_20_63:44;
1346 #endif
1347     } cn50xx;
1348     struct cvmx_gmxx_rxx_int_reg_cn52xx {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1350         uint64_t reserved_29_63:35;
1351         uint64_t hg2cc:1;
1352         uint64_t hg2fld:1;
1353         uint64_t undat:1;
1354         uint64_t uneop:1;
1355         uint64_t unsop:1;
1356         uint64_t bad_term:1;
1357         uint64_t bad_seq:1;
1358         uint64_t rem_fault:1;
1359         uint64_t loc_fault:1;
1360         uint64_t pause_drp:1;
1361         uint64_t reserved_16_18:3;
1362         uint64_t ifgerr:1;
1363         uint64_t coldet:1;
1364         uint64_t falerr:1;
1365         uint64_t rsverr:1;
1366         uint64_t pcterr:1;
1367         uint64_t ovrerr:1;
1368         uint64_t reserved_9_9:1;
1369         uint64_t skperr:1;
1370         uint64_t rcverr:1;
1371         uint64_t reserved_5_6:2;
1372         uint64_t fcserr:1;
1373         uint64_t jabber:1;
1374         uint64_t reserved_2_2:1;
1375         uint64_t carext:1;
1376         uint64_t reserved_0_0:1;
1377 #else
1378         uint64_t reserved_0_0:1;
1379         uint64_t carext:1;
1380         uint64_t reserved_2_2:1;
1381         uint64_t jabber:1;
1382         uint64_t fcserr:1;
1383         uint64_t reserved_5_6:2;
1384         uint64_t rcverr:1;
1385         uint64_t skperr:1;
1386         uint64_t reserved_9_9:1;
1387         uint64_t ovrerr:1;
1388         uint64_t pcterr:1;
1389         uint64_t rsverr:1;
1390         uint64_t falerr:1;
1391         uint64_t coldet:1;
1392         uint64_t ifgerr:1;
1393         uint64_t reserved_16_18:3;
1394         uint64_t pause_drp:1;
1395         uint64_t loc_fault:1;
1396         uint64_t rem_fault:1;
1397         uint64_t bad_seq:1;
1398         uint64_t bad_term:1;
1399         uint64_t unsop:1;
1400         uint64_t uneop:1;
1401         uint64_t undat:1;
1402         uint64_t hg2fld:1;
1403         uint64_t hg2cc:1;
1404         uint64_t reserved_29_63:35;
1405 #endif
1406     } cn52xx;
1407     struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1408 #ifdef __BIG_ENDIAN_BITFIELD
1409         uint64_t reserved_27_63:37;
1410         uint64_t undat:1;
1411         uint64_t uneop:1;
1412         uint64_t unsop:1;
1413         uint64_t bad_term:1;
1414         uint64_t bad_seq:1;
1415         uint64_t rem_fault:1;
1416         uint64_t loc_fault:1;
1417         uint64_t pause_drp:1;
1418         uint64_t reserved_16_18:3;
1419         uint64_t ifgerr:1;
1420         uint64_t coldet:1;
1421         uint64_t falerr:1;
1422         uint64_t rsverr:1;
1423         uint64_t pcterr:1;
1424         uint64_t ovrerr:1;
1425         uint64_t reserved_9_9:1;
1426         uint64_t skperr:1;
1427         uint64_t rcverr:1;
1428         uint64_t reserved_5_6:2;
1429         uint64_t fcserr:1;
1430         uint64_t jabber:1;
1431         uint64_t reserved_2_2:1;
1432         uint64_t carext:1;
1433         uint64_t reserved_0_0:1;
1434 #else
1435         uint64_t reserved_0_0:1;
1436         uint64_t carext:1;
1437         uint64_t reserved_2_2:1;
1438         uint64_t jabber:1;
1439         uint64_t fcserr:1;
1440         uint64_t reserved_5_6:2;
1441         uint64_t rcverr:1;
1442         uint64_t skperr:1;
1443         uint64_t reserved_9_9:1;
1444         uint64_t ovrerr:1;
1445         uint64_t pcterr:1;
1446         uint64_t rsverr:1;
1447         uint64_t falerr:1;
1448         uint64_t coldet:1;
1449         uint64_t ifgerr:1;
1450         uint64_t reserved_16_18:3;
1451         uint64_t pause_drp:1;
1452         uint64_t loc_fault:1;
1453         uint64_t rem_fault:1;
1454         uint64_t bad_seq:1;
1455         uint64_t bad_term:1;
1456         uint64_t unsop:1;
1457         uint64_t uneop:1;
1458         uint64_t undat:1;
1459         uint64_t reserved_27_63:37;
1460 #endif
1461     } cn56xxp1;
1462     struct cvmx_gmxx_rxx_int_reg_cn58xx {
1463 #ifdef __BIG_ENDIAN_BITFIELD
1464         uint64_t reserved_20_63:44;
1465         uint64_t pause_drp:1;
1466         uint64_t phy_dupx:1;
1467         uint64_t phy_spd:1;
1468         uint64_t phy_link:1;
1469         uint64_t ifgerr:1;
1470         uint64_t coldet:1;
1471         uint64_t falerr:1;
1472         uint64_t rsverr:1;
1473         uint64_t pcterr:1;
1474         uint64_t ovrerr:1;
1475         uint64_t niberr:1;
1476         uint64_t skperr:1;
1477         uint64_t rcverr:1;
1478         uint64_t lenerr:1;
1479         uint64_t alnerr:1;
1480         uint64_t fcserr:1;
1481         uint64_t jabber:1;
1482         uint64_t maxerr:1;
1483         uint64_t carext:1;
1484         uint64_t minerr:1;
1485 #else
1486         uint64_t minerr:1;
1487         uint64_t carext:1;
1488         uint64_t maxerr:1;
1489         uint64_t jabber:1;
1490         uint64_t fcserr:1;
1491         uint64_t alnerr:1;
1492         uint64_t lenerr:1;
1493         uint64_t rcverr:1;
1494         uint64_t skperr:1;
1495         uint64_t niberr:1;
1496         uint64_t ovrerr:1;
1497         uint64_t pcterr:1;
1498         uint64_t rsverr:1;
1499         uint64_t falerr:1;
1500         uint64_t coldet:1;
1501         uint64_t ifgerr:1;
1502         uint64_t phy_link:1;
1503         uint64_t phy_spd:1;
1504         uint64_t phy_dupx:1;
1505         uint64_t pause_drp:1;
1506         uint64_t reserved_20_63:44;
1507 #endif
1508     } cn58xx;
1509     struct cvmx_gmxx_rxx_int_reg_cn61xx {
1510 #ifdef __BIG_ENDIAN_BITFIELD
1511         uint64_t reserved_29_63:35;
1512         uint64_t hg2cc:1;
1513         uint64_t hg2fld:1;
1514         uint64_t undat:1;
1515         uint64_t uneop:1;
1516         uint64_t unsop:1;
1517         uint64_t bad_term:1;
1518         uint64_t bad_seq:1;
1519         uint64_t rem_fault:1;
1520         uint64_t loc_fault:1;
1521         uint64_t pause_drp:1;
1522         uint64_t reserved_16_18:3;
1523         uint64_t ifgerr:1;
1524         uint64_t coldet:1;
1525         uint64_t falerr:1;
1526         uint64_t rsverr:1;
1527         uint64_t pcterr:1;
1528         uint64_t ovrerr:1;
1529         uint64_t reserved_9_9:1;
1530         uint64_t skperr:1;
1531         uint64_t rcverr:1;
1532         uint64_t reserved_5_6:2;
1533         uint64_t fcserr:1;
1534         uint64_t jabber:1;
1535         uint64_t reserved_2_2:1;
1536         uint64_t carext:1;
1537         uint64_t minerr:1;
1538 #else
1539         uint64_t minerr:1;
1540         uint64_t carext:1;
1541         uint64_t reserved_2_2:1;
1542         uint64_t jabber:1;
1543         uint64_t fcserr:1;
1544         uint64_t reserved_5_6:2;
1545         uint64_t rcverr:1;
1546         uint64_t skperr:1;
1547         uint64_t reserved_9_9:1;
1548         uint64_t ovrerr:1;
1549         uint64_t pcterr:1;
1550         uint64_t rsverr:1;
1551         uint64_t falerr:1;
1552         uint64_t coldet:1;
1553         uint64_t ifgerr:1;
1554         uint64_t reserved_16_18:3;
1555         uint64_t pause_drp:1;
1556         uint64_t loc_fault:1;
1557         uint64_t rem_fault:1;
1558         uint64_t bad_seq:1;
1559         uint64_t bad_term:1;
1560         uint64_t unsop:1;
1561         uint64_t uneop:1;
1562         uint64_t undat:1;
1563         uint64_t hg2fld:1;
1564         uint64_t hg2cc:1;
1565         uint64_t reserved_29_63:35;
1566 #endif
1567     } cn61xx;
1568 };
1569 
1570 union cvmx_gmxx_rxx_jabber {
1571     uint64_t u64;
1572     struct cvmx_gmxx_rxx_jabber_s {
1573 #ifdef __BIG_ENDIAN_BITFIELD
1574         uint64_t reserved_16_63:48;
1575         uint64_t cnt:16;
1576 #else
1577         uint64_t cnt:16;
1578         uint64_t reserved_16_63:48;
1579 #endif
1580     } s;
1581 };
1582 
1583 union cvmx_gmxx_rxx_rx_inbnd {
1584     uint64_t u64;
1585     struct cvmx_gmxx_rxx_rx_inbnd_s {
1586 #ifdef __BIG_ENDIAN_BITFIELD
1587         uint64_t reserved_4_63:60;
1588         uint64_t duplex:1;
1589         uint64_t speed:2;
1590         uint64_t status:1;
1591 #else
1592         uint64_t status:1;
1593         uint64_t speed:2;
1594         uint64_t duplex:1;
1595         uint64_t reserved_4_63:60;
1596 #endif
1597     } s;
1598 };
1599 
1600 union cvmx_gmxx_rx_prts {
1601     uint64_t u64;
1602     struct cvmx_gmxx_rx_prts_s {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604         uint64_t reserved_3_63:61;
1605         uint64_t prts:3;
1606 #else
1607         uint64_t prts:3;
1608         uint64_t reserved_3_63:61;
1609 #endif
1610     } s;
1611 };
1612 
1613 union cvmx_gmxx_rx_xaui_ctl {
1614     uint64_t u64;
1615     struct cvmx_gmxx_rx_xaui_ctl_s {
1616 #ifdef __BIG_ENDIAN_BITFIELD
1617         uint64_t reserved_2_63:62;
1618         uint64_t status:2;
1619 #else
1620         uint64_t status:2;
1621         uint64_t reserved_2_63:62;
1622 #endif
1623     } s;
1624 };
1625 
1626 union cvmx_gmxx_txx_thresh {
1627     uint64_t u64;
1628     struct cvmx_gmxx_txx_thresh_s {
1629 #ifdef __BIG_ENDIAN_BITFIELD
1630         uint64_t reserved_10_63:54;
1631         uint64_t cnt:10;
1632 #else
1633         uint64_t cnt:10;
1634         uint64_t reserved_10_63:54;
1635 #endif
1636     } s;
1637     struct cvmx_gmxx_txx_thresh_cn30xx {
1638 #ifdef __BIG_ENDIAN_BITFIELD
1639         uint64_t reserved_7_63:57;
1640         uint64_t cnt:7;
1641 #else
1642         uint64_t cnt:7;
1643         uint64_t reserved_7_63:57;
1644 #endif
1645     } cn30xx;
1646     struct cvmx_gmxx_txx_thresh_cn38xx {
1647 #ifdef __BIG_ENDIAN_BITFIELD
1648         uint64_t reserved_9_63:55;
1649         uint64_t cnt:9;
1650 #else
1651         uint64_t cnt:9;
1652         uint64_t reserved_9_63:55;
1653 #endif
1654     } cn38xx;
1655 };
1656 
1657 union cvmx_gmxx_tx_int_en {
1658     uint64_t u64;
1659     struct cvmx_gmxx_tx_int_en_s {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661         uint64_t reserved_25_63:39;
1662         uint64_t xchange:1;
1663         uint64_t ptp_lost:4;
1664         uint64_t late_col:4;
1665         uint64_t xsdef:4;
1666         uint64_t xscol:4;
1667         uint64_t reserved_6_7:2;
1668         uint64_t undflw:4;
1669         uint64_t reserved_1_1:1;
1670         uint64_t pko_nxa:1;
1671 #else
1672         uint64_t pko_nxa:1;
1673         uint64_t reserved_1_1:1;
1674         uint64_t undflw:4;
1675         uint64_t reserved_6_7:2;
1676         uint64_t xscol:4;
1677         uint64_t xsdef:4;
1678         uint64_t late_col:4;
1679         uint64_t ptp_lost:4;
1680         uint64_t xchange:1;
1681         uint64_t reserved_25_63:39;
1682 #endif
1683     } s;
1684     struct cvmx_gmxx_tx_int_en_cn30xx {
1685 #ifdef __BIG_ENDIAN_BITFIELD
1686         uint64_t reserved_19_63:45;
1687         uint64_t late_col:3;
1688         uint64_t reserved_15_15:1;
1689         uint64_t xsdef:3;
1690         uint64_t reserved_11_11:1;
1691         uint64_t xscol:3;
1692         uint64_t reserved_5_7:3;
1693         uint64_t undflw:3;
1694         uint64_t reserved_1_1:1;
1695         uint64_t pko_nxa:1;
1696 #else
1697         uint64_t pko_nxa:1;
1698         uint64_t reserved_1_1:1;
1699         uint64_t undflw:3;
1700         uint64_t reserved_5_7:3;
1701         uint64_t xscol:3;
1702         uint64_t reserved_11_11:1;
1703         uint64_t xsdef:3;
1704         uint64_t reserved_15_15:1;
1705         uint64_t late_col:3;
1706         uint64_t reserved_19_63:45;
1707 #endif
1708     } cn30xx;
1709     struct cvmx_gmxx_tx_int_en_cn31xx {
1710 #ifdef __BIG_ENDIAN_BITFIELD
1711         uint64_t reserved_15_63:49;
1712         uint64_t xsdef:3;
1713         uint64_t reserved_11_11:1;
1714         uint64_t xscol:3;
1715         uint64_t reserved_5_7:3;
1716         uint64_t undflw:3;
1717         uint64_t reserved_1_1:1;
1718         uint64_t pko_nxa:1;
1719 #else
1720         uint64_t pko_nxa:1;
1721         uint64_t reserved_1_1:1;
1722         uint64_t undflw:3;
1723         uint64_t reserved_5_7:3;
1724         uint64_t xscol:3;
1725         uint64_t reserved_11_11:1;
1726         uint64_t xsdef:3;
1727         uint64_t reserved_15_63:49;
1728 #endif
1729     } cn31xx;
1730     struct cvmx_gmxx_tx_int_en_cn38xx {
1731 #ifdef __BIG_ENDIAN_BITFIELD
1732         uint64_t reserved_20_63:44;
1733         uint64_t late_col:4;
1734         uint64_t xsdef:4;
1735         uint64_t xscol:4;
1736         uint64_t reserved_6_7:2;
1737         uint64_t undflw:4;
1738         uint64_t ncb_nxa:1;
1739         uint64_t pko_nxa:1;
1740 #else
1741         uint64_t pko_nxa:1;
1742         uint64_t ncb_nxa:1;
1743         uint64_t undflw:4;
1744         uint64_t reserved_6_7:2;
1745         uint64_t xscol:4;
1746         uint64_t xsdef:4;
1747         uint64_t late_col:4;
1748         uint64_t reserved_20_63:44;
1749 #endif
1750     } cn38xx;
1751     struct cvmx_gmxx_tx_int_en_cn38xxp2 {
1752 #ifdef __BIG_ENDIAN_BITFIELD
1753         uint64_t reserved_16_63:48;
1754         uint64_t xsdef:4;
1755         uint64_t xscol:4;
1756         uint64_t reserved_6_7:2;
1757         uint64_t undflw:4;
1758         uint64_t ncb_nxa:1;
1759         uint64_t pko_nxa:1;
1760 #else
1761         uint64_t pko_nxa:1;
1762         uint64_t ncb_nxa:1;
1763         uint64_t undflw:4;
1764         uint64_t reserved_6_7:2;
1765         uint64_t xscol:4;
1766         uint64_t xsdef:4;
1767         uint64_t reserved_16_63:48;
1768 #endif
1769     } cn38xxp2;
1770     struct cvmx_gmxx_tx_int_en_cn52xx {
1771 #ifdef __BIG_ENDIAN_BITFIELD
1772         uint64_t reserved_20_63:44;
1773         uint64_t late_col:4;
1774         uint64_t xsdef:4;
1775         uint64_t xscol:4;
1776         uint64_t reserved_6_7:2;
1777         uint64_t undflw:4;
1778         uint64_t reserved_1_1:1;
1779         uint64_t pko_nxa:1;
1780 #else
1781         uint64_t pko_nxa:1;
1782         uint64_t reserved_1_1:1;
1783         uint64_t undflw:4;
1784         uint64_t reserved_6_7:2;
1785         uint64_t xscol:4;
1786         uint64_t xsdef:4;
1787         uint64_t late_col:4;
1788         uint64_t reserved_20_63:44;
1789 #endif
1790     } cn52xx;
1791     struct cvmx_gmxx_tx_int_en_cn63xx {
1792 #ifdef __BIG_ENDIAN_BITFIELD
1793         uint64_t reserved_24_63:40;
1794         uint64_t ptp_lost:4;
1795         uint64_t late_col:4;
1796         uint64_t xsdef:4;
1797         uint64_t xscol:4;
1798         uint64_t reserved_6_7:2;
1799         uint64_t undflw:4;
1800         uint64_t reserved_1_1:1;
1801         uint64_t pko_nxa:1;
1802 #else
1803         uint64_t pko_nxa:1;
1804         uint64_t reserved_1_1:1;
1805         uint64_t undflw:4;
1806         uint64_t reserved_6_7:2;
1807         uint64_t xscol:4;
1808         uint64_t xsdef:4;
1809         uint64_t late_col:4;
1810         uint64_t ptp_lost:4;
1811         uint64_t reserved_24_63:40;
1812 #endif
1813     } cn63xx;
1814     struct cvmx_gmxx_tx_int_en_cn68xx {
1815 #ifdef __BIG_ENDIAN_BITFIELD
1816         uint64_t reserved_25_63:39;
1817         uint64_t xchange:1;
1818         uint64_t ptp_lost:4;
1819         uint64_t late_col:4;
1820         uint64_t xsdef:4;
1821         uint64_t xscol:4;
1822         uint64_t reserved_6_7:2;
1823         uint64_t undflw:4;
1824         uint64_t pko_nxp:1;
1825         uint64_t pko_nxa:1;
1826 #else
1827         uint64_t pko_nxa:1;
1828         uint64_t pko_nxp:1;
1829         uint64_t undflw:4;
1830         uint64_t reserved_6_7:2;
1831         uint64_t xscol:4;
1832         uint64_t xsdef:4;
1833         uint64_t late_col:4;
1834         uint64_t ptp_lost:4;
1835         uint64_t xchange:1;
1836         uint64_t reserved_25_63:39;
1837 #endif
1838     } cn68xx;
1839     struct cvmx_gmxx_tx_int_en_cnf71xx {
1840 #ifdef __BIG_ENDIAN_BITFIELD
1841         uint64_t reserved_25_63:39;
1842         uint64_t xchange:1;
1843         uint64_t reserved_22_23:2;
1844         uint64_t ptp_lost:2;
1845         uint64_t reserved_18_19:2;
1846         uint64_t late_col:2;
1847         uint64_t reserved_14_15:2;
1848         uint64_t xsdef:2;
1849         uint64_t reserved_10_11:2;
1850         uint64_t xscol:2;
1851         uint64_t reserved_4_7:4;
1852         uint64_t undflw:2;
1853         uint64_t reserved_1_1:1;
1854         uint64_t pko_nxa:1;
1855 #else
1856         uint64_t pko_nxa:1;
1857         uint64_t reserved_1_1:1;
1858         uint64_t undflw:2;
1859         uint64_t reserved_4_7:4;
1860         uint64_t xscol:2;
1861         uint64_t reserved_10_11:2;
1862         uint64_t xsdef:2;
1863         uint64_t reserved_14_15:2;
1864         uint64_t late_col:2;
1865         uint64_t reserved_18_19:2;
1866         uint64_t ptp_lost:2;
1867         uint64_t reserved_22_23:2;
1868         uint64_t xchange:1;
1869         uint64_t reserved_25_63:39;
1870 #endif
1871     } cnf71xx;
1872 };
1873 
1874 union cvmx_gmxx_tx_int_reg {
1875     uint64_t u64;
1876     struct cvmx_gmxx_tx_int_reg_s {
1877 #ifdef __BIG_ENDIAN_BITFIELD
1878         uint64_t reserved_25_63:39;
1879         uint64_t xchange:1;
1880         uint64_t ptp_lost:4;
1881         uint64_t late_col:4;
1882         uint64_t xsdef:4;
1883         uint64_t xscol:4;
1884         uint64_t reserved_6_7:2;
1885         uint64_t undflw:4;
1886         uint64_t reserved_1_1:1;
1887         uint64_t pko_nxa:1;
1888 #else
1889         uint64_t pko_nxa:1;
1890         uint64_t reserved_1_1:1;
1891         uint64_t undflw:4;
1892         uint64_t reserved_6_7:2;
1893         uint64_t xscol:4;
1894         uint64_t xsdef:4;
1895         uint64_t late_col:4;
1896         uint64_t ptp_lost:4;
1897         uint64_t xchange:1;
1898         uint64_t reserved_25_63:39;
1899 #endif
1900     } s;
1901     struct cvmx_gmxx_tx_int_reg_cn30xx {
1902 #ifdef __BIG_ENDIAN_BITFIELD
1903         uint64_t reserved_19_63:45;
1904         uint64_t late_col:3;
1905         uint64_t reserved_15_15:1;
1906         uint64_t xsdef:3;
1907         uint64_t reserved_11_11:1;
1908         uint64_t xscol:3;
1909         uint64_t reserved_5_7:3;
1910         uint64_t undflw:3;
1911         uint64_t reserved_1_1:1;
1912         uint64_t pko_nxa:1;
1913 #else
1914         uint64_t pko_nxa:1;
1915         uint64_t reserved_1_1:1;
1916         uint64_t undflw:3;
1917         uint64_t reserved_5_7:3;
1918         uint64_t xscol:3;
1919         uint64_t reserved_11_11:1;
1920         uint64_t xsdef:3;
1921         uint64_t reserved_15_15:1;
1922         uint64_t late_col:3;
1923         uint64_t reserved_19_63:45;
1924 #endif
1925     } cn30xx;
1926     struct cvmx_gmxx_tx_int_reg_cn31xx {
1927 #ifdef __BIG_ENDIAN_BITFIELD
1928         uint64_t reserved_15_63:49;
1929         uint64_t xsdef:3;
1930         uint64_t reserved_11_11:1;
1931         uint64_t xscol:3;
1932         uint64_t reserved_5_7:3;
1933         uint64_t undflw:3;
1934         uint64_t reserved_1_1:1;
1935         uint64_t pko_nxa:1;
1936 #else
1937         uint64_t pko_nxa:1;
1938         uint64_t reserved_1_1:1;
1939         uint64_t undflw:3;
1940         uint64_t reserved_5_7:3;
1941         uint64_t xscol:3;
1942         uint64_t reserved_11_11:1;
1943         uint64_t xsdef:3;
1944         uint64_t reserved_15_63:49;
1945 #endif
1946     } cn31xx;
1947     struct cvmx_gmxx_tx_int_reg_cn38xx {
1948 #ifdef __BIG_ENDIAN_BITFIELD
1949         uint64_t reserved_20_63:44;
1950         uint64_t late_col:4;
1951         uint64_t xsdef:4;
1952         uint64_t xscol:4;
1953         uint64_t reserved_6_7:2;
1954         uint64_t undflw:4;
1955         uint64_t ncb_nxa:1;
1956         uint64_t pko_nxa:1;
1957 #else
1958         uint64_t pko_nxa:1;
1959         uint64_t ncb_nxa:1;
1960         uint64_t undflw:4;
1961         uint64_t reserved_6_7:2;
1962         uint64_t xscol:4;
1963         uint64_t xsdef:4;
1964         uint64_t late_col:4;
1965         uint64_t reserved_20_63:44;
1966 #endif
1967     } cn38xx;
1968     struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
1969 #ifdef __BIG_ENDIAN_BITFIELD
1970         uint64_t reserved_16_63:48;
1971         uint64_t xsdef:4;
1972         uint64_t xscol:4;
1973         uint64_t reserved_6_7:2;
1974         uint64_t undflw:4;
1975         uint64_t ncb_nxa:1;
1976         uint64_t pko_nxa:1;
1977 #else
1978         uint64_t pko_nxa:1;
1979         uint64_t ncb_nxa:1;
1980         uint64_t undflw:4;
1981         uint64_t reserved_6_7:2;
1982         uint64_t xscol:4;
1983         uint64_t xsdef:4;
1984         uint64_t reserved_16_63:48;
1985 #endif
1986     } cn38xxp2;
1987     struct cvmx_gmxx_tx_int_reg_cn52xx {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989         uint64_t reserved_20_63:44;
1990         uint64_t late_col:4;
1991         uint64_t xsdef:4;
1992         uint64_t xscol:4;
1993         uint64_t reserved_6_7:2;
1994         uint64_t undflw:4;
1995         uint64_t reserved_1_1:1;
1996         uint64_t pko_nxa:1;
1997 #else
1998         uint64_t pko_nxa:1;
1999         uint64_t reserved_1_1:1;
2000         uint64_t undflw:4;
2001         uint64_t reserved_6_7:2;
2002         uint64_t xscol:4;
2003         uint64_t xsdef:4;
2004         uint64_t late_col:4;
2005         uint64_t reserved_20_63:44;
2006 #endif
2007     } cn52xx;
2008     struct cvmx_gmxx_tx_int_reg_cn63xx {
2009 #ifdef __BIG_ENDIAN_BITFIELD
2010         uint64_t reserved_24_63:40;
2011         uint64_t ptp_lost:4;
2012         uint64_t late_col:4;
2013         uint64_t xsdef:4;
2014         uint64_t xscol:4;
2015         uint64_t reserved_6_7:2;
2016         uint64_t undflw:4;
2017         uint64_t reserved_1_1:1;
2018         uint64_t pko_nxa:1;
2019 #else
2020         uint64_t pko_nxa:1;
2021         uint64_t reserved_1_1:1;
2022         uint64_t undflw:4;
2023         uint64_t reserved_6_7:2;
2024         uint64_t xscol:4;
2025         uint64_t xsdef:4;
2026         uint64_t late_col:4;
2027         uint64_t ptp_lost:4;
2028         uint64_t reserved_24_63:40;
2029 #endif
2030     } cn63xx;
2031     struct cvmx_gmxx_tx_int_reg_cn68xx {
2032 #ifdef __BIG_ENDIAN_BITFIELD
2033         uint64_t reserved_25_63:39;
2034         uint64_t xchange:1;
2035         uint64_t ptp_lost:4;
2036         uint64_t late_col:4;
2037         uint64_t xsdef:4;
2038         uint64_t xscol:4;
2039         uint64_t reserved_6_7:2;
2040         uint64_t undflw:4;
2041         uint64_t pko_nxp:1;
2042         uint64_t pko_nxa:1;
2043 #else
2044         uint64_t pko_nxa:1;
2045         uint64_t pko_nxp:1;
2046         uint64_t undflw:4;
2047         uint64_t reserved_6_7:2;
2048         uint64_t xscol:4;
2049         uint64_t xsdef:4;
2050         uint64_t late_col:4;
2051         uint64_t ptp_lost:4;
2052         uint64_t xchange:1;
2053         uint64_t reserved_25_63:39;
2054 #endif
2055     } cn68xx;
2056     struct cvmx_gmxx_tx_int_reg_cnf71xx {
2057 #ifdef __BIG_ENDIAN_BITFIELD
2058         uint64_t reserved_25_63:39;
2059         uint64_t xchange:1;
2060         uint64_t reserved_22_23:2;
2061         uint64_t ptp_lost:2;
2062         uint64_t reserved_18_19:2;
2063         uint64_t late_col:2;
2064         uint64_t reserved_14_15:2;
2065         uint64_t xsdef:2;
2066         uint64_t reserved_10_11:2;
2067         uint64_t xscol:2;
2068         uint64_t reserved_4_7:4;
2069         uint64_t undflw:2;
2070         uint64_t reserved_1_1:1;
2071         uint64_t pko_nxa:1;
2072 #else
2073         uint64_t pko_nxa:1;
2074         uint64_t reserved_1_1:1;
2075         uint64_t undflw:2;
2076         uint64_t reserved_4_7:4;
2077         uint64_t xscol:2;
2078         uint64_t reserved_10_11:2;
2079         uint64_t xsdef:2;
2080         uint64_t reserved_14_15:2;
2081         uint64_t late_col:2;
2082         uint64_t reserved_18_19:2;
2083         uint64_t ptp_lost:2;
2084         uint64_t reserved_22_23:2;
2085         uint64_t xchange:1;
2086         uint64_t reserved_25_63:39;
2087 #endif
2088     } cnf71xx;
2089 };
2090 
2091 union cvmx_gmxx_tx_ovr_bp {
2092     uint64_t u64;
2093     struct cvmx_gmxx_tx_ovr_bp_s {
2094 #ifdef __BIG_ENDIAN_BITFIELD
2095         uint64_t reserved_48_63:16;
2096         uint64_t tx_prt_bp:16;
2097         uint64_t reserved_12_31:20;
2098         uint64_t en:4;
2099         uint64_t bp:4;
2100         uint64_t ign_full:4;
2101 #else
2102         uint64_t ign_full:4;
2103         uint64_t bp:4;
2104         uint64_t en:4;
2105         uint64_t reserved_12_31:20;
2106         uint64_t tx_prt_bp:16;
2107         uint64_t reserved_48_63:16;
2108 #endif
2109     } s;
2110     struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112         uint64_t reserved_11_63:53;
2113         uint64_t en:3;
2114         uint64_t reserved_7_7:1;
2115         uint64_t bp:3;
2116         uint64_t reserved_3_3:1;
2117         uint64_t ign_full:3;
2118 #else
2119         uint64_t ign_full:3;
2120         uint64_t reserved_3_3:1;
2121         uint64_t bp:3;
2122         uint64_t reserved_7_7:1;
2123         uint64_t en:3;
2124         uint64_t reserved_11_63:53;
2125 #endif
2126     } cn30xx;
2127     struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2128 #ifdef __BIG_ENDIAN_BITFIELD
2129         uint64_t reserved_12_63:52;
2130         uint64_t en:4;
2131         uint64_t bp:4;
2132         uint64_t ign_full:4;
2133 #else
2134         uint64_t ign_full:4;
2135         uint64_t bp:4;
2136         uint64_t en:4;
2137         uint64_t reserved_12_63:52;
2138 #endif
2139     } cn38xx;
2140     struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
2141 #ifdef __BIG_ENDIAN_BITFIELD
2142         uint64_t reserved_48_63:16;
2143         uint64_t tx_prt_bp:16;
2144         uint64_t reserved_10_31:22;
2145         uint64_t en:2;
2146         uint64_t reserved_6_7:2;
2147         uint64_t bp:2;
2148         uint64_t reserved_2_3:2;
2149         uint64_t ign_full:2;
2150 #else
2151         uint64_t ign_full:2;
2152         uint64_t reserved_2_3:2;
2153         uint64_t bp:2;
2154         uint64_t reserved_6_7:2;
2155         uint64_t en:2;
2156         uint64_t reserved_10_31:22;
2157         uint64_t tx_prt_bp:16;
2158         uint64_t reserved_48_63:16;
2159 #endif
2160     } cnf71xx;
2161 };
2162 
2163 union cvmx_gmxx_tx_prts {
2164     uint64_t u64;
2165     struct cvmx_gmxx_tx_prts_s {
2166 #ifdef __BIG_ENDIAN_BITFIELD
2167         uint64_t reserved_5_63:59;
2168         uint64_t prts:5;
2169 #else
2170         uint64_t prts:5;
2171         uint64_t reserved_5_63:59;
2172 #endif
2173     } s;
2174 };
2175 
2176 union cvmx_gmxx_tx_spi_ctl {
2177     uint64_t u64;
2178     struct cvmx_gmxx_tx_spi_ctl_s {
2179 #ifdef __BIG_ENDIAN_BITFIELD
2180         uint64_t reserved_2_63:62;
2181         uint64_t tpa_clr:1;
2182         uint64_t cont_pkt:1;
2183 #else
2184         uint64_t cont_pkt:1;
2185         uint64_t tpa_clr:1;
2186         uint64_t reserved_2_63:62;
2187 #endif
2188     } s;
2189 };
2190 
2191 union cvmx_gmxx_tx_spi_max {
2192     uint64_t u64;
2193     struct cvmx_gmxx_tx_spi_max_s {
2194 #ifdef __BIG_ENDIAN_BITFIELD
2195         uint64_t reserved_23_63:41;
2196         uint64_t slice:7;
2197         uint64_t max2:8;
2198         uint64_t max1:8;
2199 #else
2200         uint64_t max1:8;
2201         uint64_t max2:8;
2202         uint64_t slice:7;
2203         uint64_t reserved_23_63:41;
2204 #endif
2205     } s;
2206     struct cvmx_gmxx_tx_spi_max_cn38xx {
2207 #ifdef __BIG_ENDIAN_BITFIELD
2208         uint64_t reserved_16_63:48;
2209         uint64_t max2:8;
2210         uint64_t max1:8;
2211 #else
2212         uint64_t max1:8;
2213         uint64_t max2:8;
2214         uint64_t reserved_16_63:48;
2215 #endif
2216     } cn38xx;
2217 };
2218 
2219 union cvmx_gmxx_tx_spi_thresh {
2220     uint64_t u64;
2221     struct cvmx_gmxx_tx_spi_thresh_s {
2222 #ifdef __BIG_ENDIAN_BITFIELD
2223         uint64_t reserved_6_63:58;
2224         uint64_t thresh:6;
2225 #else
2226         uint64_t thresh:6;
2227         uint64_t reserved_6_63:58;
2228 #endif
2229     } s;
2230 };
2231 
2232 union cvmx_gmxx_tx_xaui_ctl {
2233     uint64_t u64;
2234     struct cvmx_gmxx_tx_xaui_ctl_s {
2235 #ifdef __BIG_ENDIAN_BITFIELD
2236         uint64_t reserved_11_63:53;
2237         uint64_t hg_pause_hgi:2;
2238         uint64_t hg_en:1;
2239         uint64_t reserved_7_7:1;
2240         uint64_t ls_byp:1;
2241         uint64_t ls:2;
2242         uint64_t reserved_2_3:2;
2243         uint64_t uni_en:1;
2244         uint64_t dic_en:1;
2245 #else
2246         uint64_t dic_en:1;
2247         uint64_t uni_en:1;
2248         uint64_t reserved_2_3:2;
2249         uint64_t ls:2;
2250         uint64_t ls_byp:1;
2251         uint64_t reserved_7_7:1;
2252         uint64_t hg_en:1;
2253         uint64_t hg_pause_hgi:2;
2254         uint64_t reserved_11_63:53;
2255 #endif
2256     } s;
2257 };
2258 
2259 #endif
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