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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_FPA_DEFS_H__
0029 #define __CVMX_FPA_DEFS_H__
0030 
0031 #define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull))
0032 #define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull))
0033 #define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull))
0034 #define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull))
0035 #define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull))
0036 #define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1)
0037 #define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2)
0038 #define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3)
0039 #define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4)
0040 #define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5)
0041 #define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6)
0042 #define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7)
0043 #define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull))
0044 #define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull))
0045 #define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1)
0046 #define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1)
0047 #define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull))
0048 #define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull))
0049 #define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull))
0050 #define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8)
0051 #define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8)
0052 #define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8)
0053 #define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0)
0054 #define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1)
0055 #define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2)
0056 #define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3)
0057 #define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4)
0058 #define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5)
0059 #define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6)
0060 #define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7)
0061 #define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull))
0062 #define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8)
0063 #define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8)
0064 #define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull))
0065 #define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull))
0066 #define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull))
0067 #define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull))
0068 #define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull))
0069 #define CVMX_FPA_CLK_COUNT (CVMX_ADD_IO_SEG(0x00012800000000F0ull))
0070 
0071 union cvmx_fpa_addr_range_error {
0072     uint64_t u64;
0073     struct cvmx_fpa_addr_range_error_s {
0074 #ifdef __BIG_ENDIAN_BITFIELD
0075         uint64_t reserved_38_63:26;
0076         uint64_t pool:5;
0077         uint64_t addr:33;
0078 #else
0079         uint64_t addr:33;
0080         uint64_t pool:5;
0081         uint64_t reserved_38_63:26;
0082 #endif
0083     } s;
0084 };
0085 
0086 union cvmx_fpa_bist_status {
0087     uint64_t u64;
0088     struct cvmx_fpa_bist_status_s {
0089 #ifdef __BIG_ENDIAN_BITFIELD
0090         uint64_t reserved_5_63:59;
0091         uint64_t frd:1;
0092         uint64_t fpf0:1;
0093         uint64_t fpf1:1;
0094         uint64_t ffr:1;
0095         uint64_t fdr:1;
0096 #else
0097         uint64_t fdr:1;
0098         uint64_t ffr:1;
0099         uint64_t fpf1:1;
0100         uint64_t fpf0:1;
0101         uint64_t frd:1;
0102         uint64_t reserved_5_63:59;
0103 #endif
0104     } s;
0105 };
0106 
0107 union cvmx_fpa_ctl_status {
0108     uint64_t u64;
0109     struct cvmx_fpa_ctl_status_s {
0110 #ifdef __BIG_ENDIAN_BITFIELD
0111         uint64_t reserved_21_63:43;
0112         uint64_t free_en:1;
0113         uint64_t ret_off:1;
0114         uint64_t req_off:1;
0115         uint64_t reset:1;
0116         uint64_t use_ldt:1;
0117         uint64_t use_stt:1;
0118         uint64_t enb:1;
0119         uint64_t mem1_err:7;
0120         uint64_t mem0_err:7;
0121 #else
0122         uint64_t mem0_err:7;
0123         uint64_t mem1_err:7;
0124         uint64_t enb:1;
0125         uint64_t use_stt:1;
0126         uint64_t use_ldt:1;
0127         uint64_t reset:1;
0128         uint64_t req_off:1;
0129         uint64_t ret_off:1;
0130         uint64_t free_en:1;
0131         uint64_t reserved_21_63:43;
0132 #endif
0133     } s;
0134     struct cvmx_fpa_ctl_status_cn30xx {
0135 #ifdef __BIG_ENDIAN_BITFIELD
0136         uint64_t reserved_18_63:46;
0137         uint64_t reset:1;
0138         uint64_t use_ldt:1;
0139         uint64_t use_stt:1;
0140         uint64_t enb:1;
0141         uint64_t mem1_err:7;
0142         uint64_t mem0_err:7;
0143 #else
0144         uint64_t mem0_err:7;
0145         uint64_t mem1_err:7;
0146         uint64_t enb:1;
0147         uint64_t use_stt:1;
0148         uint64_t use_ldt:1;
0149         uint64_t reset:1;
0150         uint64_t reserved_18_63:46;
0151 #endif
0152     } cn30xx;
0153 };
0154 
0155 union cvmx_fpa_fpfx_marks {
0156     uint64_t u64;
0157     struct cvmx_fpa_fpfx_marks_s {
0158 #ifdef __BIG_ENDIAN_BITFIELD
0159         uint64_t reserved_22_63:42;
0160         uint64_t fpf_wr:11;
0161         uint64_t fpf_rd:11;
0162 #else
0163         uint64_t fpf_rd:11;
0164         uint64_t fpf_wr:11;
0165         uint64_t reserved_22_63:42;
0166 #endif
0167     } s;
0168 };
0169 
0170 union cvmx_fpa_fpfx_size {
0171     uint64_t u64;
0172     struct cvmx_fpa_fpfx_size_s {
0173 #ifdef __BIG_ENDIAN_BITFIELD
0174         uint64_t reserved_11_63:53;
0175         uint64_t fpf_siz:11;
0176 #else
0177         uint64_t fpf_siz:11;
0178         uint64_t reserved_11_63:53;
0179 #endif
0180     } s;
0181 };
0182 
0183 union cvmx_fpa_fpf0_marks {
0184     uint64_t u64;
0185     struct cvmx_fpa_fpf0_marks_s {
0186 #ifdef __BIG_ENDIAN_BITFIELD
0187         uint64_t reserved_24_63:40;
0188         uint64_t fpf_wr:12;
0189         uint64_t fpf_rd:12;
0190 #else
0191         uint64_t fpf_rd:12;
0192         uint64_t fpf_wr:12;
0193         uint64_t reserved_24_63:40;
0194 #endif
0195     } s;
0196 };
0197 
0198 union cvmx_fpa_fpf0_size {
0199     uint64_t u64;
0200     struct cvmx_fpa_fpf0_size_s {
0201 #ifdef __BIG_ENDIAN_BITFIELD
0202         uint64_t reserved_12_63:52;
0203         uint64_t fpf_siz:12;
0204 #else
0205         uint64_t fpf_siz:12;
0206         uint64_t reserved_12_63:52;
0207 #endif
0208     } s;
0209 };
0210 
0211 union cvmx_fpa_fpf8_marks {
0212     uint64_t u64;
0213     struct cvmx_fpa_fpf8_marks_s {
0214 #ifdef __BIG_ENDIAN_BITFIELD
0215         uint64_t reserved_22_63:42;
0216         uint64_t fpf_wr:11;
0217         uint64_t fpf_rd:11;
0218 #else
0219         uint64_t fpf_rd:11;
0220         uint64_t fpf_wr:11;
0221         uint64_t reserved_22_63:42;
0222 #endif
0223     } s;
0224 };
0225 
0226 union cvmx_fpa_fpf8_size {
0227     uint64_t u64;
0228     struct cvmx_fpa_fpf8_size_s {
0229 #ifdef __BIG_ENDIAN_BITFIELD
0230         uint64_t reserved_12_63:52;
0231         uint64_t fpf_siz:12;
0232 #else
0233         uint64_t fpf_siz:12;
0234         uint64_t reserved_12_63:52;
0235 #endif
0236     } s;
0237 };
0238 
0239 union cvmx_fpa_int_enb {
0240     uint64_t u64;
0241     struct cvmx_fpa_int_enb_s {
0242 #ifdef __BIG_ENDIAN_BITFIELD
0243         uint64_t reserved_50_63:14;
0244         uint64_t paddr_e:1;
0245         uint64_t reserved_44_48:5;
0246         uint64_t free7:1;
0247         uint64_t free6:1;
0248         uint64_t free5:1;
0249         uint64_t free4:1;
0250         uint64_t free3:1;
0251         uint64_t free2:1;
0252         uint64_t free1:1;
0253         uint64_t free0:1;
0254         uint64_t pool7th:1;
0255         uint64_t pool6th:1;
0256         uint64_t pool5th:1;
0257         uint64_t pool4th:1;
0258         uint64_t pool3th:1;
0259         uint64_t pool2th:1;
0260         uint64_t pool1th:1;
0261         uint64_t pool0th:1;
0262         uint64_t q7_perr:1;
0263         uint64_t q7_coff:1;
0264         uint64_t q7_und:1;
0265         uint64_t q6_perr:1;
0266         uint64_t q6_coff:1;
0267         uint64_t q6_und:1;
0268         uint64_t q5_perr:1;
0269         uint64_t q5_coff:1;
0270         uint64_t q5_und:1;
0271         uint64_t q4_perr:1;
0272         uint64_t q4_coff:1;
0273         uint64_t q4_und:1;
0274         uint64_t q3_perr:1;
0275         uint64_t q3_coff:1;
0276         uint64_t q3_und:1;
0277         uint64_t q2_perr:1;
0278         uint64_t q2_coff:1;
0279         uint64_t q2_und:1;
0280         uint64_t q1_perr:1;
0281         uint64_t q1_coff:1;
0282         uint64_t q1_und:1;
0283         uint64_t q0_perr:1;
0284         uint64_t q0_coff:1;
0285         uint64_t q0_und:1;
0286         uint64_t fed1_dbe:1;
0287         uint64_t fed1_sbe:1;
0288         uint64_t fed0_dbe:1;
0289         uint64_t fed0_sbe:1;
0290 #else
0291         uint64_t fed0_sbe:1;
0292         uint64_t fed0_dbe:1;
0293         uint64_t fed1_sbe:1;
0294         uint64_t fed1_dbe:1;
0295         uint64_t q0_und:1;
0296         uint64_t q0_coff:1;
0297         uint64_t q0_perr:1;
0298         uint64_t q1_und:1;
0299         uint64_t q1_coff:1;
0300         uint64_t q1_perr:1;
0301         uint64_t q2_und:1;
0302         uint64_t q2_coff:1;
0303         uint64_t q2_perr:1;
0304         uint64_t q3_und:1;
0305         uint64_t q3_coff:1;
0306         uint64_t q3_perr:1;
0307         uint64_t q4_und:1;
0308         uint64_t q4_coff:1;
0309         uint64_t q4_perr:1;
0310         uint64_t q5_und:1;
0311         uint64_t q5_coff:1;
0312         uint64_t q5_perr:1;
0313         uint64_t q6_und:1;
0314         uint64_t q6_coff:1;
0315         uint64_t q6_perr:1;
0316         uint64_t q7_und:1;
0317         uint64_t q7_coff:1;
0318         uint64_t q7_perr:1;
0319         uint64_t pool0th:1;
0320         uint64_t pool1th:1;
0321         uint64_t pool2th:1;
0322         uint64_t pool3th:1;
0323         uint64_t pool4th:1;
0324         uint64_t pool5th:1;
0325         uint64_t pool6th:1;
0326         uint64_t pool7th:1;
0327         uint64_t free0:1;
0328         uint64_t free1:1;
0329         uint64_t free2:1;
0330         uint64_t free3:1;
0331         uint64_t free4:1;
0332         uint64_t free5:1;
0333         uint64_t free6:1;
0334         uint64_t free7:1;
0335         uint64_t reserved_44_48:5;
0336         uint64_t paddr_e:1;
0337         uint64_t reserved_50_63:14;
0338 #endif
0339     } s;
0340     struct cvmx_fpa_int_enb_cn30xx {
0341 #ifdef __BIG_ENDIAN_BITFIELD
0342         uint64_t reserved_28_63:36;
0343         uint64_t q7_perr:1;
0344         uint64_t q7_coff:1;
0345         uint64_t q7_und:1;
0346         uint64_t q6_perr:1;
0347         uint64_t q6_coff:1;
0348         uint64_t q6_und:1;
0349         uint64_t q5_perr:1;
0350         uint64_t q5_coff:1;
0351         uint64_t q5_und:1;
0352         uint64_t q4_perr:1;
0353         uint64_t q4_coff:1;
0354         uint64_t q4_und:1;
0355         uint64_t q3_perr:1;
0356         uint64_t q3_coff:1;
0357         uint64_t q3_und:1;
0358         uint64_t q2_perr:1;
0359         uint64_t q2_coff:1;
0360         uint64_t q2_und:1;
0361         uint64_t q1_perr:1;
0362         uint64_t q1_coff:1;
0363         uint64_t q1_und:1;
0364         uint64_t q0_perr:1;
0365         uint64_t q0_coff:1;
0366         uint64_t q0_und:1;
0367         uint64_t fed1_dbe:1;
0368         uint64_t fed1_sbe:1;
0369         uint64_t fed0_dbe:1;
0370         uint64_t fed0_sbe:1;
0371 #else
0372         uint64_t fed0_sbe:1;
0373         uint64_t fed0_dbe:1;
0374         uint64_t fed1_sbe:1;
0375         uint64_t fed1_dbe:1;
0376         uint64_t q0_und:1;
0377         uint64_t q0_coff:1;
0378         uint64_t q0_perr:1;
0379         uint64_t q1_und:1;
0380         uint64_t q1_coff:1;
0381         uint64_t q1_perr:1;
0382         uint64_t q2_und:1;
0383         uint64_t q2_coff:1;
0384         uint64_t q2_perr:1;
0385         uint64_t q3_und:1;
0386         uint64_t q3_coff:1;
0387         uint64_t q3_perr:1;
0388         uint64_t q4_und:1;
0389         uint64_t q4_coff:1;
0390         uint64_t q4_perr:1;
0391         uint64_t q5_und:1;
0392         uint64_t q5_coff:1;
0393         uint64_t q5_perr:1;
0394         uint64_t q6_und:1;
0395         uint64_t q6_coff:1;
0396         uint64_t q6_perr:1;
0397         uint64_t q7_und:1;
0398         uint64_t q7_coff:1;
0399         uint64_t q7_perr:1;
0400         uint64_t reserved_28_63:36;
0401 #endif
0402     } cn30xx;
0403     struct cvmx_fpa_int_enb_cn61xx {
0404 #ifdef __BIG_ENDIAN_BITFIELD
0405         uint64_t reserved_50_63:14;
0406         uint64_t paddr_e:1;
0407         uint64_t res_44:5;
0408         uint64_t free7:1;
0409         uint64_t free6:1;
0410         uint64_t free5:1;
0411         uint64_t free4:1;
0412         uint64_t free3:1;
0413         uint64_t free2:1;
0414         uint64_t free1:1;
0415         uint64_t free0:1;
0416         uint64_t pool7th:1;
0417         uint64_t pool6th:1;
0418         uint64_t pool5th:1;
0419         uint64_t pool4th:1;
0420         uint64_t pool3th:1;
0421         uint64_t pool2th:1;
0422         uint64_t pool1th:1;
0423         uint64_t pool0th:1;
0424         uint64_t q7_perr:1;
0425         uint64_t q7_coff:1;
0426         uint64_t q7_und:1;
0427         uint64_t q6_perr:1;
0428         uint64_t q6_coff:1;
0429         uint64_t q6_und:1;
0430         uint64_t q5_perr:1;
0431         uint64_t q5_coff:1;
0432         uint64_t q5_und:1;
0433         uint64_t q4_perr:1;
0434         uint64_t q4_coff:1;
0435         uint64_t q4_und:1;
0436         uint64_t q3_perr:1;
0437         uint64_t q3_coff:1;
0438         uint64_t q3_und:1;
0439         uint64_t q2_perr:1;
0440         uint64_t q2_coff:1;
0441         uint64_t q2_und:1;
0442         uint64_t q1_perr:1;
0443         uint64_t q1_coff:1;
0444         uint64_t q1_und:1;
0445         uint64_t q0_perr:1;
0446         uint64_t q0_coff:1;
0447         uint64_t q0_und:1;
0448         uint64_t fed1_dbe:1;
0449         uint64_t fed1_sbe:1;
0450         uint64_t fed0_dbe:1;
0451         uint64_t fed0_sbe:1;
0452 #else
0453         uint64_t fed0_sbe:1;
0454         uint64_t fed0_dbe:1;
0455         uint64_t fed1_sbe:1;
0456         uint64_t fed1_dbe:1;
0457         uint64_t q0_und:1;
0458         uint64_t q0_coff:1;
0459         uint64_t q0_perr:1;
0460         uint64_t q1_und:1;
0461         uint64_t q1_coff:1;
0462         uint64_t q1_perr:1;
0463         uint64_t q2_und:1;
0464         uint64_t q2_coff:1;
0465         uint64_t q2_perr:1;
0466         uint64_t q3_und:1;
0467         uint64_t q3_coff:1;
0468         uint64_t q3_perr:1;
0469         uint64_t q4_und:1;
0470         uint64_t q4_coff:1;
0471         uint64_t q4_perr:1;
0472         uint64_t q5_und:1;
0473         uint64_t q5_coff:1;
0474         uint64_t q5_perr:1;
0475         uint64_t q6_und:1;
0476         uint64_t q6_coff:1;
0477         uint64_t q6_perr:1;
0478         uint64_t q7_und:1;
0479         uint64_t q7_coff:1;
0480         uint64_t q7_perr:1;
0481         uint64_t pool0th:1;
0482         uint64_t pool1th:1;
0483         uint64_t pool2th:1;
0484         uint64_t pool3th:1;
0485         uint64_t pool4th:1;
0486         uint64_t pool5th:1;
0487         uint64_t pool6th:1;
0488         uint64_t pool7th:1;
0489         uint64_t free0:1;
0490         uint64_t free1:1;
0491         uint64_t free2:1;
0492         uint64_t free3:1;
0493         uint64_t free4:1;
0494         uint64_t free5:1;
0495         uint64_t free6:1;
0496         uint64_t free7:1;
0497         uint64_t res_44:5;
0498         uint64_t paddr_e:1;
0499         uint64_t reserved_50_63:14;
0500 #endif
0501     } cn61xx;
0502     struct cvmx_fpa_int_enb_cn63xx {
0503 #ifdef __BIG_ENDIAN_BITFIELD
0504         uint64_t reserved_44_63:20;
0505         uint64_t free7:1;
0506         uint64_t free6:1;
0507         uint64_t free5:1;
0508         uint64_t free4:1;
0509         uint64_t free3:1;
0510         uint64_t free2:1;
0511         uint64_t free1:1;
0512         uint64_t free0:1;
0513         uint64_t pool7th:1;
0514         uint64_t pool6th:1;
0515         uint64_t pool5th:1;
0516         uint64_t pool4th:1;
0517         uint64_t pool3th:1;
0518         uint64_t pool2th:1;
0519         uint64_t pool1th:1;
0520         uint64_t pool0th:1;
0521         uint64_t q7_perr:1;
0522         uint64_t q7_coff:1;
0523         uint64_t q7_und:1;
0524         uint64_t q6_perr:1;
0525         uint64_t q6_coff:1;
0526         uint64_t q6_und:1;
0527         uint64_t q5_perr:1;
0528         uint64_t q5_coff:1;
0529         uint64_t q5_und:1;
0530         uint64_t q4_perr:1;
0531         uint64_t q4_coff:1;
0532         uint64_t q4_und:1;
0533         uint64_t q3_perr:1;
0534         uint64_t q3_coff:1;
0535         uint64_t q3_und:1;
0536         uint64_t q2_perr:1;
0537         uint64_t q2_coff:1;
0538         uint64_t q2_und:1;
0539         uint64_t q1_perr:1;
0540         uint64_t q1_coff:1;
0541         uint64_t q1_und:1;
0542         uint64_t q0_perr:1;
0543         uint64_t q0_coff:1;
0544         uint64_t q0_und:1;
0545         uint64_t fed1_dbe:1;
0546         uint64_t fed1_sbe:1;
0547         uint64_t fed0_dbe:1;
0548         uint64_t fed0_sbe:1;
0549 #else
0550         uint64_t fed0_sbe:1;
0551         uint64_t fed0_dbe:1;
0552         uint64_t fed1_sbe:1;
0553         uint64_t fed1_dbe:1;
0554         uint64_t q0_und:1;
0555         uint64_t q0_coff:1;
0556         uint64_t q0_perr:1;
0557         uint64_t q1_und:1;
0558         uint64_t q1_coff:1;
0559         uint64_t q1_perr:1;
0560         uint64_t q2_und:1;
0561         uint64_t q2_coff:1;
0562         uint64_t q2_perr:1;
0563         uint64_t q3_und:1;
0564         uint64_t q3_coff:1;
0565         uint64_t q3_perr:1;
0566         uint64_t q4_und:1;
0567         uint64_t q4_coff:1;
0568         uint64_t q4_perr:1;
0569         uint64_t q5_und:1;
0570         uint64_t q5_coff:1;
0571         uint64_t q5_perr:1;
0572         uint64_t q6_und:1;
0573         uint64_t q6_coff:1;
0574         uint64_t q6_perr:1;
0575         uint64_t q7_und:1;
0576         uint64_t q7_coff:1;
0577         uint64_t q7_perr:1;
0578         uint64_t pool0th:1;
0579         uint64_t pool1th:1;
0580         uint64_t pool2th:1;
0581         uint64_t pool3th:1;
0582         uint64_t pool4th:1;
0583         uint64_t pool5th:1;
0584         uint64_t pool6th:1;
0585         uint64_t pool7th:1;
0586         uint64_t free0:1;
0587         uint64_t free1:1;
0588         uint64_t free2:1;
0589         uint64_t free3:1;
0590         uint64_t free4:1;
0591         uint64_t free5:1;
0592         uint64_t free6:1;
0593         uint64_t free7:1;
0594         uint64_t reserved_44_63:20;
0595 #endif
0596     } cn63xx;
0597     struct cvmx_fpa_int_enb_cn68xx {
0598 #ifdef __BIG_ENDIAN_BITFIELD
0599         uint64_t reserved_50_63:14;
0600         uint64_t paddr_e:1;
0601         uint64_t pool8th:1;
0602         uint64_t q8_perr:1;
0603         uint64_t q8_coff:1;
0604         uint64_t q8_und:1;
0605         uint64_t free8:1;
0606         uint64_t free7:1;
0607         uint64_t free6:1;
0608         uint64_t free5:1;
0609         uint64_t free4:1;
0610         uint64_t free3:1;
0611         uint64_t free2:1;
0612         uint64_t free1:1;
0613         uint64_t free0:1;
0614         uint64_t pool7th:1;
0615         uint64_t pool6th:1;
0616         uint64_t pool5th:1;
0617         uint64_t pool4th:1;
0618         uint64_t pool3th:1;
0619         uint64_t pool2th:1;
0620         uint64_t pool1th:1;
0621         uint64_t pool0th:1;
0622         uint64_t q7_perr:1;
0623         uint64_t q7_coff:1;
0624         uint64_t q7_und:1;
0625         uint64_t q6_perr:1;
0626         uint64_t q6_coff:1;
0627         uint64_t q6_und:1;
0628         uint64_t q5_perr:1;
0629         uint64_t q5_coff:1;
0630         uint64_t q5_und:1;
0631         uint64_t q4_perr:1;
0632         uint64_t q4_coff:1;
0633         uint64_t q4_und:1;
0634         uint64_t q3_perr:1;
0635         uint64_t q3_coff:1;
0636         uint64_t q3_und:1;
0637         uint64_t q2_perr:1;
0638         uint64_t q2_coff:1;
0639         uint64_t q2_und:1;
0640         uint64_t q1_perr:1;
0641         uint64_t q1_coff:1;
0642         uint64_t q1_und:1;
0643         uint64_t q0_perr:1;
0644         uint64_t q0_coff:1;
0645         uint64_t q0_und:1;
0646         uint64_t fed1_dbe:1;
0647         uint64_t fed1_sbe:1;
0648         uint64_t fed0_dbe:1;
0649         uint64_t fed0_sbe:1;
0650 #else
0651         uint64_t fed0_sbe:1;
0652         uint64_t fed0_dbe:1;
0653         uint64_t fed1_sbe:1;
0654         uint64_t fed1_dbe:1;
0655         uint64_t q0_und:1;
0656         uint64_t q0_coff:1;
0657         uint64_t q0_perr:1;
0658         uint64_t q1_und:1;
0659         uint64_t q1_coff:1;
0660         uint64_t q1_perr:1;
0661         uint64_t q2_und:1;
0662         uint64_t q2_coff:1;
0663         uint64_t q2_perr:1;
0664         uint64_t q3_und:1;
0665         uint64_t q3_coff:1;
0666         uint64_t q3_perr:1;
0667         uint64_t q4_und:1;
0668         uint64_t q4_coff:1;
0669         uint64_t q4_perr:1;
0670         uint64_t q5_und:1;
0671         uint64_t q5_coff:1;
0672         uint64_t q5_perr:1;
0673         uint64_t q6_und:1;
0674         uint64_t q6_coff:1;
0675         uint64_t q6_perr:1;
0676         uint64_t q7_und:1;
0677         uint64_t q7_coff:1;
0678         uint64_t q7_perr:1;
0679         uint64_t pool0th:1;
0680         uint64_t pool1th:1;
0681         uint64_t pool2th:1;
0682         uint64_t pool3th:1;
0683         uint64_t pool4th:1;
0684         uint64_t pool5th:1;
0685         uint64_t pool6th:1;
0686         uint64_t pool7th:1;
0687         uint64_t free0:1;
0688         uint64_t free1:1;
0689         uint64_t free2:1;
0690         uint64_t free3:1;
0691         uint64_t free4:1;
0692         uint64_t free5:1;
0693         uint64_t free6:1;
0694         uint64_t free7:1;
0695         uint64_t free8:1;
0696         uint64_t q8_und:1;
0697         uint64_t q8_coff:1;
0698         uint64_t q8_perr:1;
0699         uint64_t pool8th:1;
0700         uint64_t paddr_e:1;
0701         uint64_t reserved_50_63:14;
0702 #endif
0703     } cn68xx;
0704 };
0705 
0706 union cvmx_fpa_int_sum {
0707     uint64_t u64;
0708     struct cvmx_fpa_int_sum_s {
0709 #ifdef __BIG_ENDIAN_BITFIELD
0710         uint64_t reserved_50_63:14;
0711         uint64_t paddr_e:1;
0712         uint64_t pool8th:1;
0713         uint64_t q8_perr:1;
0714         uint64_t q8_coff:1;
0715         uint64_t q8_und:1;
0716         uint64_t free8:1;
0717         uint64_t free7:1;
0718         uint64_t free6:1;
0719         uint64_t free5:1;
0720         uint64_t free4:1;
0721         uint64_t free3:1;
0722         uint64_t free2:1;
0723         uint64_t free1:1;
0724         uint64_t free0:1;
0725         uint64_t pool7th:1;
0726         uint64_t pool6th:1;
0727         uint64_t pool5th:1;
0728         uint64_t pool4th:1;
0729         uint64_t pool3th:1;
0730         uint64_t pool2th:1;
0731         uint64_t pool1th:1;
0732         uint64_t pool0th:1;
0733         uint64_t q7_perr:1;
0734         uint64_t q7_coff:1;
0735         uint64_t q7_und:1;
0736         uint64_t q6_perr:1;
0737         uint64_t q6_coff:1;
0738         uint64_t q6_und:1;
0739         uint64_t q5_perr:1;
0740         uint64_t q5_coff:1;
0741         uint64_t q5_und:1;
0742         uint64_t q4_perr:1;
0743         uint64_t q4_coff:1;
0744         uint64_t q4_und:1;
0745         uint64_t q3_perr:1;
0746         uint64_t q3_coff:1;
0747         uint64_t q3_und:1;
0748         uint64_t q2_perr:1;
0749         uint64_t q2_coff:1;
0750         uint64_t q2_und:1;
0751         uint64_t q1_perr:1;
0752         uint64_t q1_coff:1;
0753         uint64_t q1_und:1;
0754         uint64_t q0_perr:1;
0755         uint64_t q0_coff:1;
0756         uint64_t q0_und:1;
0757         uint64_t fed1_dbe:1;
0758         uint64_t fed1_sbe:1;
0759         uint64_t fed0_dbe:1;
0760         uint64_t fed0_sbe:1;
0761 #else
0762         uint64_t fed0_sbe:1;
0763         uint64_t fed0_dbe:1;
0764         uint64_t fed1_sbe:1;
0765         uint64_t fed1_dbe:1;
0766         uint64_t q0_und:1;
0767         uint64_t q0_coff:1;
0768         uint64_t q0_perr:1;
0769         uint64_t q1_und:1;
0770         uint64_t q1_coff:1;
0771         uint64_t q1_perr:1;
0772         uint64_t q2_und:1;
0773         uint64_t q2_coff:1;
0774         uint64_t q2_perr:1;
0775         uint64_t q3_und:1;
0776         uint64_t q3_coff:1;
0777         uint64_t q3_perr:1;
0778         uint64_t q4_und:1;
0779         uint64_t q4_coff:1;
0780         uint64_t q4_perr:1;
0781         uint64_t q5_und:1;
0782         uint64_t q5_coff:1;
0783         uint64_t q5_perr:1;
0784         uint64_t q6_und:1;
0785         uint64_t q6_coff:1;
0786         uint64_t q6_perr:1;
0787         uint64_t q7_und:1;
0788         uint64_t q7_coff:1;
0789         uint64_t q7_perr:1;
0790         uint64_t pool0th:1;
0791         uint64_t pool1th:1;
0792         uint64_t pool2th:1;
0793         uint64_t pool3th:1;
0794         uint64_t pool4th:1;
0795         uint64_t pool5th:1;
0796         uint64_t pool6th:1;
0797         uint64_t pool7th:1;
0798         uint64_t free0:1;
0799         uint64_t free1:1;
0800         uint64_t free2:1;
0801         uint64_t free3:1;
0802         uint64_t free4:1;
0803         uint64_t free5:1;
0804         uint64_t free6:1;
0805         uint64_t free7:1;
0806         uint64_t free8:1;
0807         uint64_t q8_und:1;
0808         uint64_t q8_coff:1;
0809         uint64_t q8_perr:1;
0810         uint64_t pool8th:1;
0811         uint64_t paddr_e:1;
0812         uint64_t reserved_50_63:14;
0813 #endif
0814     } s;
0815     struct cvmx_fpa_int_sum_cn30xx {
0816 #ifdef __BIG_ENDIAN_BITFIELD
0817         uint64_t reserved_28_63:36;
0818         uint64_t q7_perr:1;
0819         uint64_t q7_coff:1;
0820         uint64_t q7_und:1;
0821         uint64_t q6_perr:1;
0822         uint64_t q6_coff:1;
0823         uint64_t q6_und:1;
0824         uint64_t q5_perr:1;
0825         uint64_t q5_coff:1;
0826         uint64_t q5_und:1;
0827         uint64_t q4_perr:1;
0828         uint64_t q4_coff:1;
0829         uint64_t q4_und:1;
0830         uint64_t q3_perr:1;
0831         uint64_t q3_coff:1;
0832         uint64_t q3_und:1;
0833         uint64_t q2_perr:1;
0834         uint64_t q2_coff:1;
0835         uint64_t q2_und:1;
0836         uint64_t q1_perr:1;
0837         uint64_t q1_coff:1;
0838         uint64_t q1_und:1;
0839         uint64_t q0_perr:1;
0840         uint64_t q0_coff:1;
0841         uint64_t q0_und:1;
0842         uint64_t fed1_dbe:1;
0843         uint64_t fed1_sbe:1;
0844         uint64_t fed0_dbe:1;
0845         uint64_t fed0_sbe:1;
0846 #else
0847         uint64_t fed0_sbe:1;
0848         uint64_t fed0_dbe:1;
0849         uint64_t fed1_sbe:1;
0850         uint64_t fed1_dbe:1;
0851         uint64_t q0_und:1;
0852         uint64_t q0_coff:1;
0853         uint64_t q0_perr:1;
0854         uint64_t q1_und:1;
0855         uint64_t q1_coff:1;
0856         uint64_t q1_perr:1;
0857         uint64_t q2_und:1;
0858         uint64_t q2_coff:1;
0859         uint64_t q2_perr:1;
0860         uint64_t q3_und:1;
0861         uint64_t q3_coff:1;
0862         uint64_t q3_perr:1;
0863         uint64_t q4_und:1;
0864         uint64_t q4_coff:1;
0865         uint64_t q4_perr:1;
0866         uint64_t q5_und:1;
0867         uint64_t q5_coff:1;
0868         uint64_t q5_perr:1;
0869         uint64_t q6_und:1;
0870         uint64_t q6_coff:1;
0871         uint64_t q6_perr:1;
0872         uint64_t q7_und:1;
0873         uint64_t q7_coff:1;
0874         uint64_t q7_perr:1;
0875         uint64_t reserved_28_63:36;
0876 #endif
0877     } cn30xx;
0878     struct cvmx_fpa_int_sum_cn61xx {
0879 #ifdef __BIG_ENDIAN_BITFIELD
0880         uint64_t reserved_50_63:14;
0881         uint64_t paddr_e:1;
0882         uint64_t reserved_44_48:5;
0883         uint64_t free7:1;
0884         uint64_t free6:1;
0885         uint64_t free5:1;
0886         uint64_t free4:1;
0887         uint64_t free3:1;
0888         uint64_t free2:1;
0889         uint64_t free1:1;
0890         uint64_t free0:1;
0891         uint64_t pool7th:1;
0892         uint64_t pool6th:1;
0893         uint64_t pool5th:1;
0894         uint64_t pool4th:1;
0895         uint64_t pool3th:1;
0896         uint64_t pool2th:1;
0897         uint64_t pool1th:1;
0898         uint64_t pool0th:1;
0899         uint64_t q7_perr:1;
0900         uint64_t q7_coff:1;
0901         uint64_t q7_und:1;
0902         uint64_t q6_perr:1;
0903         uint64_t q6_coff:1;
0904         uint64_t q6_und:1;
0905         uint64_t q5_perr:1;
0906         uint64_t q5_coff:1;
0907         uint64_t q5_und:1;
0908         uint64_t q4_perr:1;
0909         uint64_t q4_coff:1;
0910         uint64_t q4_und:1;
0911         uint64_t q3_perr:1;
0912         uint64_t q3_coff:1;
0913         uint64_t q3_und:1;
0914         uint64_t q2_perr:1;
0915         uint64_t q2_coff:1;
0916         uint64_t q2_und:1;
0917         uint64_t q1_perr:1;
0918         uint64_t q1_coff:1;
0919         uint64_t q1_und:1;
0920         uint64_t q0_perr:1;
0921         uint64_t q0_coff:1;
0922         uint64_t q0_und:1;
0923         uint64_t fed1_dbe:1;
0924         uint64_t fed1_sbe:1;
0925         uint64_t fed0_dbe:1;
0926         uint64_t fed0_sbe:1;
0927 #else
0928         uint64_t fed0_sbe:1;
0929         uint64_t fed0_dbe:1;
0930         uint64_t fed1_sbe:1;
0931         uint64_t fed1_dbe:1;
0932         uint64_t q0_und:1;
0933         uint64_t q0_coff:1;
0934         uint64_t q0_perr:1;
0935         uint64_t q1_und:1;
0936         uint64_t q1_coff:1;
0937         uint64_t q1_perr:1;
0938         uint64_t q2_und:1;
0939         uint64_t q2_coff:1;
0940         uint64_t q2_perr:1;
0941         uint64_t q3_und:1;
0942         uint64_t q3_coff:1;
0943         uint64_t q3_perr:1;
0944         uint64_t q4_und:1;
0945         uint64_t q4_coff:1;
0946         uint64_t q4_perr:1;
0947         uint64_t q5_und:1;
0948         uint64_t q5_coff:1;
0949         uint64_t q5_perr:1;
0950         uint64_t q6_und:1;
0951         uint64_t q6_coff:1;
0952         uint64_t q6_perr:1;
0953         uint64_t q7_und:1;
0954         uint64_t q7_coff:1;
0955         uint64_t q7_perr:1;
0956         uint64_t pool0th:1;
0957         uint64_t pool1th:1;
0958         uint64_t pool2th:1;
0959         uint64_t pool3th:1;
0960         uint64_t pool4th:1;
0961         uint64_t pool5th:1;
0962         uint64_t pool6th:1;
0963         uint64_t pool7th:1;
0964         uint64_t free0:1;
0965         uint64_t free1:1;
0966         uint64_t free2:1;
0967         uint64_t free3:1;
0968         uint64_t free4:1;
0969         uint64_t free5:1;
0970         uint64_t free6:1;
0971         uint64_t free7:1;
0972         uint64_t reserved_44_48:5;
0973         uint64_t paddr_e:1;
0974         uint64_t reserved_50_63:14;
0975 #endif
0976     } cn61xx;
0977     struct cvmx_fpa_int_sum_cn63xx {
0978 #ifdef __BIG_ENDIAN_BITFIELD
0979         uint64_t reserved_44_63:20;
0980         uint64_t free7:1;
0981         uint64_t free6:1;
0982         uint64_t free5:1;
0983         uint64_t free4:1;
0984         uint64_t free3:1;
0985         uint64_t free2:1;
0986         uint64_t free1:1;
0987         uint64_t free0:1;
0988         uint64_t pool7th:1;
0989         uint64_t pool6th:1;
0990         uint64_t pool5th:1;
0991         uint64_t pool4th:1;
0992         uint64_t pool3th:1;
0993         uint64_t pool2th:1;
0994         uint64_t pool1th:1;
0995         uint64_t pool0th:1;
0996         uint64_t q7_perr:1;
0997         uint64_t q7_coff:1;
0998         uint64_t q7_und:1;
0999         uint64_t q6_perr:1;
1000         uint64_t q6_coff:1;
1001         uint64_t q6_und:1;
1002         uint64_t q5_perr:1;
1003         uint64_t q5_coff:1;
1004         uint64_t q5_und:1;
1005         uint64_t q4_perr:1;
1006         uint64_t q4_coff:1;
1007         uint64_t q4_und:1;
1008         uint64_t q3_perr:1;
1009         uint64_t q3_coff:1;
1010         uint64_t q3_und:1;
1011         uint64_t q2_perr:1;
1012         uint64_t q2_coff:1;
1013         uint64_t q2_und:1;
1014         uint64_t q1_perr:1;
1015         uint64_t q1_coff:1;
1016         uint64_t q1_und:1;
1017         uint64_t q0_perr:1;
1018         uint64_t q0_coff:1;
1019         uint64_t q0_und:1;
1020         uint64_t fed1_dbe:1;
1021         uint64_t fed1_sbe:1;
1022         uint64_t fed0_dbe:1;
1023         uint64_t fed0_sbe:1;
1024 #else
1025         uint64_t fed0_sbe:1;
1026         uint64_t fed0_dbe:1;
1027         uint64_t fed1_sbe:1;
1028         uint64_t fed1_dbe:1;
1029         uint64_t q0_und:1;
1030         uint64_t q0_coff:1;
1031         uint64_t q0_perr:1;
1032         uint64_t q1_und:1;
1033         uint64_t q1_coff:1;
1034         uint64_t q1_perr:1;
1035         uint64_t q2_und:1;
1036         uint64_t q2_coff:1;
1037         uint64_t q2_perr:1;
1038         uint64_t q3_und:1;
1039         uint64_t q3_coff:1;
1040         uint64_t q3_perr:1;
1041         uint64_t q4_und:1;
1042         uint64_t q4_coff:1;
1043         uint64_t q4_perr:1;
1044         uint64_t q5_und:1;
1045         uint64_t q5_coff:1;
1046         uint64_t q5_perr:1;
1047         uint64_t q6_und:1;
1048         uint64_t q6_coff:1;
1049         uint64_t q6_perr:1;
1050         uint64_t q7_und:1;
1051         uint64_t q7_coff:1;
1052         uint64_t q7_perr:1;
1053         uint64_t pool0th:1;
1054         uint64_t pool1th:1;
1055         uint64_t pool2th:1;
1056         uint64_t pool3th:1;
1057         uint64_t pool4th:1;
1058         uint64_t pool5th:1;
1059         uint64_t pool6th:1;
1060         uint64_t pool7th:1;
1061         uint64_t free0:1;
1062         uint64_t free1:1;
1063         uint64_t free2:1;
1064         uint64_t free3:1;
1065         uint64_t free4:1;
1066         uint64_t free5:1;
1067         uint64_t free6:1;
1068         uint64_t free7:1;
1069         uint64_t reserved_44_63:20;
1070 #endif
1071     } cn63xx;
1072 };
1073 
1074 union cvmx_fpa_packet_threshold {
1075     uint64_t u64;
1076     struct cvmx_fpa_packet_threshold_s {
1077 #ifdef __BIG_ENDIAN_BITFIELD
1078         uint64_t reserved_32_63:32;
1079         uint64_t thresh:32;
1080 #else
1081         uint64_t thresh:32;
1082         uint64_t reserved_32_63:32;
1083 #endif
1084     } s;
1085 };
1086 
1087 union cvmx_fpa_poolx_end_addr {
1088     uint64_t u64;
1089     struct cvmx_fpa_poolx_end_addr_s {
1090 #ifdef __BIG_ENDIAN_BITFIELD
1091         uint64_t reserved_33_63:31;
1092         uint64_t addr:33;
1093 #else
1094         uint64_t addr:33;
1095         uint64_t reserved_33_63:31;
1096 #endif
1097     } s;
1098 };
1099 
1100 union cvmx_fpa_poolx_start_addr {
1101     uint64_t u64;
1102     struct cvmx_fpa_poolx_start_addr_s {
1103 #ifdef __BIG_ENDIAN_BITFIELD
1104         uint64_t reserved_33_63:31;
1105         uint64_t addr:33;
1106 #else
1107         uint64_t addr:33;
1108         uint64_t reserved_33_63:31;
1109 #endif
1110     } s;
1111 };
1112 
1113 union cvmx_fpa_poolx_threshold {
1114     uint64_t u64;
1115     struct cvmx_fpa_poolx_threshold_s {
1116 #ifdef __BIG_ENDIAN_BITFIELD
1117         uint64_t reserved_32_63:32;
1118         uint64_t thresh:32;
1119 #else
1120         uint64_t thresh:32;
1121         uint64_t reserved_32_63:32;
1122 #endif
1123     } s;
1124     struct cvmx_fpa_poolx_threshold_cn61xx {
1125 #ifdef __BIG_ENDIAN_BITFIELD
1126         uint64_t reserved_29_63:35;
1127         uint64_t thresh:29;
1128 #else
1129         uint64_t thresh:29;
1130         uint64_t reserved_29_63:35;
1131 #endif
1132     } cn61xx;
1133 };
1134 
1135 union cvmx_fpa_quex_available {
1136     uint64_t u64;
1137     struct cvmx_fpa_quex_available_s {
1138 #ifdef __BIG_ENDIAN_BITFIELD
1139         uint64_t reserved_32_63:32;
1140         uint64_t que_siz:32;
1141 #else
1142         uint64_t que_siz:32;
1143         uint64_t reserved_32_63:32;
1144 #endif
1145     } s;
1146     struct cvmx_fpa_quex_available_cn30xx {
1147 #ifdef __BIG_ENDIAN_BITFIELD
1148         uint64_t reserved_29_63:35;
1149         uint64_t que_siz:29;
1150 #else
1151         uint64_t que_siz:29;
1152         uint64_t reserved_29_63:35;
1153 #endif
1154     } cn30xx;
1155 };
1156 
1157 union cvmx_fpa_quex_page_index {
1158     uint64_t u64;
1159     struct cvmx_fpa_quex_page_index_s {
1160 #ifdef __BIG_ENDIAN_BITFIELD
1161         uint64_t reserved_25_63:39;
1162         uint64_t pg_num:25;
1163 #else
1164         uint64_t pg_num:25;
1165         uint64_t reserved_25_63:39;
1166 #endif
1167     } s;
1168 };
1169 
1170 union cvmx_fpa_que8_page_index {
1171     uint64_t u64;
1172     struct cvmx_fpa_que8_page_index_s {
1173 #ifdef __BIG_ENDIAN_BITFIELD
1174         uint64_t reserved_25_63:39;
1175         uint64_t pg_num:25;
1176 #else
1177         uint64_t pg_num:25;
1178         uint64_t reserved_25_63:39;
1179 #endif
1180     } s;
1181 };
1182 
1183 union cvmx_fpa_que_act {
1184     uint64_t u64;
1185     struct cvmx_fpa_que_act_s {
1186 #ifdef __BIG_ENDIAN_BITFIELD
1187         uint64_t reserved_29_63:35;
1188         uint64_t act_que:3;
1189         uint64_t act_indx:26;
1190 #else
1191         uint64_t act_indx:26;
1192         uint64_t act_que:3;
1193         uint64_t reserved_29_63:35;
1194 #endif
1195     } s;
1196 };
1197 
1198 union cvmx_fpa_que_exp {
1199     uint64_t u64;
1200     struct cvmx_fpa_que_exp_s {
1201 #ifdef __BIG_ENDIAN_BITFIELD
1202         uint64_t reserved_29_63:35;
1203         uint64_t exp_que:3;
1204         uint64_t exp_indx:26;
1205 #else
1206         uint64_t exp_indx:26;
1207         uint64_t exp_que:3;
1208         uint64_t reserved_29_63:35;
1209 #endif
1210     } s;
1211 };
1212 
1213 union cvmx_fpa_wart_ctl {
1214     uint64_t u64;
1215     struct cvmx_fpa_wart_ctl_s {
1216 #ifdef __BIG_ENDIAN_BITFIELD
1217         uint64_t reserved_16_63:48;
1218         uint64_t ctl:16;
1219 #else
1220         uint64_t ctl:16;
1221         uint64_t reserved_16_63:48;
1222 #endif
1223     } s;
1224 };
1225 
1226 union cvmx_fpa_wart_status {
1227     uint64_t u64;
1228     struct cvmx_fpa_wart_status_s {
1229 #ifdef __BIG_ENDIAN_BITFIELD
1230         uint64_t reserved_32_63:32;
1231         uint64_t status:32;
1232 #else
1233         uint64_t status:32;
1234         uint64_t reserved_32_63:32;
1235 #endif
1236     } s;
1237 };
1238 
1239 union cvmx_fpa_wqe_threshold {
1240     uint64_t u64;
1241     struct cvmx_fpa_wqe_threshold_s {
1242 #ifdef __BIG_ENDIAN_BITFIELD
1243         uint64_t reserved_32_63:32;
1244         uint64_t thresh:32;
1245 #else
1246         uint64_t thresh:32;
1247         uint64_t reserved_32_63:32;
1248 #endif
1249     } s;
1250 };
1251 
1252 #endif
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