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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_DPI_DEFS_H__
0029 #define __CVMX_DPI_DEFS_H__
0030 
0031 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
0032 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
0033 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
0034 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
0035 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
0036 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
0037 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
0038 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
0039 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
0040 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
0041 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
0042 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
0043 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
0044 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
0045 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
0046 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
0047 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
0048 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
0049 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
0050 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
0051 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
0052 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
0053 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
0054 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
0055 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
0056 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
0057 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
0058 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
0059 {
0060     switch (cvmx_get_octeon_family()) {
0061     case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
0062         return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
0063     case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
0064     case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
0065     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0066 
0067         if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
0068             return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
0069 
0070         if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
0071             return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
0072         return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
0073     case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
0074         return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
0075     }
0076     return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
0077 }
0078 
0079 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
0080 
0081 union cvmx_dpi_bist_status {
0082     uint64_t u64;
0083     struct cvmx_dpi_bist_status_s {
0084 #ifdef __BIG_ENDIAN_BITFIELD
0085         uint64_t reserved_47_63:17;
0086         uint64_t bist:47;
0087 #else
0088         uint64_t bist:47;
0089         uint64_t reserved_47_63:17;
0090 #endif
0091     } s;
0092     struct cvmx_dpi_bist_status_cn63xx {
0093 #ifdef __BIG_ENDIAN_BITFIELD
0094         uint64_t reserved_45_63:19;
0095         uint64_t bist:45;
0096 #else
0097         uint64_t bist:45;
0098         uint64_t reserved_45_63:19;
0099 #endif
0100     } cn63xx;
0101     struct cvmx_dpi_bist_status_cn63xxp1 {
0102 #ifdef __BIG_ENDIAN_BITFIELD
0103         uint64_t reserved_37_63:27;
0104         uint64_t bist:37;
0105 #else
0106         uint64_t bist:37;
0107         uint64_t reserved_37_63:27;
0108 #endif
0109     } cn63xxp1;
0110 };
0111 
0112 union cvmx_dpi_ctl {
0113     uint64_t u64;
0114     struct cvmx_dpi_ctl_s {
0115 #ifdef __BIG_ENDIAN_BITFIELD
0116         uint64_t reserved_2_63:62;
0117         uint64_t clk:1;
0118         uint64_t en:1;
0119 #else
0120         uint64_t en:1;
0121         uint64_t clk:1;
0122         uint64_t reserved_2_63:62;
0123 #endif
0124     } s;
0125     struct cvmx_dpi_ctl_cn61xx {
0126 #ifdef __BIG_ENDIAN_BITFIELD
0127         uint64_t reserved_1_63:63;
0128         uint64_t en:1;
0129 #else
0130         uint64_t en:1;
0131         uint64_t reserved_1_63:63;
0132 #endif
0133     } cn61xx;
0134 };
0135 
0136 union cvmx_dpi_dmax_counts {
0137     uint64_t u64;
0138     struct cvmx_dpi_dmax_counts_s {
0139 #ifdef __BIG_ENDIAN_BITFIELD
0140         uint64_t reserved_39_63:25;
0141         uint64_t fcnt:7;
0142         uint64_t dbell:32;
0143 #else
0144         uint64_t dbell:32;
0145         uint64_t fcnt:7;
0146         uint64_t reserved_39_63:25;
0147 #endif
0148     } s;
0149 };
0150 
0151 union cvmx_dpi_dmax_dbell {
0152     uint64_t u64;
0153     struct cvmx_dpi_dmax_dbell_s {
0154 #ifdef __BIG_ENDIAN_BITFIELD
0155         uint64_t reserved_16_63:48;
0156         uint64_t dbell:16;
0157 #else
0158         uint64_t dbell:16;
0159         uint64_t reserved_16_63:48;
0160 #endif
0161     } s;
0162 };
0163 
0164 union cvmx_dpi_dmax_err_rsp_status {
0165     uint64_t u64;
0166     struct cvmx_dpi_dmax_err_rsp_status_s {
0167 #ifdef __BIG_ENDIAN_BITFIELD
0168         uint64_t reserved_6_63:58;
0169         uint64_t status:6;
0170 #else
0171         uint64_t status:6;
0172         uint64_t reserved_6_63:58;
0173 #endif
0174     } s;
0175 };
0176 
0177 union cvmx_dpi_dmax_ibuff_saddr {
0178     uint64_t u64;
0179     struct cvmx_dpi_dmax_ibuff_saddr_s {
0180 #ifdef __BIG_ENDIAN_BITFIELD
0181         uint64_t reserved_62_63:2;
0182         uint64_t csize:14;
0183         uint64_t reserved_41_47:7;
0184         uint64_t idle:1;
0185         uint64_t saddr:33;
0186         uint64_t reserved_0_6:7;
0187 #else
0188         uint64_t reserved_0_6:7;
0189         uint64_t saddr:33;
0190         uint64_t idle:1;
0191         uint64_t reserved_41_47:7;
0192         uint64_t csize:14;
0193         uint64_t reserved_62_63:2;
0194 #endif
0195     } s;
0196     struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
0197 #ifdef __BIG_ENDIAN_BITFIELD
0198         uint64_t reserved_62_63:2;
0199         uint64_t csize:14;
0200         uint64_t reserved_41_47:7;
0201         uint64_t idle:1;
0202         uint64_t reserved_36_39:4;
0203         uint64_t saddr:29;
0204         uint64_t reserved_0_6:7;
0205 #else
0206         uint64_t reserved_0_6:7;
0207         uint64_t saddr:29;
0208         uint64_t reserved_36_39:4;
0209         uint64_t idle:1;
0210         uint64_t reserved_41_47:7;
0211         uint64_t csize:14;
0212         uint64_t reserved_62_63:2;
0213 #endif
0214     } cn61xx;
0215 };
0216 
0217 union cvmx_dpi_dmax_iflight {
0218     uint64_t u64;
0219     struct cvmx_dpi_dmax_iflight_s {
0220 #ifdef __BIG_ENDIAN_BITFIELD
0221         uint64_t reserved_3_63:61;
0222         uint64_t cnt:3;
0223 #else
0224         uint64_t cnt:3;
0225         uint64_t reserved_3_63:61;
0226 #endif
0227     } s;
0228 };
0229 
0230 union cvmx_dpi_dmax_naddr {
0231     uint64_t u64;
0232     struct cvmx_dpi_dmax_naddr_s {
0233 #ifdef __BIG_ENDIAN_BITFIELD
0234         uint64_t reserved_40_63:24;
0235         uint64_t addr:40;
0236 #else
0237         uint64_t addr:40;
0238         uint64_t reserved_40_63:24;
0239 #endif
0240     } s;
0241     struct cvmx_dpi_dmax_naddr_cn61xx {
0242 #ifdef __BIG_ENDIAN_BITFIELD
0243         uint64_t reserved_36_63:28;
0244         uint64_t addr:36;
0245 #else
0246         uint64_t addr:36;
0247         uint64_t reserved_36_63:28;
0248 #endif
0249     } cn61xx;
0250 };
0251 
0252 union cvmx_dpi_dmax_reqbnk0 {
0253     uint64_t u64;
0254     struct cvmx_dpi_dmax_reqbnk0_s {
0255 #ifdef __BIG_ENDIAN_BITFIELD
0256         uint64_t state:64;
0257 #else
0258         uint64_t state:64;
0259 #endif
0260     } s;
0261 };
0262 
0263 union cvmx_dpi_dmax_reqbnk1 {
0264     uint64_t u64;
0265     struct cvmx_dpi_dmax_reqbnk1_s {
0266 #ifdef __BIG_ENDIAN_BITFIELD
0267         uint64_t state:64;
0268 #else
0269         uint64_t state:64;
0270 #endif
0271     } s;
0272 };
0273 
0274 union cvmx_dpi_dma_control {
0275     uint64_t u64;
0276     struct cvmx_dpi_dma_control_s {
0277 #ifdef __BIG_ENDIAN_BITFIELD
0278         uint64_t reserved_62_63:2;
0279         uint64_t dici_mode:1;
0280         uint64_t pkt_en1:1;
0281         uint64_t ffp_dis:1;
0282         uint64_t commit_mode:1;
0283         uint64_t pkt_hp:1;
0284         uint64_t pkt_en:1;
0285         uint64_t reserved_54_55:2;
0286         uint64_t dma_enb:6;
0287         uint64_t reserved_34_47:14;
0288         uint64_t b0_lend:1;
0289         uint64_t dwb_denb:1;
0290         uint64_t dwb_ichk:9;
0291         uint64_t fpa_que:3;
0292         uint64_t o_add1:1;
0293         uint64_t o_ro:1;
0294         uint64_t o_ns:1;
0295         uint64_t o_es:2;
0296         uint64_t o_mode:1;
0297         uint64_t reserved_0_13:14;
0298 #else
0299         uint64_t reserved_0_13:14;
0300         uint64_t o_mode:1;
0301         uint64_t o_es:2;
0302         uint64_t o_ns:1;
0303         uint64_t o_ro:1;
0304         uint64_t o_add1:1;
0305         uint64_t fpa_que:3;
0306         uint64_t dwb_ichk:9;
0307         uint64_t dwb_denb:1;
0308         uint64_t b0_lend:1;
0309         uint64_t reserved_34_47:14;
0310         uint64_t dma_enb:6;
0311         uint64_t reserved_54_55:2;
0312         uint64_t pkt_en:1;
0313         uint64_t pkt_hp:1;
0314         uint64_t commit_mode:1;
0315         uint64_t ffp_dis:1;
0316         uint64_t pkt_en1:1;
0317         uint64_t dici_mode:1;
0318         uint64_t reserved_62_63:2;
0319 #endif
0320     } s;
0321     struct cvmx_dpi_dma_control_cn63xx {
0322 #ifdef __BIG_ENDIAN_BITFIELD
0323         uint64_t reserved_61_63:3;
0324         uint64_t pkt_en1:1;
0325         uint64_t ffp_dis:1;
0326         uint64_t commit_mode:1;
0327         uint64_t pkt_hp:1;
0328         uint64_t pkt_en:1;
0329         uint64_t reserved_54_55:2;
0330         uint64_t dma_enb:6;
0331         uint64_t reserved_34_47:14;
0332         uint64_t b0_lend:1;
0333         uint64_t dwb_denb:1;
0334         uint64_t dwb_ichk:9;
0335         uint64_t fpa_que:3;
0336         uint64_t o_add1:1;
0337         uint64_t o_ro:1;
0338         uint64_t o_ns:1;
0339         uint64_t o_es:2;
0340         uint64_t o_mode:1;
0341         uint64_t reserved_0_13:14;
0342 #else
0343         uint64_t reserved_0_13:14;
0344         uint64_t o_mode:1;
0345         uint64_t o_es:2;
0346         uint64_t o_ns:1;
0347         uint64_t o_ro:1;
0348         uint64_t o_add1:1;
0349         uint64_t fpa_que:3;
0350         uint64_t dwb_ichk:9;
0351         uint64_t dwb_denb:1;
0352         uint64_t b0_lend:1;
0353         uint64_t reserved_34_47:14;
0354         uint64_t dma_enb:6;
0355         uint64_t reserved_54_55:2;
0356         uint64_t pkt_en:1;
0357         uint64_t pkt_hp:1;
0358         uint64_t commit_mode:1;
0359         uint64_t ffp_dis:1;
0360         uint64_t pkt_en1:1;
0361         uint64_t reserved_61_63:3;
0362 #endif
0363     } cn63xx;
0364     struct cvmx_dpi_dma_control_cn63xxp1 {
0365 #ifdef __BIG_ENDIAN_BITFIELD
0366         uint64_t reserved_59_63:5;
0367         uint64_t commit_mode:1;
0368         uint64_t pkt_hp:1;
0369         uint64_t pkt_en:1;
0370         uint64_t reserved_54_55:2;
0371         uint64_t dma_enb:6;
0372         uint64_t reserved_34_47:14;
0373         uint64_t b0_lend:1;
0374         uint64_t dwb_denb:1;
0375         uint64_t dwb_ichk:9;
0376         uint64_t fpa_que:3;
0377         uint64_t o_add1:1;
0378         uint64_t o_ro:1;
0379         uint64_t o_ns:1;
0380         uint64_t o_es:2;
0381         uint64_t o_mode:1;
0382         uint64_t reserved_0_13:14;
0383 #else
0384         uint64_t reserved_0_13:14;
0385         uint64_t o_mode:1;
0386         uint64_t o_es:2;
0387         uint64_t o_ns:1;
0388         uint64_t o_ro:1;
0389         uint64_t o_add1:1;
0390         uint64_t fpa_que:3;
0391         uint64_t dwb_ichk:9;
0392         uint64_t dwb_denb:1;
0393         uint64_t b0_lend:1;
0394         uint64_t reserved_34_47:14;
0395         uint64_t dma_enb:6;
0396         uint64_t reserved_54_55:2;
0397         uint64_t pkt_en:1;
0398         uint64_t pkt_hp:1;
0399         uint64_t commit_mode:1;
0400         uint64_t reserved_59_63:5;
0401 #endif
0402     } cn63xxp1;
0403 };
0404 
0405 union cvmx_dpi_dma_engx_en {
0406     uint64_t u64;
0407     struct cvmx_dpi_dma_engx_en_s {
0408 #ifdef __BIG_ENDIAN_BITFIELD
0409         uint64_t reserved_8_63:56;
0410         uint64_t qen:8;
0411 #else
0412         uint64_t qen:8;
0413         uint64_t reserved_8_63:56;
0414 #endif
0415     } s;
0416 };
0417 
0418 union cvmx_dpi_dma_ppx_cnt {
0419     uint64_t u64;
0420     struct cvmx_dpi_dma_ppx_cnt_s {
0421 #ifdef __BIG_ENDIAN_BITFIELD
0422         uint64_t reserved_16_63:48;
0423         uint64_t cnt:16;
0424 #else
0425         uint64_t cnt:16;
0426         uint64_t reserved_16_63:48;
0427 #endif
0428     } s;
0429 };
0430 
0431 union cvmx_dpi_engx_buf {
0432     uint64_t u64;
0433     struct cvmx_dpi_engx_buf_s {
0434 #ifdef __BIG_ENDIAN_BITFIELD
0435         uint64_t reserved_37_63:27;
0436         uint64_t compblks:5;
0437         uint64_t reserved_9_31:23;
0438         uint64_t base:5;
0439         uint64_t blks:4;
0440 #else
0441         uint64_t blks:4;
0442         uint64_t base:5;
0443         uint64_t reserved_9_31:23;
0444         uint64_t compblks:5;
0445         uint64_t reserved_37_63:27;
0446 #endif
0447     } s;
0448     struct cvmx_dpi_engx_buf_cn63xx {
0449 #ifdef __BIG_ENDIAN_BITFIELD
0450         uint64_t reserved_8_63:56;
0451         uint64_t base:4;
0452         uint64_t blks:4;
0453 #else
0454         uint64_t blks:4;
0455         uint64_t base:4;
0456         uint64_t reserved_8_63:56;
0457 #endif
0458     } cn63xx;
0459 };
0460 
0461 union cvmx_dpi_info_reg {
0462     uint64_t u64;
0463     struct cvmx_dpi_info_reg_s {
0464 #ifdef __BIG_ENDIAN_BITFIELD
0465         uint64_t reserved_8_63:56;
0466         uint64_t ffp:4;
0467         uint64_t reserved_2_3:2;
0468         uint64_t ncb:1;
0469         uint64_t rsl:1;
0470 #else
0471         uint64_t rsl:1;
0472         uint64_t ncb:1;
0473         uint64_t reserved_2_3:2;
0474         uint64_t ffp:4;
0475         uint64_t reserved_8_63:56;
0476 #endif
0477     } s;
0478     struct cvmx_dpi_info_reg_cn63xxp1 {
0479 #ifdef __BIG_ENDIAN_BITFIELD
0480         uint64_t reserved_2_63:62;
0481         uint64_t ncb:1;
0482         uint64_t rsl:1;
0483 #else
0484         uint64_t rsl:1;
0485         uint64_t ncb:1;
0486         uint64_t reserved_2_63:62;
0487 #endif
0488     } cn63xxp1;
0489 };
0490 
0491 union cvmx_dpi_int_en {
0492     uint64_t u64;
0493     struct cvmx_dpi_int_en_s {
0494 #ifdef __BIG_ENDIAN_BITFIELD
0495         uint64_t reserved_28_63:36;
0496         uint64_t sprt3_rst:1;
0497         uint64_t sprt2_rst:1;
0498         uint64_t sprt1_rst:1;
0499         uint64_t sprt0_rst:1;
0500         uint64_t reserved_23_23:1;
0501         uint64_t req_badfil:1;
0502         uint64_t req_inull:1;
0503         uint64_t req_anull:1;
0504         uint64_t req_undflw:1;
0505         uint64_t req_ovrflw:1;
0506         uint64_t req_badlen:1;
0507         uint64_t req_badadr:1;
0508         uint64_t dmadbo:8;
0509         uint64_t reserved_2_7:6;
0510         uint64_t nfovr:1;
0511         uint64_t nderr:1;
0512 #else
0513         uint64_t nderr:1;
0514         uint64_t nfovr:1;
0515         uint64_t reserved_2_7:6;
0516         uint64_t dmadbo:8;
0517         uint64_t req_badadr:1;
0518         uint64_t req_badlen:1;
0519         uint64_t req_ovrflw:1;
0520         uint64_t req_undflw:1;
0521         uint64_t req_anull:1;
0522         uint64_t req_inull:1;
0523         uint64_t req_badfil:1;
0524         uint64_t reserved_23_23:1;
0525         uint64_t sprt0_rst:1;
0526         uint64_t sprt1_rst:1;
0527         uint64_t sprt2_rst:1;
0528         uint64_t sprt3_rst:1;
0529         uint64_t reserved_28_63:36;
0530 #endif
0531     } s;
0532     struct cvmx_dpi_int_en_cn63xx {
0533 #ifdef __BIG_ENDIAN_BITFIELD
0534         uint64_t reserved_26_63:38;
0535         uint64_t sprt1_rst:1;
0536         uint64_t sprt0_rst:1;
0537         uint64_t reserved_23_23:1;
0538         uint64_t req_badfil:1;
0539         uint64_t req_inull:1;
0540         uint64_t req_anull:1;
0541         uint64_t req_undflw:1;
0542         uint64_t req_ovrflw:1;
0543         uint64_t req_badlen:1;
0544         uint64_t req_badadr:1;
0545         uint64_t dmadbo:8;
0546         uint64_t reserved_2_7:6;
0547         uint64_t nfovr:1;
0548         uint64_t nderr:1;
0549 #else
0550         uint64_t nderr:1;
0551         uint64_t nfovr:1;
0552         uint64_t reserved_2_7:6;
0553         uint64_t dmadbo:8;
0554         uint64_t req_badadr:1;
0555         uint64_t req_badlen:1;
0556         uint64_t req_ovrflw:1;
0557         uint64_t req_undflw:1;
0558         uint64_t req_anull:1;
0559         uint64_t req_inull:1;
0560         uint64_t req_badfil:1;
0561         uint64_t reserved_23_23:1;
0562         uint64_t sprt0_rst:1;
0563         uint64_t sprt1_rst:1;
0564         uint64_t reserved_26_63:38;
0565 #endif
0566     } cn63xx;
0567 };
0568 
0569 union cvmx_dpi_int_reg {
0570     uint64_t u64;
0571     struct cvmx_dpi_int_reg_s {
0572 #ifdef __BIG_ENDIAN_BITFIELD
0573         uint64_t reserved_28_63:36;
0574         uint64_t sprt3_rst:1;
0575         uint64_t sprt2_rst:1;
0576         uint64_t sprt1_rst:1;
0577         uint64_t sprt0_rst:1;
0578         uint64_t reserved_23_23:1;
0579         uint64_t req_badfil:1;
0580         uint64_t req_inull:1;
0581         uint64_t req_anull:1;
0582         uint64_t req_undflw:1;
0583         uint64_t req_ovrflw:1;
0584         uint64_t req_badlen:1;
0585         uint64_t req_badadr:1;
0586         uint64_t dmadbo:8;
0587         uint64_t reserved_2_7:6;
0588         uint64_t nfovr:1;
0589         uint64_t nderr:1;
0590 #else
0591         uint64_t nderr:1;
0592         uint64_t nfovr:1;
0593         uint64_t reserved_2_7:6;
0594         uint64_t dmadbo:8;
0595         uint64_t req_badadr:1;
0596         uint64_t req_badlen:1;
0597         uint64_t req_ovrflw:1;
0598         uint64_t req_undflw:1;
0599         uint64_t req_anull:1;
0600         uint64_t req_inull:1;
0601         uint64_t req_badfil:1;
0602         uint64_t reserved_23_23:1;
0603         uint64_t sprt0_rst:1;
0604         uint64_t sprt1_rst:1;
0605         uint64_t sprt2_rst:1;
0606         uint64_t sprt3_rst:1;
0607         uint64_t reserved_28_63:36;
0608 #endif
0609     } s;
0610     struct cvmx_dpi_int_reg_cn63xx {
0611 #ifdef __BIG_ENDIAN_BITFIELD
0612         uint64_t reserved_26_63:38;
0613         uint64_t sprt1_rst:1;
0614         uint64_t sprt0_rst:1;
0615         uint64_t reserved_23_23:1;
0616         uint64_t req_badfil:1;
0617         uint64_t req_inull:1;
0618         uint64_t req_anull:1;
0619         uint64_t req_undflw:1;
0620         uint64_t req_ovrflw:1;
0621         uint64_t req_badlen:1;
0622         uint64_t req_badadr:1;
0623         uint64_t dmadbo:8;
0624         uint64_t reserved_2_7:6;
0625         uint64_t nfovr:1;
0626         uint64_t nderr:1;
0627 #else
0628         uint64_t nderr:1;
0629         uint64_t nfovr:1;
0630         uint64_t reserved_2_7:6;
0631         uint64_t dmadbo:8;
0632         uint64_t req_badadr:1;
0633         uint64_t req_badlen:1;
0634         uint64_t req_ovrflw:1;
0635         uint64_t req_undflw:1;
0636         uint64_t req_anull:1;
0637         uint64_t req_inull:1;
0638         uint64_t req_badfil:1;
0639         uint64_t reserved_23_23:1;
0640         uint64_t sprt0_rst:1;
0641         uint64_t sprt1_rst:1;
0642         uint64_t reserved_26_63:38;
0643 #endif
0644     } cn63xx;
0645 };
0646 
0647 union cvmx_dpi_ncbx_cfg {
0648     uint64_t u64;
0649     struct cvmx_dpi_ncbx_cfg_s {
0650 #ifdef __BIG_ENDIAN_BITFIELD
0651         uint64_t reserved_6_63:58;
0652         uint64_t molr:6;
0653 #else
0654         uint64_t molr:6;
0655         uint64_t reserved_6_63:58;
0656 #endif
0657     } s;
0658 };
0659 
0660 union cvmx_dpi_pint_info {
0661     uint64_t u64;
0662     struct cvmx_dpi_pint_info_s {
0663 #ifdef __BIG_ENDIAN_BITFIELD
0664         uint64_t reserved_14_63:50;
0665         uint64_t iinfo:6;
0666         uint64_t reserved_6_7:2;
0667         uint64_t sinfo:6;
0668 #else
0669         uint64_t sinfo:6;
0670         uint64_t reserved_6_7:2;
0671         uint64_t iinfo:6;
0672         uint64_t reserved_14_63:50;
0673 #endif
0674     } s;
0675 };
0676 
0677 union cvmx_dpi_pkt_err_rsp {
0678     uint64_t u64;
0679     struct cvmx_dpi_pkt_err_rsp_s {
0680 #ifdef __BIG_ENDIAN_BITFIELD
0681         uint64_t reserved_1_63:63;
0682         uint64_t pkterr:1;
0683 #else
0684         uint64_t pkterr:1;
0685         uint64_t reserved_1_63:63;
0686 #endif
0687     } s;
0688 };
0689 
0690 union cvmx_dpi_req_err_rsp {
0691     uint64_t u64;
0692     struct cvmx_dpi_req_err_rsp_s {
0693 #ifdef __BIG_ENDIAN_BITFIELD
0694         uint64_t reserved_8_63:56;
0695         uint64_t qerr:8;
0696 #else
0697         uint64_t qerr:8;
0698         uint64_t reserved_8_63:56;
0699 #endif
0700     } s;
0701 };
0702 
0703 union cvmx_dpi_req_err_rsp_en {
0704     uint64_t u64;
0705     struct cvmx_dpi_req_err_rsp_en_s {
0706 #ifdef __BIG_ENDIAN_BITFIELD
0707         uint64_t reserved_8_63:56;
0708         uint64_t en:8;
0709 #else
0710         uint64_t en:8;
0711         uint64_t reserved_8_63:56;
0712 #endif
0713     } s;
0714 };
0715 
0716 union cvmx_dpi_req_err_rst {
0717     uint64_t u64;
0718     struct cvmx_dpi_req_err_rst_s {
0719 #ifdef __BIG_ENDIAN_BITFIELD
0720         uint64_t reserved_8_63:56;
0721         uint64_t qerr:8;
0722 #else
0723         uint64_t qerr:8;
0724         uint64_t reserved_8_63:56;
0725 #endif
0726     } s;
0727 };
0728 
0729 union cvmx_dpi_req_err_rst_en {
0730     uint64_t u64;
0731     struct cvmx_dpi_req_err_rst_en_s {
0732 #ifdef __BIG_ENDIAN_BITFIELD
0733         uint64_t reserved_8_63:56;
0734         uint64_t en:8;
0735 #else
0736         uint64_t en:8;
0737         uint64_t reserved_8_63:56;
0738 #endif
0739     } s;
0740 };
0741 
0742 union cvmx_dpi_req_err_skip_comp {
0743     uint64_t u64;
0744     struct cvmx_dpi_req_err_skip_comp_s {
0745 #ifdef __BIG_ENDIAN_BITFIELD
0746         uint64_t reserved_24_63:40;
0747         uint64_t en_rst:8;
0748         uint64_t reserved_8_15:8;
0749         uint64_t en_rsp:8;
0750 #else
0751         uint64_t en_rsp:8;
0752         uint64_t reserved_8_15:8;
0753         uint64_t en_rst:8;
0754         uint64_t reserved_24_63:40;
0755 #endif
0756     } s;
0757 };
0758 
0759 union cvmx_dpi_req_gbl_en {
0760     uint64_t u64;
0761     struct cvmx_dpi_req_gbl_en_s {
0762 #ifdef __BIG_ENDIAN_BITFIELD
0763         uint64_t reserved_8_63:56;
0764         uint64_t qen:8;
0765 #else
0766         uint64_t qen:8;
0767         uint64_t reserved_8_63:56;
0768 #endif
0769     } s;
0770 };
0771 
0772 union cvmx_dpi_sli_prtx_cfg {
0773     uint64_t u64;
0774     struct cvmx_dpi_sli_prtx_cfg_s {
0775 #ifdef __BIG_ENDIAN_BITFIELD
0776         uint64_t reserved_25_63:39;
0777         uint64_t halt:1;
0778         uint64_t qlm_cfg:4;
0779         uint64_t reserved_17_19:3;
0780         uint64_t rd_mode:1;
0781         uint64_t reserved_14_15:2;
0782         uint64_t molr:6;
0783         uint64_t mps_lim:1;
0784         uint64_t reserved_5_6:2;
0785         uint64_t mps:1;
0786         uint64_t mrrs_lim:1;
0787         uint64_t reserved_2_2:1;
0788         uint64_t mrrs:2;
0789 #else
0790         uint64_t mrrs:2;
0791         uint64_t reserved_2_2:1;
0792         uint64_t mrrs_lim:1;
0793         uint64_t mps:1;
0794         uint64_t reserved_5_6:2;
0795         uint64_t mps_lim:1;
0796         uint64_t molr:6;
0797         uint64_t reserved_14_15:2;
0798         uint64_t rd_mode:1;
0799         uint64_t reserved_17_19:3;
0800         uint64_t qlm_cfg:4;
0801         uint64_t halt:1;
0802         uint64_t reserved_25_63:39;
0803 #endif
0804     } s;
0805     struct cvmx_dpi_sli_prtx_cfg_cn63xx {
0806 #ifdef __BIG_ENDIAN_BITFIELD
0807         uint64_t reserved_25_63:39;
0808         uint64_t halt:1;
0809         uint64_t reserved_21_23:3;
0810         uint64_t qlm_cfg:1;
0811         uint64_t reserved_17_19:3;
0812         uint64_t rd_mode:1;
0813         uint64_t reserved_14_15:2;
0814         uint64_t molr:6;
0815         uint64_t mps_lim:1;
0816         uint64_t reserved_5_6:2;
0817         uint64_t mps:1;
0818         uint64_t mrrs_lim:1;
0819         uint64_t reserved_2_2:1;
0820         uint64_t mrrs:2;
0821 #else
0822         uint64_t mrrs:2;
0823         uint64_t reserved_2_2:1;
0824         uint64_t mrrs_lim:1;
0825         uint64_t mps:1;
0826         uint64_t reserved_5_6:2;
0827         uint64_t mps_lim:1;
0828         uint64_t molr:6;
0829         uint64_t reserved_14_15:2;
0830         uint64_t rd_mode:1;
0831         uint64_t reserved_17_19:3;
0832         uint64_t qlm_cfg:1;
0833         uint64_t reserved_21_23:3;
0834         uint64_t halt:1;
0835         uint64_t reserved_25_63:39;
0836 #endif
0837     } cn63xx;
0838 };
0839 
0840 union cvmx_dpi_sli_prtx_err {
0841     uint64_t u64;
0842     struct cvmx_dpi_sli_prtx_err_s {
0843 #ifdef __BIG_ENDIAN_BITFIELD
0844         uint64_t addr:61;
0845         uint64_t reserved_0_2:3;
0846 #else
0847         uint64_t reserved_0_2:3;
0848         uint64_t addr:61;
0849 #endif
0850     } s;
0851 };
0852 
0853 union cvmx_dpi_sli_prtx_err_info {
0854     uint64_t u64;
0855     struct cvmx_dpi_sli_prtx_err_info_s {
0856 #ifdef __BIG_ENDIAN_BITFIELD
0857         uint64_t reserved_9_63:55;
0858         uint64_t lock:1;
0859         uint64_t reserved_5_7:3;
0860         uint64_t type:1;
0861         uint64_t reserved_3_3:1;
0862         uint64_t reqq:3;
0863 #else
0864         uint64_t reqq:3;
0865         uint64_t reserved_3_3:1;
0866         uint64_t type:1;
0867         uint64_t reserved_5_7:3;
0868         uint64_t lock:1;
0869         uint64_t reserved_9_63:55;
0870 #endif
0871     } s;
0872 };
0873 
0874 #endif
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