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0028 #ifndef __CVMX_DBG_DEFS_H__
0029 #define __CVMX_DBG_DEFS_H__
0030
0031 #define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
0032
0033 union cvmx_dbg_data {
0034 uint64_t u64;
0035 struct cvmx_dbg_data_s {
0036 #ifdef __BIG_ENDIAN_BITFIELD
0037 uint64_t reserved_23_63:41;
0038 uint64_t c_mul:5;
0039 uint64_t dsel_ext:1;
0040 uint64_t data:17;
0041 #else
0042 uint64_t data:17;
0043 uint64_t dsel_ext:1;
0044 uint64_t c_mul:5;
0045 uint64_t reserved_23_63:41;
0046 #endif
0047 } s;
0048 struct cvmx_dbg_data_cn30xx {
0049 #ifdef __BIG_ENDIAN_BITFIELD
0050 uint64_t reserved_31_63:33;
0051 uint64_t pll_mul:3;
0052 uint64_t reserved_23_27:5;
0053 uint64_t c_mul:5;
0054 uint64_t dsel_ext:1;
0055 uint64_t data:17;
0056 #else
0057 uint64_t data:17;
0058 uint64_t dsel_ext:1;
0059 uint64_t c_mul:5;
0060 uint64_t reserved_23_27:5;
0061 uint64_t pll_mul:3;
0062 uint64_t reserved_31_63:33;
0063 #endif
0064 } cn30xx;
0065 struct cvmx_dbg_data_cn38xx {
0066 #ifdef __BIG_ENDIAN_BITFIELD
0067 uint64_t reserved_29_63:35;
0068 uint64_t d_mul:4;
0069 uint64_t dclk_mul2:1;
0070 uint64_t cclk_div2:1;
0071 uint64_t c_mul:5;
0072 uint64_t dsel_ext:1;
0073 uint64_t data:17;
0074 #else
0075 uint64_t data:17;
0076 uint64_t dsel_ext:1;
0077 uint64_t c_mul:5;
0078 uint64_t cclk_div2:1;
0079 uint64_t dclk_mul2:1;
0080 uint64_t d_mul:4;
0081 uint64_t reserved_29_63:35;
0082 #endif
0083 } cn38xx;
0084 struct cvmx_dbg_data_cn58xx {
0085 #ifdef __BIG_ENDIAN_BITFIELD
0086 uint64_t reserved_29_63:35;
0087 uint64_t rem:6;
0088 uint64_t c_mul:5;
0089 uint64_t dsel_ext:1;
0090 uint64_t data:17;
0091 #else
0092 uint64_t data:17;
0093 uint64_t dsel_ext:1;
0094 uint64_t c_mul:5;
0095 uint64_t rem:6;
0096 uint64_t reserved_29_63:35;
0097 #endif
0098 } cn58xx;
0099 };
0100
0101 #endif