asm/octeon/cvmx-config.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __CVMX_CONFIG_H__
0003 #define __CVMX_CONFIG_H__
0004
0005 /************************* Config Specific Defines ************************/
0006 #define CVMX_LLM_NUM_PORTS 1
0007 #define CVMX_NULL_POINTER_PROTECT 1
0008 #define CVMX_ENABLE_DEBUG_PRINTS 1
0009 /* PKO queues per port for interface 0 (ports 0-15) */
0010 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
0011 /* PKO queues per port for interface 1 (ports 16-31) */
0012 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
0013 /* Limit on the number of PKO ports enabled for interface 0 */
0014 #define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
0015 /* Limit on the number of PKO ports enabled for interface 1 */
0016 #define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
0017 /* PKO queues per port for PCI (ports 32-35) */
0018 #define CVMX_PKO_QUEUES_PER_PORT_PCI 1
0019 /* PKO queues per port for Loop devices (ports 36-39) */
0020 #define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
0021
0022 /************************* FPA allocation *********************************/
0023 /* Pool sizes in bytes, must be multiple of a cache line */
0024 #define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
0025 #define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
0026 #define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
0027 #define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
0028 #define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
0029 #define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
0030 #define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
0031 #define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
0032
0033 /* Pools in use */
0034 /* Packet buffers */
0035 #define CVMX_FPA_PACKET_POOL            (0)
0036 #define CVMX_FPA_PACKET_POOL_SIZE       CVMX_FPA_POOL_0_SIZE
0037 /* Work queue entries */
0038 #define CVMX_FPA_WQE_POOL           (1)
0039 #define CVMX_FPA_WQE_POOL_SIZE          CVMX_FPA_POOL_1_SIZE
0040 /* PKO queue command buffers */
0041 #define CVMX_FPA_OUTPUT_BUFFER_POOL     (2)
0042 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
0043
0044 /*************************  FAU allocation ********************************/
0045 /* The fetch and add registers are allocated here.  They are arranged
0046  * in order of descending size so that all alignment constraints are
0047  * automatically met.  The enums are linked so that the following enum
0048  * continues allocating where the previous one left off, so the
0049  * numbering within each enum always starts with zero.  The macros
0050  * take care of the address increment size, so the values entered
0051  * always increase by 1.  FAU registers are accessed with byte
0052  * addresses.
0053  */
0054
0055 #define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
0056 typedef enum {
0057     CVMX_FAU_REG_64_START   = 0,
0058     CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0),
0059 } cvmx_fau_reg_64_t;
0060
0061 #define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
0062 typedef enum {
0063     CVMX_FAU_REG_32_START   = CVMX_FAU_REG_64_END,
0064     CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
0065 } cvmx_fau_reg_32_t;
0066
0067 #define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
0068 typedef enum {
0069     CVMX_FAU_REG_16_START   = CVMX_FAU_REG_32_END,
0070     CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
0071 } cvmx_fau_reg_16_t;
0072
0073 #define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
0074 typedef enum {
0075     CVMX_FAU_REG_8_START    = CVMX_FAU_REG_16_END,
0076     CVMX_FAU_REG_8_END  = CVMX_FAU_REG_8_ADDR(0),
0077 } cvmx_fau_reg_8_t;
0078
0079 /*
0080  * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
0081  * available FAU address that is not allocated in cvmx-config.h. This
0082  * is 64 bit aligned.
0083  */
0084 #define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
0085 #define CVMX_FAU_REG_END (2048)
0086
0087 /********************** scratch memory allocation *************************/
0088 /* Scratchpad memory allocation.  Note that these are byte memory
0089  * addresses.  Some uses of scratchpad (IOBDMA for example) require
0090  * the use of 8-byte aligned addresses, so proper alignment needs to
0091  * be taken into account.
0092  */
0093 /* Generic scratch iobdma area */
0094 #define CVMX_SCR_SCRATCH           (0)
0095 /* First location available after cvmx-config.h allocated region. */
0096 #define CVMX_SCR_REG_AVAIL_BASE        (8)
0097
0098 /*
0099  * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
0100  * before the beginning of the packet. If necessary, override the
0101  * default here.  See the IPD section of the hardware manual for MBUFF
0102  * SKIP details.
0103  */
0104 #define CVMX_HELPER_FIRST_MBUFF_SKIP 184
0105
0106 /*
0107  * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
0108  * in each chained packet element. If necessary, override the default
0109  * here.
0110  */
0111 #define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
0112
0113 /*
0114  * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
0115  * enabled for all input ports. This controls if IPD sends
0116  * backpressure to all ports if Octeon's FPA pools don't have enough
0117  * packet or work queue entries. Even when this is off, it is still
0118  * possible to get backpressure from individual hardware ports. When
0119  * configuring backpressure, also check
0120  * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
0121  * the default here.
0122  */
0123 #define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
0124
0125 /*
0126  * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
0127  * function. Once it is enabled the hardware starts accepting
0128  * packets. You might want to skip the IPD enable if configuration
0129  * changes are need from the default helper setup. If necessary,
0130  * override the default here.
0131  */
0132 #define CVMX_HELPER_ENABLE_IPD 0
0133
0134 /*
0135  * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
0136  * to incoming packets.
0137  */
0138 #define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
0139
0140 #define CVMX_ENABLE_PARAMETER_CHECKING 0
0141
0142 /*
0143  * The following select which fields are used by the PIP to generate
0144  * the tag on INPUT
0145  * 0: don't include
0146  * 1: include
0147  */
0148 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP   0
0149 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP   0
0150 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
0151 #define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
0152 #define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER  0
0153 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP   0
0154 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP   0
0155 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
0156 #define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
0157 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
0158 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT    1
0159
0160 /* Select skip mode for input ports */
0161 #define CVMX_HELPER_INPUT_PORT_SKIP_MODE    CVMX_PIP_PORT_CFG_MODE_SKIPL2
0162
0163 /*
0164  * Force backpressure to be disabled.  This overrides all other
0165  * backpressure configuration.
0166  */
0167 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
0168
0169 #endif /* __CVMX_CONFIG_H__ */