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0016 #ifndef __CVMX_CIU3_DEFS_H__
0017 #define __CVMX_CIU3_DEFS_H__
0018
0019 #define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull)
0020 #define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull)
0021 #define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull)
0022 #define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull)
0023 #define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8)
0024 #define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8)
0025 #define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull)
0026 #define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8)
0027 #define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8)
0028 #define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull)
0029 #define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull)
0030 #define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull)
0031 #define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull)
0032 #define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull)
0033 #define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8)
0034 #define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8)
0035 #define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8)
0036 #define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull)
0037 #define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8)
0038 #define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8)
0039
0040 union cvmx_ciu3_bist {
0041 uint64_t u64;
0042 struct cvmx_ciu3_bist_s {
0043 #ifdef __BIG_ENDIAN_BITFIELD
0044 uint64_t reserved_9_63 : 55;
0045 uint64_t bist : 9;
0046 #else
0047 uint64_t bist : 9;
0048 uint64_t reserved_9_63 : 55;
0049 #endif
0050 } s;
0051 };
0052
0053 union cvmx_ciu3_const {
0054 uint64_t u64;
0055 struct cvmx_ciu3_const_s {
0056 #ifdef __BIG_ENDIAN_BITFIELD
0057 uint64_t dests_io : 16;
0058 uint64_t pintsn : 16;
0059 uint64_t dests_pp : 16;
0060 uint64_t idt : 16;
0061 #else
0062 uint64_t idt : 16;
0063 uint64_t dests_pp : 16;
0064 uint64_t pintsn : 16;
0065 uint64_t dests_io : 16;
0066 #endif
0067 } s;
0068 };
0069
0070 union cvmx_ciu3_ctl {
0071 uint64_t u64;
0072 struct cvmx_ciu3_ctl_s {
0073 #ifdef __BIG_ENDIAN_BITFIELD
0074 uint64_t reserved_5_63 : 59;
0075 uint64_t mcd_sel : 2;
0076 uint64_t iscmem_le : 1;
0077 uint64_t seq_dis : 1;
0078 uint64_t cclk_dis : 1;
0079 #else
0080 uint64_t cclk_dis : 1;
0081 uint64_t seq_dis : 1;
0082 uint64_t iscmem_le : 1;
0083 uint64_t mcd_sel : 2;
0084 uint64_t reserved_5_63 : 59;
0085 #endif
0086 } s;
0087 };
0088
0089 union cvmx_ciu3_destx_io_int {
0090 uint64_t u64;
0091 struct cvmx_ciu3_destx_io_int_s {
0092 #ifdef __BIG_ENDIAN_BITFIELD
0093 uint64_t reserved_52_63 : 12;
0094 uint64_t intsn : 20;
0095 uint64_t reserved_10_31 : 22;
0096 uint64_t intidt : 8;
0097 uint64_t newint : 1;
0098 uint64_t intr : 1;
0099 #else
0100 uint64_t intr : 1;
0101 uint64_t newint : 1;
0102 uint64_t intidt : 8;
0103 uint64_t reserved_10_31 : 22;
0104 uint64_t intsn : 20;
0105 uint64_t reserved_52_63 : 12;
0106 #endif
0107 } s;
0108 };
0109
0110 union cvmx_ciu3_destx_pp_int {
0111 uint64_t u64;
0112 struct cvmx_ciu3_destx_pp_int_s {
0113 #ifdef __BIG_ENDIAN_BITFIELD
0114 uint64_t reserved_52_63 : 12;
0115 uint64_t intsn : 20;
0116 uint64_t reserved_10_31 : 22;
0117 uint64_t intidt : 8;
0118 uint64_t newint : 1;
0119 uint64_t intr : 1;
0120 #else
0121 uint64_t intr : 1;
0122 uint64_t newint : 1;
0123 uint64_t intidt : 8;
0124 uint64_t reserved_10_31 : 22;
0125 uint64_t intsn : 20;
0126 uint64_t reserved_52_63 : 12;
0127 #endif
0128 } s;
0129 };
0130
0131 union cvmx_ciu3_gstop {
0132 uint64_t u64;
0133 struct cvmx_ciu3_gstop_s {
0134 #ifdef __BIG_ENDIAN_BITFIELD
0135 uint64_t reserved_1_63 : 63;
0136 uint64_t gstop : 1;
0137 #else
0138 uint64_t gstop : 1;
0139 uint64_t reserved_1_63 : 63;
0140 #endif
0141 } s;
0142 };
0143
0144 union cvmx_ciu3_idtx_ctl {
0145 uint64_t u64;
0146 struct cvmx_ciu3_idtx_ctl_s {
0147 #ifdef __BIG_ENDIAN_BITFIELD
0148 uint64_t reserved_52_63 : 12;
0149 uint64_t intsn : 20;
0150 uint64_t reserved_4_31 : 28;
0151 uint64_t intr : 1;
0152 uint64_t newint : 1;
0153 uint64_t ip_num : 2;
0154 #else
0155 uint64_t ip_num : 2;
0156 uint64_t newint : 1;
0157 uint64_t intr : 1;
0158 uint64_t reserved_4_31 : 28;
0159 uint64_t intsn : 20;
0160 uint64_t reserved_52_63 : 12;
0161 #endif
0162 } s;
0163 };
0164
0165 union cvmx_ciu3_idtx_io {
0166 uint64_t u64;
0167 struct cvmx_ciu3_idtx_io_s {
0168 #ifdef __BIG_ENDIAN_BITFIELD
0169 uint64_t reserved_5_63 : 59;
0170 uint64_t io : 5;
0171 #else
0172 uint64_t io : 5;
0173 uint64_t reserved_5_63 : 59;
0174 #endif
0175 } s;
0176 };
0177
0178 union cvmx_ciu3_idtx_ppx {
0179 uint64_t u64;
0180 struct cvmx_ciu3_idtx_ppx_s {
0181 #ifdef __BIG_ENDIAN_BITFIELD
0182 uint64_t reserved_48_63 : 16;
0183 uint64_t pp : 48;
0184 #else
0185 uint64_t pp : 48;
0186 uint64_t reserved_48_63 : 16;
0187 #endif
0188 } s;
0189 };
0190
0191 union cvmx_ciu3_intr_ram_ecc_ctl {
0192 uint64_t u64;
0193 struct cvmx_ciu3_intr_ram_ecc_ctl_s {
0194 #ifdef __BIG_ENDIAN_BITFIELD
0195 uint64_t reserved_3_63 : 61;
0196 uint64_t flip_synd : 2;
0197 uint64_t ecc_ena : 1;
0198 #else
0199 uint64_t ecc_ena : 1;
0200 uint64_t flip_synd : 2;
0201 uint64_t reserved_3_63 : 61;
0202 #endif
0203 } s;
0204 };
0205
0206 union cvmx_ciu3_intr_ram_ecc_st {
0207 uint64_t u64;
0208 struct cvmx_ciu3_intr_ram_ecc_st_s {
0209 #ifdef __BIG_ENDIAN_BITFIELD
0210 uint64_t reserved_52_63 : 12;
0211 uint64_t addr : 20;
0212 uint64_t reserved_6_31 : 26;
0213 uint64_t sisc_dbe : 1;
0214 uint64_t sisc_sbe : 1;
0215 uint64_t idt_dbe : 1;
0216 uint64_t idt_sbe : 1;
0217 uint64_t isc_dbe : 1;
0218 uint64_t isc_sbe : 1;
0219 #else
0220 uint64_t isc_sbe : 1;
0221 uint64_t isc_dbe : 1;
0222 uint64_t idt_sbe : 1;
0223 uint64_t idt_dbe : 1;
0224 uint64_t sisc_sbe : 1;
0225 uint64_t sisc_dbe : 1;
0226 uint64_t reserved_6_31 : 26;
0227 uint64_t addr : 20;
0228 uint64_t reserved_52_63 : 12;
0229 #endif
0230 } s;
0231 };
0232
0233 union cvmx_ciu3_intr_ready {
0234 uint64_t u64;
0235 struct cvmx_ciu3_intr_ready_s {
0236 #ifdef __BIG_ENDIAN_BITFIELD
0237 uint64_t reserved_46_63 : 18;
0238 uint64_t index : 14;
0239 uint64_t reserved_1_31 : 31;
0240 uint64_t ready : 1;
0241 #else
0242 uint64_t ready : 1;
0243 uint64_t reserved_1_31 : 31;
0244 uint64_t index : 14;
0245 uint64_t reserved_46_63 : 18;
0246 #endif
0247 } s;
0248 };
0249
0250 union cvmx_ciu3_intr_slowdown {
0251 uint64_t u64;
0252 struct cvmx_ciu3_intr_slowdown_s {
0253 #ifdef __BIG_ENDIAN_BITFIELD
0254 uint64_t reserved_3_63 : 61;
0255 uint64_t ctl : 3;
0256 #else
0257 uint64_t ctl : 3;
0258 uint64_t reserved_3_63 : 61;
0259 #endif
0260 } s;
0261 };
0262
0263 union cvmx_ciu3_iscx_ctl {
0264 uint64_t u64;
0265 struct cvmx_ciu3_iscx_ctl_s {
0266 #ifdef __BIG_ENDIAN_BITFIELD
0267 uint64_t reserved_24_63 : 40;
0268 uint64_t idt : 8;
0269 uint64_t imp : 1;
0270 uint64_t reserved_2_14 : 13;
0271 uint64_t en : 1;
0272 uint64_t raw : 1;
0273 #else
0274 uint64_t raw : 1;
0275 uint64_t en : 1;
0276 uint64_t reserved_2_14 : 13;
0277 uint64_t imp : 1;
0278 uint64_t idt : 8;
0279 uint64_t reserved_24_63 : 40;
0280 #endif
0281 } s;
0282 };
0283
0284 union cvmx_ciu3_iscx_w1c {
0285 uint64_t u64;
0286 struct cvmx_ciu3_iscx_w1c_s {
0287 #ifdef __BIG_ENDIAN_BITFIELD
0288 uint64_t reserved_2_63 : 62;
0289 uint64_t en : 1;
0290 uint64_t raw : 1;
0291 #else
0292 uint64_t raw : 1;
0293 uint64_t en : 1;
0294 uint64_t reserved_2_63 : 62;
0295 #endif
0296 } s;
0297 };
0298
0299 union cvmx_ciu3_iscx_w1s {
0300 uint64_t u64;
0301 struct cvmx_ciu3_iscx_w1s_s {
0302 #ifdef __BIG_ENDIAN_BITFIELD
0303 uint64_t reserved_2_63 : 62;
0304 uint64_t en : 1;
0305 uint64_t raw : 1;
0306 #else
0307 uint64_t raw : 1;
0308 uint64_t en : 1;
0309 uint64_t reserved_2_63 : 62;
0310 #endif
0311 } s;
0312 };
0313
0314 union cvmx_ciu3_nmi {
0315 uint64_t u64;
0316 struct cvmx_ciu3_nmi_s {
0317 #ifdef __BIG_ENDIAN_BITFIELD
0318 uint64_t reserved_48_63 : 16;
0319 uint64_t nmi : 48;
0320 #else
0321 uint64_t nmi : 48;
0322 uint64_t reserved_48_63 : 16;
0323 #endif
0324 } s;
0325 };
0326
0327 union cvmx_ciu3_siscx {
0328 uint64_t u64;
0329 struct cvmx_ciu3_siscx_s {
0330 #ifdef __BIG_ENDIAN_BITFIELD
0331 uint64_t en : 64;
0332 #else
0333 uint64_t en : 64;
0334 #endif
0335 } s;
0336 };
0337
0338 union cvmx_ciu3_timx {
0339 uint64_t u64;
0340 struct cvmx_ciu3_timx_s {
0341 #ifdef __BIG_ENDIAN_BITFIELD
0342 uint64_t reserved_37_63 : 27;
0343 uint64_t one_shot : 1;
0344 uint64_t len : 36;
0345 #else
0346 uint64_t len : 36;
0347 uint64_t one_shot : 1;
0348 uint64_t reserved_37_63 : 27;
0349 #endif
0350 } s;
0351 };
0352
0353 #endif
