asm/octeon/cvmx-ciu-defs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Octeon CIU definitions
0003  *
0004  * Copyright (C) 2003-2018 Cavium, Inc.
0005  */
0006
0007 #ifndef __CVMX_CIU_DEFS_H__
0008 #define __CVMX_CIU_DEFS_H__
0009
0010 #include <asm/bitfield.h>
0011
0012 #define CVMX_CIU_ADDR(addr, coreid, coremask, offset)                  \
0013     (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) +              \
0014     (((coreid) & (coremask)) * offset))
0015
0016 #define CVMX_CIU_EN2_PPX_IP4(c)     CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
0017 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
0018 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
0019 #define CVMX_CIU_FUSE           CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
0020 #define CVMX_CIU_INT_SUM1       CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
0021 #define CVMX_CIU_INTX_EN0(c)        CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
0022 #define CVMX_CIU_INTX_EN0_W1C(c)    CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
0023 #define CVMX_CIU_INTX_EN0_W1S(c)    CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
0024 #define CVMX_CIU_INTX_EN1(c)        CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
0025 #define CVMX_CIU_INTX_EN1_W1C(c)    CVMX_CIU_ADDR(0x2208, c, 0x3F, 16)
0026 #define CVMX_CIU_INTX_EN1_W1S(c)    CVMX_CIU_ADDR(0x6208, c, 0x3F, 16)
0027 #define CVMX_CIU_INTX_SUM0(c)       CVMX_CIU_ADDR(0x0000, c, 0x3F, 8)
0028 #define CVMX_CIU_NMI            CVMX_CIU_ADDR(0x0718, 0, 0x00, 0)
0029 #define CVMX_CIU_PCI_INTA       CVMX_CIU_ADDR(0x0750, 0, 0x00, 0)
0030 #define CVMX_CIU_PP_BIST_STAT       CVMX_CIU_ADDR(0x07E0, 0, 0x00, 0)
0031 #define CVMX_CIU_PP_DBG         CVMX_CIU_ADDR(0x0708, 0, 0x00, 0)
0032 #define CVMX_CIU_PP_RST         CVMX_CIU_ADDR(0x0700, 0, 0x00, 0)
0033 #define CVMX_CIU_QLM0           CVMX_CIU_ADDR(0x0780, 0, 0x00, 0)
0034 #define CVMX_CIU_QLM1           CVMX_CIU_ADDR(0x0788, 0, 0x00, 0)
0035 #define CVMX_CIU_QLM_JTGC       CVMX_CIU_ADDR(0x0768, 0, 0x00, 0)
0036 #define CVMX_CIU_QLM_JTGD       CVMX_CIU_ADDR(0x0770, 0, 0x00, 0)
0037 #define CVMX_CIU_SOFT_BIST      CVMX_CIU_ADDR(0x0738, 0, 0x00, 0)
0038 #define CVMX_CIU_SOFT_PRST1     CVMX_CIU_ADDR(0x0758, 0, 0x00, 0)
0039 #define CVMX_CIU_SOFT_PRST      CVMX_CIU_ADDR(0x0748, 0, 0x00, 0)
0040 #define CVMX_CIU_SOFT_RST       CVMX_CIU_ADDR(0x0740, 0, 0x00, 0)
0041 #define CVMX_CIU_SUM2_PPX_IP4(c)    CVMX_CIU_ADDR(0x8C00, c, 0x0F, 8)
0042 #define CVMX_CIU_TIM_MULTI_CAST     CVMX_CIU_ADDR(0xC200, 0, 0x00, 0)
0043 #define CVMX_CIU_TIMX(c)        CVMX_CIU_ADDR(0x0480, c, 0x0F, 8)
0044
0045 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned int coreid)
0046 {
0047     if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
0048         return CVMX_CIU_ADDR(0x100100600, coreid, 0x0F, 8);
0049     else
0050         return CVMX_CIU_ADDR(0x000000680, coreid, 0x0F, 8);
0051 }
0052
0053 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned int coreid)
0054 {
0055     if (cvmx_get_octeon_family() == (OCTEON_CN68XX & OCTEON_FAMILY_MASK))
0056         return CVMX_CIU_ADDR(0x100100400, coreid, 0x0F, 8);
0057     else
0058         return CVMX_CIU_ADDR(0x000000600, coreid, 0x0F, 8);
0059 }
0060
0061 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned int coreid)
0062 {
0063     switch (cvmx_get_octeon_family()) {
0064     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0065         return CVMX_CIU_ADDR(0x100100200, coreid, 0x0F, 8);
0066     case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
0067     case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
0068     case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
0069         return CVMX_CIU_ADDR(0x000030000, coreid, 0x0F, 8) -
0070             0x60000000000ull;
0071     default:
0072         return CVMX_CIU_ADDR(0x000000580, coreid, 0x0F, 8);
0073     }
0074 }
0075
0076 static inline uint64_t CVMX_CIU_WDOGX(unsigned int coreid)
0077 {
0078     switch (cvmx_get_octeon_family()) {
0079     case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
0080         return CVMX_CIU_ADDR(0x100100000, coreid, 0x0F, 8);
0081     case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
0082     case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
0083     case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
0084         return CVMX_CIU_ADDR(0x000020000, coreid, 0x0F, 8) -
0085             0x60000000000ull;
0086     default:
0087         return CVMX_CIU_ADDR(0x000000500, coreid, 0x0F, 8);
0088     }
0089 }
0090
0091
0092 union cvmx_ciu_qlm {
0093     uint64_t u64;
0094     struct cvmx_ciu_qlm_s {
0095         __BITFIELD_FIELD(uint64_t g2bypass:1,
0096         __BITFIELD_FIELD(uint64_t reserved_53_62:10,
0097         __BITFIELD_FIELD(uint64_t g2deemph:5,
0098         __BITFIELD_FIELD(uint64_t reserved_45_47:3,
0099         __BITFIELD_FIELD(uint64_t g2margin:5,
0100         __BITFIELD_FIELD(uint64_t reserved_32_39:8,
0101         __BITFIELD_FIELD(uint64_t txbypass:1,
0102         __BITFIELD_FIELD(uint64_t reserved_21_30:10,
0103         __BITFIELD_FIELD(uint64_t txdeemph:5,
0104         __BITFIELD_FIELD(uint64_t reserved_13_15:3,
0105         __BITFIELD_FIELD(uint64_t txmargin:5,
0106         __BITFIELD_FIELD(uint64_t reserved_4_7:4,
0107         __BITFIELD_FIELD(uint64_t lane_en:4,
0108         ;)))))))))))))
0109     } s;
0110 };
0111
0112 union cvmx_ciu_qlm_jtgc {
0113     uint64_t u64;
0114     struct cvmx_ciu_qlm_jtgc_s {
0115         __BITFIELD_FIELD(uint64_t reserved_17_63:47,
0116         __BITFIELD_FIELD(uint64_t bypass_ext:1,
0117         __BITFIELD_FIELD(uint64_t reserved_11_15:5,
0118         __BITFIELD_FIELD(uint64_t clk_div:3,
0119         __BITFIELD_FIELD(uint64_t reserved_7_7:1,
0120         __BITFIELD_FIELD(uint64_t mux_sel:3,
0121         __BITFIELD_FIELD(uint64_t bypass:4,
0122         ;)))))))
0123     } s;
0124 };
0125
0126 union cvmx_ciu_qlm_jtgd {
0127     uint64_t u64;
0128     struct cvmx_ciu_qlm_jtgd_s {
0129         __BITFIELD_FIELD(uint64_t capture:1,
0130         __BITFIELD_FIELD(uint64_t shift:1,
0131         __BITFIELD_FIELD(uint64_t update:1,
0132         __BITFIELD_FIELD(uint64_t reserved_45_60:16,
0133         __BITFIELD_FIELD(uint64_t select:5,
0134         __BITFIELD_FIELD(uint64_t reserved_37_39:3,
0135         __BITFIELD_FIELD(uint64_t shft_cnt:5,
0136         __BITFIELD_FIELD(uint64_t shft_reg:32,
0137         ;))))))))
0138     } s;
0139 };
0140
0141 union cvmx_ciu_soft_prst {
0142     uint64_t u64;
0143     struct cvmx_ciu_soft_prst_s {
0144         __BITFIELD_FIELD(uint64_t reserved_3_63:61,
0145         __BITFIELD_FIELD(uint64_t host64:1,
0146         __BITFIELD_FIELD(uint64_t npi:1,
0147         __BITFIELD_FIELD(uint64_t soft_prst:1,
0148         ;))))
0149     } s;
0150 };
0151
0152 union cvmx_ciu_timx {
0153     uint64_t u64;
0154     struct cvmx_ciu_timx_s {
0155         __BITFIELD_FIELD(uint64_t reserved_37_63:27,
0156         __BITFIELD_FIELD(uint64_t one_shot:1,
0157         __BITFIELD_FIELD(uint64_t len:36,
0158         ;)))
0159     } s;
0160 };
0161
0162 union cvmx_ciu_wdogx {
0163     uint64_t u64;
0164     struct cvmx_ciu_wdogx_s {
0165         __BITFIELD_FIELD(uint64_t reserved_46_63:18,
0166         __BITFIELD_FIELD(uint64_t gstopen:1,
0167         __BITFIELD_FIELD(uint64_t dstop:1,
0168         __BITFIELD_FIELD(uint64_t cnt:24,
0169         __BITFIELD_FIELD(uint64_t len:16,
0170         __BITFIELD_FIELD(uint64_t state:2,
0171         __BITFIELD_FIELD(uint64_t mode:2,
0172         ;)))))))
0173     } s;
0174 };
0175
0176 #endif /* __CVMX_CIU_DEFS_H__ */