asm/octeon/cvmx-asxx-defs.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (C) 2003-2018 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 #ifndef __CVMX_ASXX_DEFS_H__
0029 #define __CVMX_ASXX_DEFS_H__
0030
0031 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
0032 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
0033 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
0034 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
0035 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
0036 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
0037 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
0038 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
0039 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
0040 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
0041 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
0042 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
0043 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
0044 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
0045 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
0046 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
0047 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
0048 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
0049 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
0050 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
0051 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
0052 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
0053 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
0054 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
0055 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
0056 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
0057
0058 void __cvmx_interrupt_asxx_enable(int block);
0059
0060 union cvmx_asxx_gmii_rx_clk_set {
0061     uint64_t u64;
0062     struct cvmx_asxx_gmii_rx_clk_set_s {
0063 #ifdef __BIG_ENDIAN_BITFIELD
0064         uint64_t reserved_5_63:59;
0065         uint64_t setting:5;
0066 #else
0067         uint64_t setting:5;
0068         uint64_t reserved_5_63:59;
0069 #endif
0070     } s;
0071 };
0072
0073 union cvmx_asxx_gmii_rx_dat_set {
0074     uint64_t u64;
0075     struct cvmx_asxx_gmii_rx_dat_set_s {
0076 #ifdef __BIG_ENDIAN_BITFIELD
0077         uint64_t reserved_5_63:59;
0078         uint64_t setting:5;
0079 #else
0080         uint64_t setting:5;
0081         uint64_t reserved_5_63:59;
0082 #endif
0083     } s;
0084 };
0085
0086 union cvmx_asxx_int_en {
0087     uint64_t u64;
0088     struct cvmx_asxx_int_en_s {
0089 #ifdef __BIG_ENDIAN_BITFIELD
0090         uint64_t reserved_12_63:52;
0091         uint64_t txpsh:4;
0092         uint64_t txpop:4;
0093         uint64_t ovrflw:4;
0094 #else
0095         uint64_t ovrflw:4;
0096         uint64_t txpop:4;
0097         uint64_t txpsh:4;
0098         uint64_t reserved_12_63:52;
0099 #endif
0100     } s;
0101     struct cvmx_asxx_int_en_cn30xx {
0102 #ifdef __BIG_ENDIAN_BITFIELD
0103         uint64_t reserved_11_63:53;
0104         uint64_t txpsh:3;
0105         uint64_t reserved_7_7:1;
0106         uint64_t txpop:3;
0107         uint64_t reserved_3_3:1;
0108         uint64_t ovrflw:3;
0109 #else
0110         uint64_t ovrflw:3;
0111         uint64_t reserved_3_3:1;
0112         uint64_t txpop:3;
0113         uint64_t reserved_7_7:1;
0114         uint64_t txpsh:3;
0115         uint64_t reserved_11_63:53;
0116 #endif
0117     } cn30xx;
0118 };
0119
0120 union cvmx_asxx_int_reg {
0121     uint64_t u64;
0122     struct cvmx_asxx_int_reg_s {
0123 #ifdef __BIG_ENDIAN_BITFIELD
0124         uint64_t reserved_12_63:52;
0125         uint64_t txpsh:4;
0126         uint64_t txpop:4;
0127         uint64_t ovrflw:4;
0128 #else
0129         uint64_t ovrflw:4;
0130         uint64_t txpop:4;
0131         uint64_t txpsh:4;
0132         uint64_t reserved_12_63:52;
0133 #endif
0134     } s;
0135     struct cvmx_asxx_int_reg_cn30xx {
0136 #ifdef __BIG_ENDIAN_BITFIELD
0137         uint64_t reserved_11_63:53;
0138         uint64_t txpsh:3;
0139         uint64_t reserved_7_7:1;
0140         uint64_t txpop:3;
0141         uint64_t reserved_3_3:1;
0142         uint64_t ovrflw:3;
0143 #else
0144         uint64_t ovrflw:3;
0145         uint64_t reserved_3_3:1;
0146         uint64_t txpop:3;
0147         uint64_t reserved_7_7:1;
0148         uint64_t txpsh:3;
0149         uint64_t reserved_11_63:53;
0150 #endif
0151     } cn30xx;
0152 };
0153
0154 union cvmx_asxx_mii_rx_dat_set {
0155     uint64_t u64;
0156     struct cvmx_asxx_mii_rx_dat_set_s {
0157 #ifdef __BIG_ENDIAN_BITFIELD
0158         uint64_t reserved_5_63:59;
0159         uint64_t setting:5;
0160 #else
0161         uint64_t setting:5;
0162         uint64_t reserved_5_63:59;
0163 #endif
0164     } s;
0165 };
0166
0167 union cvmx_asxx_prt_loop {
0168     uint64_t u64;
0169     struct cvmx_asxx_prt_loop_s {
0170 #ifdef __BIG_ENDIAN_BITFIELD
0171         uint64_t reserved_8_63:56;
0172         uint64_t ext_loop:4;
0173         uint64_t int_loop:4;
0174 #else
0175         uint64_t int_loop:4;
0176         uint64_t ext_loop:4;
0177         uint64_t reserved_8_63:56;
0178 #endif
0179     } s;
0180     struct cvmx_asxx_prt_loop_cn30xx {
0181 #ifdef __BIG_ENDIAN_BITFIELD
0182         uint64_t reserved_7_63:57;
0183         uint64_t ext_loop:3;
0184         uint64_t reserved_3_3:1;
0185         uint64_t int_loop:3;
0186 #else
0187         uint64_t int_loop:3;
0188         uint64_t reserved_3_3:1;
0189         uint64_t ext_loop:3;
0190         uint64_t reserved_7_63:57;
0191 #endif
0192     } cn30xx;
0193 };
0194
0195 union cvmx_asxx_rld_bypass {
0196     uint64_t u64;
0197     struct cvmx_asxx_rld_bypass_s {
0198 #ifdef __BIG_ENDIAN_BITFIELD
0199         uint64_t reserved_1_63:63;
0200         uint64_t bypass:1;
0201 #else
0202         uint64_t bypass:1;
0203         uint64_t reserved_1_63:63;
0204 #endif
0205     } s;
0206 };
0207
0208 union cvmx_asxx_rld_bypass_setting {
0209     uint64_t u64;
0210     struct cvmx_asxx_rld_bypass_setting_s {
0211 #ifdef __BIG_ENDIAN_BITFIELD
0212         uint64_t reserved_5_63:59;
0213         uint64_t setting:5;
0214 #else
0215         uint64_t setting:5;
0216         uint64_t reserved_5_63:59;
0217 #endif
0218     } s;
0219 };
0220
0221 union cvmx_asxx_rld_comp {
0222     uint64_t u64;
0223     struct cvmx_asxx_rld_comp_s {
0224 #ifdef __BIG_ENDIAN_BITFIELD
0225         uint64_t reserved_9_63:55;
0226         uint64_t pctl:5;
0227         uint64_t nctl:4;
0228 #else
0229         uint64_t nctl:4;
0230         uint64_t pctl:5;
0231         uint64_t reserved_9_63:55;
0232 #endif
0233     } s;
0234     struct cvmx_asxx_rld_comp_cn38xx {
0235 #ifdef __BIG_ENDIAN_BITFIELD
0236         uint64_t reserved_8_63:56;
0237         uint64_t pctl:4;
0238         uint64_t nctl:4;
0239 #else
0240         uint64_t nctl:4;
0241         uint64_t pctl:4;
0242         uint64_t reserved_8_63:56;
0243 #endif
0244     } cn38xx;
0245 };
0246
0247 union cvmx_asxx_rld_data_drv {
0248     uint64_t u64;
0249     struct cvmx_asxx_rld_data_drv_s {
0250 #ifdef __BIG_ENDIAN_BITFIELD
0251         uint64_t reserved_8_63:56;
0252         uint64_t pctl:4;
0253         uint64_t nctl:4;
0254 #else
0255         uint64_t nctl:4;
0256         uint64_t pctl:4;
0257         uint64_t reserved_8_63:56;
0258 #endif
0259     } s;
0260 };
0261
0262 union cvmx_asxx_rld_fcram_mode {
0263     uint64_t u64;
0264     struct cvmx_asxx_rld_fcram_mode_s {
0265 #ifdef __BIG_ENDIAN_BITFIELD
0266         uint64_t reserved_1_63:63;
0267         uint64_t mode:1;
0268 #else
0269         uint64_t mode:1;
0270         uint64_t reserved_1_63:63;
0271 #endif
0272     } s;
0273 };
0274
0275 union cvmx_asxx_rld_nctl_strong {
0276     uint64_t u64;
0277     struct cvmx_asxx_rld_nctl_strong_s {
0278 #ifdef __BIG_ENDIAN_BITFIELD
0279         uint64_t reserved_5_63:59;
0280         uint64_t nctl:5;
0281 #else
0282         uint64_t nctl:5;
0283         uint64_t reserved_5_63:59;
0284 #endif
0285     } s;
0286 };
0287
0288 union cvmx_asxx_rld_nctl_weak {
0289     uint64_t u64;
0290     struct cvmx_asxx_rld_nctl_weak_s {
0291 #ifdef __BIG_ENDIAN_BITFIELD
0292         uint64_t reserved_5_63:59;
0293         uint64_t nctl:5;
0294 #else
0295         uint64_t nctl:5;
0296         uint64_t reserved_5_63:59;
0297 #endif
0298     } s;
0299 };
0300
0301 union cvmx_asxx_rld_pctl_strong {
0302     uint64_t u64;
0303     struct cvmx_asxx_rld_pctl_strong_s {
0304 #ifdef __BIG_ENDIAN_BITFIELD
0305         uint64_t reserved_5_63:59;
0306         uint64_t pctl:5;
0307 #else
0308         uint64_t pctl:5;
0309         uint64_t reserved_5_63:59;
0310 #endif
0311     } s;
0312 };
0313
0314 union cvmx_asxx_rld_pctl_weak {
0315     uint64_t u64;
0316     struct cvmx_asxx_rld_pctl_weak_s {
0317 #ifdef __BIG_ENDIAN_BITFIELD
0318         uint64_t reserved_5_63:59;
0319         uint64_t pctl:5;
0320 #else
0321         uint64_t pctl:5;
0322         uint64_t reserved_5_63:59;
0323 #endif
0324     } s;
0325 };
0326
0327 union cvmx_asxx_rld_setting {
0328     uint64_t u64;
0329     struct cvmx_asxx_rld_setting_s {
0330 #ifdef __BIG_ENDIAN_BITFIELD
0331         uint64_t reserved_13_63:51;
0332         uint64_t dfaset:5;
0333         uint64_t dfalag:1;
0334         uint64_t dfalead:1;
0335         uint64_t dfalock:1;
0336         uint64_t setting:5;
0337 #else
0338         uint64_t setting:5;
0339         uint64_t dfalock:1;
0340         uint64_t dfalead:1;
0341         uint64_t dfalag:1;
0342         uint64_t dfaset:5;
0343         uint64_t reserved_13_63:51;
0344 #endif
0345     } s;
0346     struct cvmx_asxx_rld_setting_cn38xx {
0347 #ifdef __BIG_ENDIAN_BITFIELD
0348         uint64_t reserved_5_63:59;
0349         uint64_t setting:5;
0350 #else
0351         uint64_t setting:5;
0352         uint64_t reserved_5_63:59;
0353 #endif
0354     } cn38xx;
0355 };
0356
0357 union cvmx_asxx_rx_clk_setx {
0358     uint64_t u64;
0359     struct cvmx_asxx_rx_clk_setx_s {
0360 #ifdef __BIG_ENDIAN_BITFIELD
0361         uint64_t reserved_5_63:59;
0362         uint64_t setting:5;
0363 #else
0364         uint64_t setting:5;
0365         uint64_t reserved_5_63:59;
0366 #endif
0367     } s;
0368 };
0369
0370 union cvmx_asxx_rx_prt_en {
0371     uint64_t u64;
0372     struct cvmx_asxx_rx_prt_en_s {
0373 #ifdef __BIG_ENDIAN_BITFIELD
0374         uint64_t reserved_4_63:60;
0375         uint64_t prt_en:4;
0376 #else
0377         uint64_t prt_en:4;
0378         uint64_t reserved_4_63:60;
0379 #endif
0380     } s;
0381     struct cvmx_asxx_rx_prt_en_cn30xx {
0382 #ifdef __BIG_ENDIAN_BITFIELD
0383         uint64_t reserved_3_63:61;
0384         uint64_t prt_en:3;
0385 #else
0386         uint64_t prt_en:3;
0387         uint64_t reserved_3_63:61;
0388 #endif
0389     } cn30xx;
0390 };
0391
0392 union cvmx_asxx_rx_wol {
0393     uint64_t u64;
0394     struct cvmx_asxx_rx_wol_s {
0395 #ifdef __BIG_ENDIAN_BITFIELD
0396         uint64_t reserved_2_63:62;
0397         uint64_t status:1;
0398         uint64_t enable:1;
0399 #else
0400         uint64_t enable:1;
0401         uint64_t status:1;
0402         uint64_t reserved_2_63:62;
0403 #endif
0404     } s;
0405 };
0406
0407 union cvmx_asxx_rx_wol_msk {
0408     uint64_t u64;
0409     struct cvmx_asxx_rx_wol_msk_s {
0410 #ifdef __BIG_ENDIAN_BITFIELD
0411         uint64_t msk:64;
0412 #else
0413         uint64_t msk:64;
0414 #endif
0415     } s;
0416 };
0417
0418 union cvmx_asxx_rx_wol_powok {
0419     uint64_t u64;
0420     struct cvmx_asxx_rx_wol_powok_s {
0421 #ifdef __BIG_ENDIAN_BITFIELD
0422         uint64_t reserved_1_63:63;
0423         uint64_t powerok:1;
0424 #else
0425         uint64_t powerok:1;
0426         uint64_t reserved_1_63:63;
0427 #endif
0428     } s;
0429 };
0430
0431 union cvmx_asxx_rx_wol_sig {
0432     uint64_t u64;
0433     struct cvmx_asxx_rx_wol_sig_s {
0434 #ifdef __BIG_ENDIAN_BITFIELD
0435         uint64_t reserved_32_63:32;
0436         uint64_t sig:32;
0437 #else
0438         uint64_t sig:32;
0439         uint64_t reserved_32_63:32;
0440 #endif
0441     } s;
0442 };
0443
0444 union cvmx_asxx_tx_clk_setx {
0445     uint64_t u64;
0446     struct cvmx_asxx_tx_clk_setx_s {
0447 #ifdef __BIG_ENDIAN_BITFIELD
0448         uint64_t reserved_5_63:59;
0449         uint64_t setting:5;
0450 #else
0451         uint64_t setting:5;
0452         uint64_t reserved_5_63:59;
0453 #endif
0454     } s;
0455 };
0456
0457 union cvmx_asxx_tx_comp_byp {
0458     uint64_t u64;
0459     struct cvmx_asxx_tx_comp_byp_s {
0460 #ifdef __BIG_ENDIAN_BITFIELD
0461         uint64_t reserved_0_63:64;
0462 #else
0463         uint64_t reserved_0_63:64;
0464 #endif
0465     } s;
0466     struct cvmx_asxx_tx_comp_byp_cn30xx {
0467 #ifdef __BIG_ENDIAN_BITFIELD
0468         uint64_t reserved_9_63:55;
0469         uint64_t bypass:1;
0470         uint64_t pctl:4;
0471         uint64_t nctl:4;
0472 #else
0473         uint64_t nctl:4;
0474         uint64_t pctl:4;
0475         uint64_t bypass:1;
0476         uint64_t reserved_9_63:55;
0477 #endif
0478     } cn30xx;
0479     struct cvmx_asxx_tx_comp_byp_cn38xx {
0480 #ifdef __BIG_ENDIAN_BITFIELD
0481         uint64_t reserved_8_63:56;
0482         uint64_t pctl:4;
0483         uint64_t nctl:4;
0484 #else
0485         uint64_t nctl:4;
0486         uint64_t pctl:4;
0487         uint64_t reserved_8_63:56;
0488 #endif
0489     } cn38xx;
0490     struct cvmx_asxx_tx_comp_byp_cn50xx {
0491 #ifdef __BIG_ENDIAN_BITFIELD
0492         uint64_t reserved_17_63:47;
0493         uint64_t bypass:1;
0494         uint64_t reserved_13_15:3;
0495         uint64_t pctl:5;
0496         uint64_t reserved_5_7:3;
0497         uint64_t nctl:5;
0498 #else
0499         uint64_t nctl:5;
0500         uint64_t reserved_5_7:3;
0501         uint64_t pctl:5;
0502         uint64_t reserved_13_15:3;
0503         uint64_t bypass:1;
0504         uint64_t reserved_17_63:47;
0505 #endif
0506     } cn50xx;
0507     struct cvmx_asxx_tx_comp_byp_cn58xx {
0508 #ifdef __BIG_ENDIAN_BITFIELD
0509         uint64_t reserved_13_63:51;
0510         uint64_t pctl:5;
0511         uint64_t reserved_5_7:3;
0512         uint64_t nctl:5;
0513 #else
0514         uint64_t nctl:5;
0515         uint64_t reserved_5_7:3;
0516         uint64_t pctl:5;
0517         uint64_t reserved_13_63:51;
0518 #endif
0519     } cn58xx;
0520 };
0521
0522 union cvmx_asxx_tx_hi_waterx {
0523     uint64_t u64;
0524     struct cvmx_asxx_tx_hi_waterx_s {
0525 #ifdef __BIG_ENDIAN_BITFIELD
0526         uint64_t reserved_4_63:60;
0527         uint64_t mark:4;
0528 #else
0529         uint64_t mark:4;
0530         uint64_t reserved_4_63:60;
0531 #endif
0532     } s;
0533     struct cvmx_asxx_tx_hi_waterx_cn30xx {
0534 #ifdef __BIG_ENDIAN_BITFIELD
0535         uint64_t reserved_3_63:61;
0536         uint64_t mark:3;
0537 #else
0538         uint64_t mark:3;
0539         uint64_t reserved_3_63:61;
0540 #endif
0541     } cn30xx;
0542 };
0543
0544 union cvmx_asxx_tx_prt_en {
0545     uint64_t u64;
0546     struct cvmx_asxx_tx_prt_en_s {
0547 #ifdef __BIG_ENDIAN_BITFIELD
0548         uint64_t reserved_4_63:60;
0549         uint64_t prt_en:4;
0550 #else
0551         uint64_t prt_en:4;
0552         uint64_t reserved_4_63:60;
0553 #endif
0554     } s;
0555     struct cvmx_asxx_tx_prt_en_cn30xx {
0556 #ifdef __BIG_ENDIAN_BITFIELD
0557         uint64_t reserved_3_63:61;
0558         uint64_t prt_en:3;
0559 #else
0560         uint64_t prt_en:3;
0561         uint64_t reserved_3_63:61;
0562 #endif
0563     } cn30xx;
0564 };
0565
0566 #endif