asm/octeon/cvmx-asm.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2008 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /*
0029  *
0030  * This is file defines ASM primitives for the executive.
0031  */
0032 #ifndef __CVMX_ASM_H__
0033 #define __CVMX_ASM_H__
0034
0035 #include <asm/octeon/octeon-model.h>
0036
0037 /* other useful stuff */
0038 #define CVMX_SYNC asm volatile ("sync" : : : "memory")
0039 /* String version of SYNCW macro for using in inline asm constructs */
0040 #define CVMX_SYNCW_STR "syncw\nsyncw\n"
0041 #ifdef __OCTEON__
0042
0043 /* Deprecated, will be removed in future release */
0044 #define CVMX_SYNCIO asm volatile ("nop")
0045
0046 #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
0047
0048 /* Deprecated, will be removed in future release */
0049 #define CVMX_SYNCIOALL asm volatile ("nop")
0050
0051 /*
0052  * We actually use two syncw instructions in a row when we need a write
0053  * memory barrier. This is because the CN3XXX series of Octeons have
0054  * errata Core-401. This can cause a single syncw to not enforce
0055  * ordering under very rare conditions. Even if it is rare, better safe
0056  * than sorry.
0057  */
0058 #define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
0059
0060 /*
0061  * Define new sync instructions to be normal SYNC instructions for
0062  * operating systems that use threads.
0063  */
0064 #define CVMX_SYNCWS CVMX_SYNCW
0065 #define CVMX_SYNCS  CVMX_SYNC
0066 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
0067 #else
0068 /*
0069  * Not using a Cavium compiler, always use the slower sync so the
0070  * assembler stays happy.
0071  */
0072 /* Deprecated, will be removed in future release */
0073 #define CVMX_SYNCIO asm volatile ("nop")
0074
0075 #define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
0076
0077 /* Deprecated, will be removed in future release */
0078 #define CVMX_SYNCIOALL asm volatile ("nop")
0079
0080 #define CVMX_SYNCW asm volatile ("sync" : : : "memory")
0081 #define CVMX_SYNCWS CVMX_SYNCW
0082 #define CVMX_SYNCS  CVMX_SYNC
0083 #define CVMX_SYNCWS_STR CVMX_SYNCW_STR
0084 #endif
0085
0086 /*
0087  * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
0088  * (actually old value or zero) until that byte is stored to (by this or
0089  * another processor. Note that the value of each byte is not only
0090  * unpredictable, but may also change again - up until the point when one
0091  * of the cores stores to the byte.
0092  */
0093 #define CVMX_PREPARE_FOR_STORE(address, offset) \
0094     asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
0095     [rbase] "d" (address))
0096 /*
0097  * This is a command headed to the L2 controller to tell it to clear
0098  * its dirty bit for a block. Basically, SW is telling HW that the
0099  * current version of the block will not be used.
0100  */
0101 #define CVMX_DONT_WRITE_BACK(address, offset) \
0102     asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
0103     [rbase] "d" (address))
0104
0105 /* flush stores, invalidate entire icache */
0106 #define CVMX_ICACHE_INVALIDATE \
0107     { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
0108
0109 /* flush stores, invalidate entire icache */
0110 #define CVMX_ICACHE_INVALIDATE2 \
0111     { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
0112
0113 /* complete prefetches, invalidate entire dcache */
0114 #define CVMX_DCACHE_INVALIDATE \
0115     { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
0116
0117 #define CVMX_CACHE(op, address, offset)                 \
0118     asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
0119         : : [rbase] "d" (address) )
0120 /* fetch and lock the state. */
0121 #define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
0122 /* unlock the state. */
0123 #define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
0124 /* invalidate the cache block and clear the USED bits for the block */
0125 #define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
0126 /* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
0127 #define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
0128
0129 #define CVMX_POP(result, input) \
0130     asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
0131 #define CVMX_DPOP(result, input) \
0132     asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
0133
0134 /* some new cop0-like stuff */
0135 #define CVMX_RDHWR(result, regstr) \
0136     asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
0137 #define CVMX_RDHWRNV(result, regstr) \
0138     asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
0139 #endif /* __CVMX_ASM_H__ */