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0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2012 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027 
0028 #ifndef __CVMX_AGL_DEFS_H__
0029 #define __CVMX_AGL_DEFS_H__
0030 
0031 #define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
0032 #define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
0033 #define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
0034 #define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
0035 #define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
0036 #define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
0037 #define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
0038 #define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
0039 #define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
0040 #define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
0041 #define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
0042 #define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
0043 #define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
0044 #define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
0045 #define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
0046 #define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
0047 #define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
0048 #define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
0049 #define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
0050 #define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
0051 #define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
0052 #define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
0053 #define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
0054 #define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
0055 #define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
0056 #define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
0057 #define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
0058 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
0059 #define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
0060 #define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
0061 #define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
0062 #define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
0063 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
0064 #define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
0065 #define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
0066 #define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
0067 #define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
0068 #define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
0069 #define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
0070 #define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
0071 #define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
0072 #define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
0073 #define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
0074 #define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
0075 #define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
0076 #define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
0077 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
0078 #define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
0079 #define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
0080 #define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
0081 #define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
0082 #define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
0083 #define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
0084 #define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
0085 #define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
0086 #define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
0087 #define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
0088 #define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
0089 #define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
0090 #define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
0091 #define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
0092 #define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
0093 #define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
0094 #define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
0095 #define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
0096 #define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
0097 #define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
0098 #define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
0099 #define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
0100 #define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
0101 #define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
0102 #define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
0103 #define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
0104 #define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
0105 
0106 union cvmx_agl_gmx_bad_reg {
0107     uint64_t u64;
0108     struct cvmx_agl_gmx_bad_reg_s {
0109 #ifdef __BIG_ENDIAN_BITFIELD
0110         uint64_t reserved_38_63:26;
0111         uint64_t txpsh1:1;
0112         uint64_t txpop1:1;
0113         uint64_t ovrflw1:1;
0114         uint64_t txpsh:1;
0115         uint64_t txpop:1;
0116         uint64_t ovrflw:1;
0117         uint64_t reserved_27_31:5;
0118         uint64_t statovr:1;
0119         uint64_t reserved_24_25:2;
0120         uint64_t loststat:2;
0121         uint64_t reserved_4_21:18;
0122         uint64_t out_ovr:2;
0123         uint64_t reserved_0_1:2;
0124 #else
0125         uint64_t reserved_0_1:2;
0126         uint64_t out_ovr:2;
0127         uint64_t reserved_4_21:18;
0128         uint64_t loststat:2;
0129         uint64_t reserved_24_25:2;
0130         uint64_t statovr:1;
0131         uint64_t reserved_27_31:5;
0132         uint64_t ovrflw:1;
0133         uint64_t txpop:1;
0134         uint64_t txpsh:1;
0135         uint64_t ovrflw1:1;
0136         uint64_t txpop1:1;
0137         uint64_t txpsh1:1;
0138         uint64_t reserved_38_63:26;
0139 #endif
0140     } s;
0141     struct cvmx_agl_gmx_bad_reg_cn52xx {
0142 #ifdef __BIG_ENDIAN_BITFIELD
0143         uint64_t reserved_38_63:26;
0144         uint64_t txpsh1:1;
0145         uint64_t txpop1:1;
0146         uint64_t ovrflw1:1;
0147         uint64_t txpsh:1;
0148         uint64_t txpop:1;
0149         uint64_t ovrflw:1;
0150         uint64_t reserved_27_31:5;
0151         uint64_t statovr:1;
0152         uint64_t reserved_23_25:3;
0153         uint64_t loststat:1;
0154         uint64_t reserved_4_21:18;
0155         uint64_t out_ovr:2;
0156         uint64_t reserved_0_1:2;
0157 #else
0158         uint64_t reserved_0_1:2;
0159         uint64_t out_ovr:2;
0160         uint64_t reserved_4_21:18;
0161         uint64_t loststat:1;
0162         uint64_t reserved_23_25:3;
0163         uint64_t statovr:1;
0164         uint64_t reserved_27_31:5;
0165         uint64_t ovrflw:1;
0166         uint64_t txpop:1;
0167         uint64_t txpsh:1;
0168         uint64_t ovrflw1:1;
0169         uint64_t txpop1:1;
0170         uint64_t txpsh1:1;
0171         uint64_t reserved_38_63:26;
0172 #endif
0173     } cn52xx;
0174     struct cvmx_agl_gmx_bad_reg_cn56xx {
0175 #ifdef __BIG_ENDIAN_BITFIELD
0176         uint64_t reserved_35_63:29;
0177         uint64_t txpsh:1;
0178         uint64_t txpop:1;
0179         uint64_t ovrflw:1;
0180         uint64_t reserved_27_31:5;
0181         uint64_t statovr:1;
0182         uint64_t reserved_23_25:3;
0183         uint64_t loststat:1;
0184         uint64_t reserved_3_21:19;
0185         uint64_t out_ovr:1;
0186         uint64_t reserved_0_1:2;
0187 #else
0188         uint64_t reserved_0_1:2;
0189         uint64_t out_ovr:1;
0190         uint64_t reserved_3_21:19;
0191         uint64_t loststat:1;
0192         uint64_t reserved_23_25:3;
0193         uint64_t statovr:1;
0194         uint64_t reserved_27_31:5;
0195         uint64_t ovrflw:1;
0196         uint64_t txpop:1;
0197         uint64_t txpsh:1;
0198         uint64_t reserved_35_63:29;
0199 #endif
0200     } cn56xx;
0201 };
0202 
0203 union cvmx_agl_gmx_bist {
0204     uint64_t u64;
0205     struct cvmx_agl_gmx_bist_s {
0206 #ifdef __BIG_ENDIAN_BITFIELD
0207         uint64_t reserved_25_63:39;
0208         uint64_t status:25;
0209 #else
0210         uint64_t status:25;
0211         uint64_t reserved_25_63:39;
0212 #endif
0213     } s;
0214     struct cvmx_agl_gmx_bist_cn52xx {
0215 #ifdef __BIG_ENDIAN_BITFIELD
0216         uint64_t reserved_10_63:54;
0217         uint64_t status:10;
0218 #else
0219         uint64_t status:10;
0220         uint64_t reserved_10_63:54;
0221 #endif
0222     } cn52xx;
0223 };
0224 
0225 union cvmx_agl_gmx_drv_ctl {
0226     uint64_t u64;
0227     struct cvmx_agl_gmx_drv_ctl_s {
0228 #ifdef __BIG_ENDIAN_BITFIELD
0229         uint64_t reserved_49_63:15;
0230         uint64_t byp_en1:1;
0231         uint64_t reserved_45_47:3;
0232         uint64_t pctl1:5;
0233         uint64_t reserved_37_39:3;
0234         uint64_t nctl1:5;
0235         uint64_t reserved_17_31:15;
0236         uint64_t byp_en:1;
0237         uint64_t reserved_13_15:3;
0238         uint64_t pctl:5;
0239         uint64_t reserved_5_7:3;
0240         uint64_t nctl:5;
0241 #else
0242         uint64_t nctl:5;
0243         uint64_t reserved_5_7:3;
0244         uint64_t pctl:5;
0245         uint64_t reserved_13_15:3;
0246         uint64_t byp_en:1;
0247         uint64_t reserved_17_31:15;
0248         uint64_t nctl1:5;
0249         uint64_t reserved_37_39:3;
0250         uint64_t pctl1:5;
0251         uint64_t reserved_45_47:3;
0252         uint64_t byp_en1:1;
0253         uint64_t reserved_49_63:15;
0254 #endif
0255     } s;
0256     struct cvmx_agl_gmx_drv_ctl_cn56xx {
0257 #ifdef __BIG_ENDIAN_BITFIELD
0258         uint64_t reserved_17_63:47;
0259         uint64_t byp_en:1;
0260         uint64_t reserved_13_15:3;
0261         uint64_t pctl:5;
0262         uint64_t reserved_5_7:3;
0263         uint64_t nctl:5;
0264 #else
0265         uint64_t nctl:5;
0266         uint64_t reserved_5_7:3;
0267         uint64_t pctl:5;
0268         uint64_t reserved_13_15:3;
0269         uint64_t byp_en:1;
0270         uint64_t reserved_17_63:47;
0271 #endif
0272     } cn56xx;
0273 };
0274 
0275 union cvmx_agl_gmx_inf_mode {
0276     uint64_t u64;
0277     struct cvmx_agl_gmx_inf_mode_s {
0278 #ifdef __BIG_ENDIAN_BITFIELD
0279         uint64_t reserved_2_63:62;
0280         uint64_t en:1;
0281         uint64_t reserved_0_0:1;
0282 #else
0283         uint64_t reserved_0_0:1;
0284         uint64_t en:1;
0285         uint64_t reserved_2_63:62;
0286 #endif
0287     } s;
0288 };
0289 
0290 union cvmx_agl_gmx_prtx_cfg {
0291     uint64_t u64;
0292     struct cvmx_agl_gmx_prtx_cfg_s {
0293 #ifdef __BIG_ENDIAN_BITFIELD
0294         uint64_t reserved_14_63:50;
0295         uint64_t tx_idle:1;
0296         uint64_t rx_idle:1;
0297         uint64_t reserved_9_11:3;
0298         uint64_t speed_msb:1;
0299         uint64_t reserved_7_7:1;
0300         uint64_t burst:1;
0301         uint64_t tx_en:1;
0302         uint64_t rx_en:1;
0303         uint64_t slottime:1;
0304         uint64_t duplex:1;
0305         uint64_t speed:1;
0306         uint64_t en:1;
0307 #else
0308         uint64_t en:1;
0309         uint64_t speed:1;
0310         uint64_t duplex:1;
0311         uint64_t slottime:1;
0312         uint64_t rx_en:1;
0313         uint64_t tx_en:1;
0314         uint64_t burst:1;
0315         uint64_t reserved_7_7:1;
0316         uint64_t speed_msb:1;
0317         uint64_t reserved_9_11:3;
0318         uint64_t rx_idle:1;
0319         uint64_t tx_idle:1;
0320         uint64_t reserved_14_63:50;
0321 #endif
0322     } s;
0323     struct cvmx_agl_gmx_prtx_cfg_cn52xx {
0324 #ifdef __BIG_ENDIAN_BITFIELD
0325         uint64_t reserved_6_63:58;
0326         uint64_t tx_en:1;
0327         uint64_t rx_en:1;
0328         uint64_t slottime:1;
0329         uint64_t duplex:1;
0330         uint64_t speed:1;
0331         uint64_t en:1;
0332 #else
0333         uint64_t en:1;
0334         uint64_t speed:1;
0335         uint64_t duplex:1;
0336         uint64_t slottime:1;
0337         uint64_t rx_en:1;
0338         uint64_t tx_en:1;
0339         uint64_t reserved_6_63:58;
0340 #endif
0341     } cn52xx;
0342 };
0343 
0344 union cvmx_agl_gmx_rxx_adr_cam0 {
0345     uint64_t u64;
0346     struct cvmx_agl_gmx_rxx_adr_cam0_s {
0347 #ifdef __BIG_ENDIAN_BITFIELD
0348         uint64_t adr:64;
0349 #else
0350         uint64_t adr:64;
0351 #endif
0352     } s;
0353 };
0354 
0355 union cvmx_agl_gmx_rxx_adr_cam1 {
0356     uint64_t u64;
0357     struct cvmx_agl_gmx_rxx_adr_cam1_s {
0358 #ifdef __BIG_ENDIAN_BITFIELD
0359         uint64_t adr:64;
0360 #else
0361         uint64_t adr:64;
0362 #endif
0363     } s;
0364 };
0365 
0366 union cvmx_agl_gmx_rxx_adr_cam2 {
0367     uint64_t u64;
0368     struct cvmx_agl_gmx_rxx_adr_cam2_s {
0369 #ifdef __BIG_ENDIAN_BITFIELD
0370         uint64_t adr:64;
0371 #else
0372         uint64_t adr:64;
0373 #endif
0374     } s;
0375 };
0376 
0377 union cvmx_agl_gmx_rxx_adr_cam3 {
0378     uint64_t u64;
0379     struct cvmx_agl_gmx_rxx_adr_cam3_s {
0380 #ifdef __BIG_ENDIAN_BITFIELD
0381         uint64_t adr:64;
0382 #else
0383         uint64_t adr:64;
0384 #endif
0385     } s;
0386 };
0387 
0388 union cvmx_agl_gmx_rxx_adr_cam4 {
0389     uint64_t u64;
0390     struct cvmx_agl_gmx_rxx_adr_cam4_s {
0391 #ifdef __BIG_ENDIAN_BITFIELD
0392         uint64_t adr:64;
0393 #else
0394         uint64_t adr:64;
0395 #endif
0396     } s;
0397 };
0398 
0399 union cvmx_agl_gmx_rxx_adr_cam5 {
0400     uint64_t u64;
0401     struct cvmx_agl_gmx_rxx_adr_cam5_s {
0402 #ifdef __BIG_ENDIAN_BITFIELD
0403         uint64_t adr:64;
0404 #else
0405         uint64_t adr:64;
0406 #endif
0407     } s;
0408 };
0409 
0410 union cvmx_agl_gmx_rxx_adr_cam_en {
0411     uint64_t u64;
0412     struct cvmx_agl_gmx_rxx_adr_cam_en_s {
0413 #ifdef __BIG_ENDIAN_BITFIELD
0414         uint64_t reserved_8_63:56;
0415         uint64_t en:8;
0416 #else
0417         uint64_t en:8;
0418         uint64_t reserved_8_63:56;
0419 #endif
0420     } s;
0421 };
0422 
0423 union cvmx_agl_gmx_rxx_adr_ctl {
0424     uint64_t u64;
0425     struct cvmx_agl_gmx_rxx_adr_ctl_s {
0426 #ifdef __BIG_ENDIAN_BITFIELD
0427         uint64_t reserved_4_63:60;
0428         uint64_t cam_mode:1;
0429         uint64_t mcst:2;
0430         uint64_t bcst:1;
0431 #else
0432         uint64_t bcst:1;
0433         uint64_t mcst:2;
0434         uint64_t cam_mode:1;
0435         uint64_t reserved_4_63:60;
0436 #endif
0437     } s;
0438 };
0439 
0440 union cvmx_agl_gmx_rxx_decision {
0441     uint64_t u64;
0442     struct cvmx_agl_gmx_rxx_decision_s {
0443 #ifdef __BIG_ENDIAN_BITFIELD
0444         uint64_t reserved_5_63:59;
0445         uint64_t cnt:5;
0446 #else
0447         uint64_t cnt:5;
0448         uint64_t reserved_5_63:59;
0449 #endif
0450     } s;
0451 };
0452 
0453 union cvmx_agl_gmx_rxx_frm_chk {
0454     uint64_t u64;
0455     struct cvmx_agl_gmx_rxx_frm_chk_s {
0456 #ifdef __BIG_ENDIAN_BITFIELD
0457         uint64_t reserved_10_63:54;
0458         uint64_t niberr:1;
0459         uint64_t skperr:1;
0460         uint64_t rcverr:1;
0461         uint64_t lenerr:1;
0462         uint64_t alnerr:1;
0463         uint64_t fcserr:1;
0464         uint64_t jabber:1;
0465         uint64_t maxerr:1;
0466         uint64_t carext:1;
0467         uint64_t minerr:1;
0468 #else
0469         uint64_t minerr:1;
0470         uint64_t carext:1;
0471         uint64_t maxerr:1;
0472         uint64_t jabber:1;
0473         uint64_t fcserr:1;
0474         uint64_t alnerr:1;
0475         uint64_t lenerr:1;
0476         uint64_t rcverr:1;
0477         uint64_t skperr:1;
0478         uint64_t niberr:1;
0479         uint64_t reserved_10_63:54;
0480 #endif
0481     } s;
0482     struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
0483 #ifdef __BIG_ENDIAN_BITFIELD
0484         uint64_t reserved_9_63:55;
0485         uint64_t skperr:1;
0486         uint64_t rcverr:1;
0487         uint64_t lenerr:1;
0488         uint64_t alnerr:1;
0489         uint64_t fcserr:1;
0490         uint64_t jabber:1;
0491         uint64_t maxerr:1;
0492         uint64_t reserved_1_1:1;
0493         uint64_t minerr:1;
0494 #else
0495         uint64_t minerr:1;
0496         uint64_t reserved_1_1:1;
0497         uint64_t maxerr:1;
0498         uint64_t jabber:1;
0499         uint64_t fcserr:1;
0500         uint64_t alnerr:1;
0501         uint64_t lenerr:1;
0502         uint64_t rcverr:1;
0503         uint64_t skperr:1;
0504         uint64_t reserved_9_63:55;
0505 #endif
0506     } cn52xx;
0507 };
0508 
0509 union cvmx_agl_gmx_rxx_frm_ctl {
0510     uint64_t u64;
0511     struct cvmx_agl_gmx_rxx_frm_ctl_s {
0512 #ifdef __BIG_ENDIAN_BITFIELD
0513         uint64_t reserved_13_63:51;
0514         uint64_t ptp_mode:1;
0515         uint64_t reserved_11_11:1;
0516         uint64_t null_dis:1;
0517         uint64_t pre_align:1;
0518         uint64_t pad_len:1;
0519         uint64_t vlan_len:1;
0520         uint64_t pre_free:1;
0521         uint64_t ctl_smac:1;
0522         uint64_t ctl_mcst:1;
0523         uint64_t ctl_bck:1;
0524         uint64_t ctl_drp:1;
0525         uint64_t pre_strp:1;
0526         uint64_t pre_chk:1;
0527 #else
0528         uint64_t pre_chk:1;
0529         uint64_t pre_strp:1;
0530         uint64_t ctl_drp:1;
0531         uint64_t ctl_bck:1;
0532         uint64_t ctl_mcst:1;
0533         uint64_t ctl_smac:1;
0534         uint64_t pre_free:1;
0535         uint64_t vlan_len:1;
0536         uint64_t pad_len:1;
0537         uint64_t pre_align:1;
0538         uint64_t null_dis:1;
0539         uint64_t reserved_11_11:1;
0540         uint64_t ptp_mode:1;
0541         uint64_t reserved_13_63:51;
0542 #endif
0543     } s;
0544     struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
0545 #ifdef __BIG_ENDIAN_BITFIELD
0546         uint64_t reserved_10_63:54;
0547         uint64_t pre_align:1;
0548         uint64_t pad_len:1;
0549         uint64_t vlan_len:1;
0550         uint64_t pre_free:1;
0551         uint64_t ctl_smac:1;
0552         uint64_t ctl_mcst:1;
0553         uint64_t ctl_bck:1;
0554         uint64_t ctl_drp:1;
0555         uint64_t pre_strp:1;
0556         uint64_t pre_chk:1;
0557 #else
0558         uint64_t pre_chk:1;
0559         uint64_t pre_strp:1;
0560         uint64_t ctl_drp:1;
0561         uint64_t ctl_bck:1;
0562         uint64_t ctl_mcst:1;
0563         uint64_t ctl_smac:1;
0564         uint64_t pre_free:1;
0565         uint64_t vlan_len:1;
0566         uint64_t pad_len:1;
0567         uint64_t pre_align:1;
0568         uint64_t reserved_10_63:54;
0569 #endif
0570     } cn52xx;
0571 };
0572 
0573 union cvmx_agl_gmx_rxx_frm_max {
0574     uint64_t u64;
0575     struct cvmx_agl_gmx_rxx_frm_max_s {
0576 #ifdef __BIG_ENDIAN_BITFIELD
0577         uint64_t reserved_16_63:48;
0578         uint64_t len:16;
0579 #else
0580         uint64_t len:16;
0581         uint64_t reserved_16_63:48;
0582 #endif
0583     } s;
0584 };
0585 
0586 union cvmx_agl_gmx_rxx_frm_min {
0587     uint64_t u64;
0588     struct cvmx_agl_gmx_rxx_frm_min_s {
0589 #ifdef __BIG_ENDIAN_BITFIELD
0590         uint64_t reserved_16_63:48;
0591         uint64_t len:16;
0592 #else
0593         uint64_t len:16;
0594         uint64_t reserved_16_63:48;
0595 #endif
0596     } s;
0597 };
0598 
0599 union cvmx_agl_gmx_rxx_ifg {
0600     uint64_t u64;
0601     struct cvmx_agl_gmx_rxx_ifg_s {
0602 #ifdef __BIG_ENDIAN_BITFIELD
0603         uint64_t reserved_4_63:60;
0604         uint64_t ifg:4;
0605 #else
0606         uint64_t ifg:4;
0607         uint64_t reserved_4_63:60;
0608 #endif
0609     } s;
0610 };
0611 
0612 union cvmx_agl_gmx_rxx_int_en {
0613     uint64_t u64;
0614     struct cvmx_agl_gmx_rxx_int_en_s {
0615 #ifdef __BIG_ENDIAN_BITFIELD
0616         uint64_t reserved_20_63:44;
0617         uint64_t pause_drp:1;
0618         uint64_t phy_dupx:1;
0619         uint64_t phy_spd:1;
0620         uint64_t phy_link:1;
0621         uint64_t ifgerr:1;
0622         uint64_t coldet:1;
0623         uint64_t falerr:1;
0624         uint64_t rsverr:1;
0625         uint64_t pcterr:1;
0626         uint64_t ovrerr:1;
0627         uint64_t niberr:1;
0628         uint64_t skperr:1;
0629         uint64_t rcverr:1;
0630         uint64_t lenerr:1;
0631         uint64_t alnerr:1;
0632         uint64_t fcserr:1;
0633         uint64_t jabber:1;
0634         uint64_t maxerr:1;
0635         uint64_t carext:1;
0636         uint64_t minerr:1;
0637 #else
0638         uint64_t minerr:1;
0639         uint64_t carext:1;
0640         uint64_t maxerr:1;
0641         uint64_t jabber:1;
0642         uint64_t fcserr:1;
0643         uint64_t alnerr:1;
0644         uint64_t lenerr:1;
0645         uint64_t rcverr:1;
0646         uint64_t skperr:1;
0647         uint64_t niberr:1;
0648         uint64_t ovrerr:1;
0649         uint64_t pcterr:1;
0650         uint64_t rsverr:1;
0651         uint64_t falerr:1;
0652         uint64_t coldet:1;
0653         uint64_t ifgerr:1;
0654         uint64_t phy_link:1;
0655         uint64_t phy_spd:1;
0656         uint64_t phy_dupx:1;
0657         uint64_t pause_drp:1;
0658         uint64_t reserved_20_63:44;
0659 #endif
0660     } s;
0661     struct cvmx_agl_gmx_rxx_int_en_cn52xx {
0662 #ifdef __BIG_ENDIAN_BITFIELD
0663         uint64_t reserved_20_63:44;
0664         uint64_t pause_drp:1;
0665         uint64_t reserved_16_18:3;
0666         uint64_t ifgerr:1;
0667         uint64_t coldet:1;
0668         uint64_t falerr:1;
0669         uint64_t rsverr:1;
0670         uint64_t pcterr:1;
0671         uint64_t ovrerr:1;
0672         uint64_t reserved_9_9:1;
0673         uint64_t skperr:1;
0674         uint64_t rcverr:1;
0675         uint64_t lenerr:1;
0676         uint64_t alnerr:1;
0677         uint64_t fcserr:1;
0678         uint64_t jabber:1;
0679         uint64_t maxerr:1;
0680         uint64_t reserved_1_1:1;
0681         uint64_t minerr:1;
0682 #else
0683         uint64_t minerr:1;
0684         uint64_t reserved_1_1:1;
0685         uint64_t maxerr:1;
0686         uint64_t jabber:1;
0687         uint64_t fcserr:1;
0688         uint64_t alnerr:1;
0689         uint64_t lenerr:1;
0690         uint64_t rcverr:1;
0691         uint64_t skperr:1;
0692         uint64_t reserved_9_9:1;
0693         uint64_t ovrerr:1;
0694         uint64_t pcterr:1;
0695         uint64_t rsverr:1;
0696         uint64_t falerr:1;
0697         uint64_t coldet:1;
0698         uint64_t ifgerr:1;
0699         uint64_t reserved_16_18:3;
0700         uint64_t pause_drp:1;
0701         uint64_t reserved_20_63:44;
0702 #endif
0703     } cn52xx;
0704 };
0705 
0706 union cvmx_agl_gmx_rxx_int_reg {
0707     uint64_t u64;
0708     struct cvmx_agl_gmx_rxx_int_reg_s {
0709 #ifdef __BIG_ENDIAN_BITFIELD
0710         uint64_t reserved_20_63:44;
0711         uint64_t pause_drp:1;
0712         uint64_t phy_dupx:1;
0713         uint64_t phy_spd:1;
0714         uint64_t phy_link:1;
0715         uint64_t ifgerr:1;
0716         uint64_t coldet:1;
0717         uint64_t falerr:1;
0718         uint64_t rsverr:1;
0719         uint64_t pcterr:1;
0720         uint64_t ovrerr:1;
0721         uint64_t niberr:1;
0722         uint64_t skperr:1;
0723         uint64_t rcverr:1;
0724         uint64_t lenerr:1;
0725         uint64_t alnerr:1;
0726         uint64_t fcserr:1;
0727         uint64_t jabber:1;
0728         uint64_t maxerr:1;
0729         uint64_t carext:1;
0730         uint64_t minerr:1;
0731 #else
0732         uint64_t minerr:1;
0733         uint64_t carext:1;
0734         uint64_t maxerr:1;
0735         uint64_t jabber:1;
0736         uint64_t fcserr:1;
0737         uint64_t alnerr:1;
0738         uint64_t lenerr:1;
0739         uint64_t rcverr:1;
0740         uint64_t skperr:1;
0741         uint64_t niberr:1;
0742         uint64_t ovrerr:1;
0743         uint64_t pcterr:1;
0744         uint64_t rsverr:1;
0745         uint64_t falerr:1;
0746         uint64_t coldet:1;
0747         uint64_t ifgerr:1;
0748         uint64_t phy_link:1;
0749         uint64_t phy_spd:1;
0750         uint64_t phy_dupx:1;
0751         uint64_t pause_drp:1;
0752         uint64_t reserved_20_63:44;
0753 #endif
0754     } s;
0755     struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
0756 #ifdef __BIG_ENDIAN_BITFIELD
0757         uint64_t reserved_20_63:44;
0758         uint64_t pause_drp:1;
0759         uint64_t reserved_16_18:3;
0760         uint64_t ifgerr:1;
0761         uint64_t coldet:1;
0762         uint64_t falerr:1;
0763         uint64_t rsverr:1;
0764         uint64_t pcterr:1;
0765         uint64_t ovrerr:1;
0766         uint64_t reserved_9_9:1;
0767         uint64_t skperr:1;
0768         uint64_t rcverr:1;
0769         uint64_t lenerr:1;
0770         uint64_t alnerr:1;
0771         uint64_t fcserr:1;
0772         uint64_t jabber:1;
0773         uint64_t maxerr:1;
0774         uint64_t reserved_1_1:1;
0775         uint64_t minerr:1;
0776 #else
0777         uint64_t minerr:1;
0778         uint64_t reserved_1_1:1;
0779         uint64_t maxerr:1;
0780         uint64_t jabber:1;
0781         uint64_t fcserr:1;
0782         uint64_t alnerr:1;
0783         uint64_t lenerr:1;
0784         uint64_t rcverr:1;
0785         uint64_t skperr:1;
0786         uint64_t reserved_9_9:1;
0787         uint64_t ovrerr:1;
0788         uint64_t pcterr:1;
0789         uint64_t rsverr:1;
0790         uint64_t falerr:1;
0791         uint64_t coldet:1;
0792         uint64_t ifgerr:1;
0793         uint64_t reserved_16_18:3;
0794         uint64_t pause_drp:1;
0795         uint64_t reserved_20_63:44;
0796 #endif
0797     } cn52xx;
0798 };
0799 
0800 union cvmx_agl_gmx_rxx_jabber {
0801     uint64_t u64;
0802     struct cvmx_agl_gmx_rxx_jabber_s {
0803 #ifdef __BIG_ENDIAN_BITFIELD
0804         uint64_t reserved_16_63:48;
0805         uint64_t cnt:16;
0806 #else
0807         uint64_t cnt:16;
0808         uint64_t reserved_16_63:48;
0809 #endif
0810     } s;
0811 };
0812 
0813 union cvmx_agl_gmx_rxx_pause_drop_time {
0814     uint64_t u64;
0815     struct cvmx_agl_gmx_rxx_pause_drop_time_s {
0816 #ifdef __BIG_ENDIAN_BITFIELD
0817         uint64_t reserved_16_63:48;
0818         uint64_t status:16;
0819 #else
0820         uint64_t status:16;
0821         uint64_t reserved_16_63:48;
0822 #endif
0823     } s;
0824 };
0825 
0826 union cvmx_agl_gmx_rxx_rx_inbnd {
0827     uint64_t u64;
0828     struct cvmx_agl_gmx_rxx_rx_inbnd_s {
0829 #ifdef __BIG_ENDIAN_BITFIELD
0830         uint64_t reserved_4_63:60;
0831         uint64_t duplex:1;
0832         uint64_t speed:2;
0833         uint64_t status:1;
0834 #else
0835         uint64_t status:1;
0836         uint64_t speed:2;
0837         uint64_t duplex:1;
0838         uint64_t reserved_4_63:60;
0839 #endif
0840     } s;
0841 };
0842 
0843 union cvmx_agl_gmx_rxx_stats_ctl {
0844     uint64_t u64;
0845     struct cvmx_agl_gmx_rxx_stats_ctl_s {
0846 #ifdef __BIG_ENDIAN_BITFIELD
0847         uint64_t reserved_1_63:63;
0848         uint64_t rd_clr:1;
0849 #else
0850         uint64_t rd_clr:1;
0851         uint64_t reserved_1_63:63;
0852 #endif
0853     } s;
0854 };
0855 
0856 union cvmx_agl_gmx_rxx_stats_octs {
0857     uint64_t u64;
0858     struct cvmx_agl_gmx_rxx_stats_octs_s {
0859 #ifdef __BIG_ENDIAN_BITFIELD
0860         uint64_t reserved_48_63:16;
0861         uint64_t cnt:48;
0862 #else
0863         uint64_t cnt:48;
0864         uint64_t reserved_48_63:16;
0865 #endif
0866     } s;
0867 };
0868 
0869 union cvmx_agl_gmx_rxx_stats_octs_ctl {
0870     uint64_t u64;
0871     struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
0872 #ifdef __BIG_ENDIAN_BITFIELD
0873         uint64_t reserved_48_63:16;
0874         uint64_t cnt:48;
0875 #else
0876         uint64_t cnt:48;
0877         uint64_t reserved_48_63:16;
0878 #endif
0879     } s;
0880 };
0881 
0882 union cvmx_agl_gmx_rxx_stats_octs_dmac {
0883     uint64_t u64;
0884     struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
0885 #ifdef __BIG_ENDIAN_BITFIELD
0886         uint64_t reserved_48_63:16;
0887         uint64_t cnt:48;
0888 #else
0889         uint64_t cnt:48;
0890         uint64_t reserved_48_63:16;
0891 #endif
0892     } s;
0893 };
0894 
0895 union cvmx_agl_gmx_rxx_stats_octs_drp {
0896     uint64_t u64;
0897     struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
0898 #ifdef __BIG_ENDIAN_BITFIELD
0899         uint64_t reserved_48_63:16;
0900         uint64_t cnt:48;
0901 #else
0902         uint64_t cnt:48;
0903         uint64_t reserved_48_63:16;
0904 #endif
0905     } s;
0906 };
0907 
0908 union cvmx_agl_gmx_rxx_stats_pkts {
0909     uint64_t u64;
0910     struct cvmx_agl_gmx_rxx_stats_pkts_s {
0911 #ifdef __BIG_ENDIAN_BITFIELD
0912         uint64_t reserved_32_63:32;
0913         uint64_t cnt:32;
0914 #else
0915         uint64_t cnt:32;
0916         uint64_t reserved_32_63:32;
0917 #endif
0918     } s;
0919 };
0920 
0921 union cvmx_agl_gmx_rxx_stats_pkts_bad {
0922     uint64_t u64;
0923     struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
0924 #ifdef __BIG_ENDIAN_BITFIELD
0925         uint64_t reserved_32_63:32;
0926         uint64_t cnt:32;
0927 #else
0928         uint64_t cnt:32;
0929         uint64_t reserved_32_63:32;
0930 #endif
0931     } s;
0932 };
0933 
0934 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
0935     uint64_t u64;
0936     struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
0937 #ifdef __BIG_ENDIAN_BITFIELD
0938         uint64_t reserved_32_63:32;
0939         uint64_t cnt:32;
0940 #else
0941         uint64_t cnt:32;
0942         uint64_t reserved_32_63:32;
0943 #endif
0944     } s;
0945 };
0946 
0947 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
0948     uint64_t u64;
0949     struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
0950 #ifdef __BIG_ENDIAN_BITFIELD
0951         uint64_t reserved_32_63:32;
0952         uint64_t cnt:32;
0953 #else
0954         uint64_t cnt:32;
0955         uint64_t reserved_32_63:32;
0956 #endif
0957     } s;
0958 };
0959 
0960 union cvmx_agl_gmx_rxx_stats_pkts_drp {
0961     uint64_t u64;
0962     struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
0963 #ifdef __BIG_ENDIAN_BITFIELD
0964         uint64_t reserved_32_63:32;
0965         uint64_t cnt:32;
0966 #else
0967         uint64_t cnt:32;
0968         uint64_t reserved_32_63:32;
0969 #endif
0970     } s;
0971 };
0972 
0973 union cvmx_agl_gmx_rxx_udd_skp {
0974     uint64_t u64;
0975     struct cvmx_agl_gmx_rxx_udd_skp_s {
0976 #ifdef __BIG_ENDIAN_BITFIELD
0977         uint64_t reserved_9_63:55;
0978         uint64_t fcssel:1;
0979         uint64_t reserved_7_7:1;
0980         uint64_t len:7;
0981 #else
0982         uint64_t len:7;
0983         uint64_t reserved_7_7:1;
0984         uint64_t fcssel:1;
0985         uint64_t reserved_9_63:55;
0986 #endif
0987     } s;
0988 };
0989 
0990 union cvmx_agl_gmx_rx_bp_dropx {
0991     uint64_t u64;
0992     struct cvmx_agl_gmx_rx_bp_dropx_s {
0993 #ifdef __BIG_ENDIAN_BITFIELD
0994         uint64_t reserved_6_63:58;
0995         uint64_t mark:6;
0996 #else
0997         uint64_t mark:6;
0998         uint64_t reserved_6_63:58;
0999 #endif
1000     } s;
1001 };
1002 
1003 union cvmx_agl_gmx_rx_bp_offx {
1004     uint64_t u64;
1005     struct cvmx_agl_gmx_rx_bp_offx_s {
1006 #ifdef __BIG_ENDIAN_BITFIELD
1007         uint64_t reserved_6_63:58;
1008         uint64_t mark:6;
1009 #else
1010         uint64_t mark:6;
1011         uint64_t reserved_6_63:58;
1012 #endif
1013     } s;
1014 };
1015 
1016 union cvmx_agl_gmx_rx_bp_onx {
1017     uint64_t u64;
1018     struct cvmx_agl_gmx_rx_bp_onx_s {
1019 #ifdef __BIG_ENDIAN_BITFIELD
1020         uint64_t reserved_9_63:55;
1021         uint64_t mark:9;
1022 #else
1023         uint64_t mark:9;
1024         uint64_t reserved_9_63:55;
1025 #endif
1026     } s;
1027 };
1028 
1029 union cvmx_agl_gmx_rx_prt_info {
1030     uint64_t u64;
1031     struct cvmx_agl_gmx_rx_prt_info_s {
1032 #ifdef __BIG_ENDIAN_BITFIELD
1033         uint64_t reserved_18_63:46;
1034         uint64_t drop:2;
1035         uint64_t reserved_2_15:14;
1036         uint64_t commit:2;
1037 #else
1038         uint64_t commit:2;
1039         uint64_t reserved_2_15:14;
1040         uint64_t drop:2;
1041         uint64_t reserved_18_63:46;
1042 #endif
1043     } s;
1044     struct cvmx_agl_gmx_rx_prt_info_cn56xx {
1045 #ifdef __BIG_ENDIAN_BITFIELD
1046         uint64_t reserved_17_63:47;
1047         uint64_t drop:1;
1048         uint64_t reserved_1_15:15;
1049         uint64_t commit:1;
1050 #else
1051         uint64_t commit:1;
1052         uint64_t reserved_1_15:15;
1053         uint64_t drop:1;
1054         uint64_t reserved_17_63:47;
1055 #endif
1056     } cn56xx;
1057 };
1058 
1059 union cvmx_agl_gmx_rx_tx_status {
1060     uint64_t u64;
1061     struct cvmx_agl_gmx_rx_tx_status_s {
1062 #ifdef __BIG_ENDIAN_BITFIELD
1063         uint64_t reserved_6_63:58;
1064         uint64_t tx:2;
1065         uint64_t reserved_2_3:2;
1066         uint64_t rx:2;
1067 #else
1068         uint64_t rx:2;
1069         uint64_t reserved_2_3:2;
1070         uint64_t tx:2;
1071         uint64_t reserved_6_63:58;
1072 #endif
1073     } s;
1074     struct cvmx_agl_gmx_rx_tx_status_cn56xx {
1075 #ifdef __BIG_ENDIAN_BITFIELD
1076         uint64_t reserved_5_63:59;
1077         uint64_t tx:1;
1078         uint64_t reserved_1_3:3;
1079         uint64_t rx:1;
1080 #else
1081         uint64_t rx:1;
1082         uint64_t reserved_1_3:3;
1083         uint64_t tx:1;
1084         uint64_t reserved_5_63:59;
1085 #endif
1086     } cn56xx;
1087 };
1088 
1089 union cvmx_agl_gmx_smacx {
1090     uint64_t u64;
1091     struct cvmx_agl_gmx_smacx_s {
1092 #ifdef __BIG_ENDIAN_BITFIELD
1093         uint64_t reserved_48_63:16;
1094         uint64_t smac:48;
1095 #else
1096         uint64_t smac:48;
1097         uint64_t reserved_48_63:16;
1098 #endif
1099     } s;
1100 };
1101 
1102 union cvmx_agl_gmx_stat_bp {
1103     uint64_t u64;
1104     struct cvmx_agl_gmx_stat_bp_s {
1105 #ifdef __BIG_ENDIAN_BITFIELD
1106         uint64_t reserved_17_63:47;
1107         uint64_t bp:1;
1108         uint64_t cnt:16;
1109 #else
1110         uint64_t cnt:16;
1111         uint64_t bp:1;
1112         uint64_t reserved_17_63:47;
1113 #endif
1114     } s;
1115 };
1116 
1117 union cvmx_agl_gmx_txx_append {
1118     uint64_t u64;
1119     struct cvmx_agl_gmx_txx_append_s {
1120 #ifdef __BIG_ENDIAN_BITFIELD
1121         uint64_t reserved_4_63:60;
1122         uint64_t force_fcs:1;
1123         uint64_t fcs:1;
1124         uint64_t pad:1;
1125         uint64_t preamble:1;
1126 #else
1127         uint64_t preamble:1;
1128         uint64_t pad:1;
1129         uint64_t fcs:1;
1130         uint64_t force_fcs:1;
1131         uint64_t reserved_4_63:60;
1132 #endif
1133     } s;
1134 };
1135 
1136 union cvmx_agl_gmx_txx_clk {
1137     uint64_t u64;
1138     struct cvmx_agl_gmx_txx_clk_s {
1139 #ifdef __BIG_ENDIAN_BITFIELD
1140         uint64_t reserved_6_63:58;
1141         uint64_t clk_cnt:6;
1142 #else
1143         uint64_t clk_cnt:6;
1144         uint64_t reserved_6_63:58;
1145 #endif
1146     } s;
1147 };
1148 
1149 union cvmx_agl_gmx_txx_ctl {
1150     uint64_t u64;
1151     struct cvmx_agl_gmx_txx_ctl_s {
1152 #ifdef __BIG_ENDIAN_BITFIELD
1153         uint64_t reserved_2_63:62;
1154         uint64_t xsdef_en:1;
1155         uint64_t xscol_en:1;
1156 #else
1157         uint64_t xscol_en:1;
1158         uint64_t xsdef_en:1;
1159         uint64_t reserved_2_63:62;
1160 #endif
1161     } s;
1162 };
1163 
1164 union cvmx_agl_gmx_txx_min_pkt {
1165     uint64_t u64;
1166     struct cvmx_agl_gmx_txx_min_pkt_s {
1167 #ifdef __BIG_ENDIAN_BITFIELD
1168         uint64_t reserved_8_63:56;
1169         uint64_t min_size:8;
1170 #else
1171         uint64_t min_size:8;
1172         uint64_t reserved_8_63:56;
1173 #endif
1174     } s;
1175 };
1176 
1177 union cvmx_agl_gmx_txx_pause_pkt_interval {
1178     uint64_t u64;
1179     struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
1180 #ifdef __BIG_ENDIAN_BITFIELD
1181         uint64_t reserved_16_63:48;
1182         uint64_t interval:16;
1183 #else
1184         uint64_t interval:16;
1185         uint64_t reserved_16_63:48;
1186 #endif
1187     } s;
1188 };
1189 
1190 union cvmx_agl_gmx_txx_pause_pkt_time {
1191     uint64_t u64;
1192     struct cvmx_agl_gmx_txx_pause_pkt_time_s {
1193 #ifdef __BIG_ENDIAN_BITFIELD
1194         uint64_t reserved_16_63:48;
1195         uint64_t time:16;
1196 #else
1197         uint64_t time:16;
1198         uint64_t reserved_16_63:48;
1199 #endif
1200     } s;
1201 };
1202 
1203 union cvmx_agl_gmx_txx_pause_togo {
1204     uint64_t u64;
1205     struct cvmx_agl_gmx_txx_pause_togo_s {
1206 #ifdef __BIG_ENDIAN_BITFIELD
1207         uint64_t reserved_16_63:48;
1208         uint64_t time:16;
1209 #else
1210         uint64_t time:16;
1211         uint64_t reserved_16_63:48;
1212 #endif
1213     } s;
1214 };
1215 
1216 union cvmx_agl_gmx_txx_pause_zero {
1217     uint64_t u64;
1218     struct cvmx_agl_gmx_txx_pause_zero_s {
1219 #ifdef __BIG_ENDIAN_BITFIELD
1220         uint64_t reserved_1_63:63;
1221         uint64_t send:1;
1222 #else
1223         uint64_t send:1;
1224         uint64_t reserved_1_63:63;
1225 #endif
1226     } s;
1227 };
1228 
1229 union cvmx_agl_gmx_txx_soft_pause {
1230     uint64_t u64;
1231     struct cvmx_agl_gmx_txx_soft_pause_s {
1232 #ifdef __BIG_ENDIAN_BITFIELD
1233         uint64_t reserved_16_63:48;
1234         uint64_t time:16;
1235 #else
1236         uint64_t time:16;
1237         uint64_t reserved_16_63:48;
1238 #endif
1239     } s;
1240 };
1241 
1242 union cvmx_agl_gmx_txx_stat0 {
1243     uint64_t u64;
1244     struct cvmx_agl_gmx_txx_stat0_s {
1245 #ifdef __BIG_ENDIAN_BITFIELD
1246         uint64_t xsdef:32;
1247         uint64_t xscol:32;
1248 #else
1249         uint64_t xscol:32;
1250         uint64_t xsdef:32;
1251 #endif
1252     } s;
1253 };
1254 
1255 union cvmx_agl_gmx_txx_stat1 {
1256     uint64_t u64;
1257     struct cvmx_agl_gmx_txx_stat1_s {
1258 #ifdef __BIG_ENDIAN_BITFIELD
1259         uint64_t scol:32;
1260         uint64_t mcol:32;
1261 #else
1262         uint64_t mcol:32;
1263         uint64_t scol:32;
1264 #endif
1265     } s;
1266 };
1267 
1268 union cvmx_agl_gmx_txx_stat2 {
1269     uint64_t u64;
1270     struct cvmx_agl_gmx_txx_stat2_s {
1271 #ifdef __BIG_ENDIAN_BITFIELD
1272         uint64_t reserved_48_63:16;
1273         uint64_t octs:48;
1274 #else
1275         uint64_t octs:48;
1276         uint64_t reserved_48_63:16;
1277 #endif
1278     } s;
1279 };
1280 
1281 union cvmx_agl_gmx_txx_stat3 {
1282     uint64_t u64;
1283     struct cvmx_agl_gmx_txx_stat3_s {
1284 #ifdef __BIG_ENDIAN_BITFIELD
1285         uint64_t reserved_32_63:32;
1286         uint64_t pkts:32;
1287 #else
1288         uint64_t pkts:32;
1289         uint64_t reserved_32_63:32;
1290 #endif
1291     } s;
1292 };
1293 
1294 union cvmx_agl_gmx_txx_stat4 {
1295     uint64_t u64;
1296     struct cvmx_agl_gmx_txx_stat4_s {
1297 #ifdef __BIG_ENDIAN_BITFIELD
1298         uint64_t hist1:32;
1299         uint64_t hist0:32;
1300 #else
1301         uint64_t hist0:32;
1302         uint64_t hist1:32;
1303 #endif
1304     } s;
1305 };
1306 
1307 union cvmx_agl_gmx_txx_stat5 {
1308     uint64_t u64;
1309     struct cvmx_agl_gmx_txx_stat5_s {
1310 #ifdef __BIG_ENDIAN_BITFIELD
1311         uint64_t hist3:32;
1312         uint64_t hist2:32;
1313 #else
1314         uint64_t hist2:32;
1315         uint64_t hist3:32;
1316 #endif
1317     } s;
1318 };
1319 
1320 union cvmx_agl_gmx_txx_stat6 {
1321     uint64_t u64;
1322     struct cvmx_agl_gmx_txx_stat6_s {
1323 #ifdef __BIG_ENDIAN_BITFIELD
1324         uint64_t hist5:32;
1325         uint64_t hist4:32;
1326 #else
1327         uint64_t hist4:32;
1328         uint64_t hist5:32;
1329 #endif
1330     } s;
1331 };
1332 
1333 union cvmx_agl_gmx_txx_stat7 {
1334     uint64_t u64;
1335     struct cvmx_agl_gmx_txx_stat7_s {
1336 #ifdef __BIG_ENDIAN_BITFIELD
1337         uint64_t hist7:32;
1338         uint64_t hist6:32;
1339 #else
1340         uint64_t hist6:32;
1341         uint64_t hist7:32;
1342 #endif
1343     } s;
1344 };
1345 
1346 union cvmx_agl_gmx_txx_stat8 {
1347     uint64_t u64;
1348     struct cvmx_agl_gmx_txx_stat8_s {
1349 #ifdef __BIG_ENDIAN_BITFIELD
1350         uint64_t mcst:32;
1351         uint64_t bcst:32;
1352 #else
1353         uint64_t bcst:32;
1354         uint64_t mcst:32;
1355 #endif
1356     } s;
1357 };
1358 
1359 union cvmx_agl_gmx_txx_stat9 {
1360     uint64_t u64;
1361     struct cvmx_agl_gmx_txx_stat9_s {
1362 #ifdef __BIG_ENDIAN_BITFIELD
1363         uint64_t undflw:32;
1364         uint64_t ctl:32;
1365 #else
1366         uint64_t ctl:32;
1367         uint64_t undflw:32;
1368 #endif
1369     } s;
1370 };
1371 
1372 union cvmx_agl_gmx_txx_stats_ctl {
1373     uint64_t u64;
1374     struct cvmx_agl_gmx_txx_stats_ctl_s {
1375 #ifdef __BIG_ENDIAN_BITFIELD
1376         uint64_t reserved_1_63:63;
1377         uint64_t rd_clr:1;
1378 #else
1379         uint64_t rd_clr:1;
1380         uint64_t reserved_1_63:63;
1381 #endif
1382     } s;
1383 };
1384 
1385 union cvmx_agl_gmx_txx_thresh {
1386     uint64_t u64;
1387     struct cvmx_agl_gmx_txx_thresh_s {
1388 #ifdef __BIG_ENDIAN_BITFIELD
1389         uint64_t reserved_6_63:58;
1390         uint64_t cnt:6;
1391 #else
1392         uint64_t cnt:6;
1393         uint64_t reserved_6_63:58;
1394 #endif
1395     } s;
1396 };
1397 
1398 union cvmx_agl_gmx_tx_bp {
1399     uint64_t u64;
1400     struct cvmx_agl_gmx_tx_bp_s {
1401 #ifdef __BIG_ENDIAN_BITFIELD
1402         uint64_t reserved_2_63:62;
1403         uint64_t bp:2;
1404 #else
1405         uint64_t bp:2;
1406         uint64_t reserved_2_63:62;
1407 #endif
1408     } s;
1409     struct cvmx_agl_gmx_tx_bp_cn56xx {
1410 #ifdef __BIG_ENDIAN_BITFIELD
1411         uint64_t reserved_1_63:63;
1412         uint64_t bp:1;
1413 #else
1414         uint64_t bp:1;
1415         uint64_t reserved_1_63:63;
1416 #endif
1417     } cn56xx;
1418 };
1419 
1420 union cvmx_agl_gmx_tx_col_attempt {
1421     uint64_t u64;
1422     struct cvmx_agl_gmx_tx_col_attempt_s {
1423 #ifdef __BIG_ENDIAN_BITFIELD
1424         uint64_t reserved_5_63:59;
1425         uint64_t limit:5;
1426 #else
1427         uint64_t limit:5;
1428         uint64_t reserved_5_63:59;
1429 #endif
1430     } s;
1431 };
1432 
1433 union cvmx_agl_gmx_tx_ifg {
1434     uint64_t u64;
1435     struct cvmx_agl_gmx_tx_ifg_s {
1436 #ifdef __BIG_ENDIAN_BITFIELD
1437         uint64_t reserved_8_63:56;
1438         uint64_t ifg2:4;
1439         uint64_t ifg1:4;
1440 #else
1441         uint64_t ifg1:4;
1442         uint64_t ifg2:4;
1443         uint64_t reserved_8_63:56;
1444 #endif
1445     } s;
1446 };
1447 
1448 union cvmx_agl_gmx_tx_int_en {
1449     uint64_t u64;
1450     struct cvmx_agl_gmx_tx_int_en_s {
1451 #ifdef __BIG_ENDIAN_BITFIELD
1452         uint64_t reserved_22_63:42;
1453         uint64_t ptp_lost:2;
1454         uint64_t reserved_18_19:2;
1455         uint64_t late_col:2;
1456         uint64_t reserved_14_15:2;
1457         uint64_t xsdef:2;
1458         uint64_t reserved_10_11:2;
1459         uint64_t xscol:2;
1460         uint64_t reserved_4_7:4;
1461         uint64_t undflw:2;
1462         uint64_t reserved_1_1:1;
1463         uint64_t pko_nxa:1;
1464 #else
1465         uint64_t pko_nxa:1;
1466         uint64_t reserved_1_1:1;
1467         uint64_t undflw:2;
1468         uint64_t reserved_4_7:4;
1469         uint64_t xscol:2;
1470         uint64_t reserved_10_11:2;
1471         uint64_t xsdef:2;
1472         uint64_t reserved_14_15:2;
1473         uint64_t late_col:2;
1474         uint64_t reserved_18_19:2;
1475         uint64_t ptp_lost:2;
1476         uint64_t reserved_22_63:42;
1477 #endif
1478     } s;
1479     struct cvmx_agl_gmx_tx_int_en_cn52xx {
1480 #ifdef __BIG_ENDIAN_BITFIELD
1481         uint64_t reserved_18_63:46;
1482         uint64_t late_col:2;
1483         uint64_t reserved_14_15:2;
1484         uint64_t xsdef:2;
1485         uint64_t reserved_10_11:2;
1486         uint64_t xscol:2;
1487         uint64_t reserved_4_7:4;
1488         uint64_t undflw:2;
1489         uint64_t reserved_1_1:1;
1490         uint64_t pko_nxa:1;
1491 #else
1492         uint64_t pko_nxa:1;
1493         uint64_t reserved_1_1:1;
1494         uint64_t undflw:2;
1495         uint64_t reserved_4_7:4;
1496         uint64_t xscol:2;
1497         uint64_t reserved_10_11:2;
1498         uint64_t xsdef:2;
1499         uint64_t reserved_14_15:2;
1500         uint64_t late_col:2;
1501         uint64_t reserved_18_63:46;
1502 #endif
1503     } cn52xx;
1504     struct cvmx_agl_gmx_tx_int_en_cn56xx {
1505 #ifdef __BIG_ENDIAN_BITFIELD
1506         uint64_t reserved_17_63:47;
1507         uint64_t late_col:1;
1508         uint64_t reserved_13_15:3;
1509         uint64_t xsdef:1;
1510         uint64_t reserved_9_11:3;
1511         uint64_t xscol:1;
1512         uint64_t reserved_3_7:5;
1513         uint64_t undflw:1;
1514         uint64_t reserved_1_1:1;
1515         uint64_t pko_nxa:1;
1516 #else
1517         uint64_t pko_nxa:1;
1518         uint64_t reserved_1_1:1;
1519         uint64_t undflw:1;
1520         uint64_t reserved_3_7:5;
1521         uint64_t xscol:1;
1522         uint64_t reserved_9_11:3;
1523         uint64_t xsdef:1;
1524         uint64_t reserved_13_15:3;
1525         uint64_t late_col:1;
1526         uint64_t reserved_17_63:47;
1527 #endif
1528     } cn56xx;
1529 };
1530 
1531 union cvmx_agl_gmx_tx_int_reg {
1532     uint64_t u64;
1533     struct cvmx_agl_gmx_tx_int_reg_s {
1534 #ifdef __BIG_ENDIAN_BITFIELD
1535         uint64_t reserved_22_63:42;
1536         uint64_t ptp_lost:2;
1537         uint64_t reserved_18_19:2;
1538         uint64_t late_col:2;
1539         uint64_t reserved_14_15:2;
1540         uint64_t xsdef:2;
1541         uint64_t reserved_10_11:2;
1542         uint64_t xscol:2;
1543         uint64_t reserved_4_7:4;
1544         uint64_t undflw:2;
1545         uint64_t reserved_1_1:1;
1546         uint64_t pko_nxa:1;
1547 #else
1548         uint64_t pko_nxa:1;
1549         uint64_t reserved_1_1:1;
1550         uint64_t undflw:2;
1551         uint64_t reserved_4_7:4;
1552         uint64_t xscol:2;
1553         uint64_t reserved_10_11:2;
1554         uint64_t xsdef:2;
1555         uint64_t reserved_14_15:2;
1556         uint64_t late_col:2;
1557         uint64_t reserved_18_19:2;
1558         uint64_t ptp_lost:2;
1559         uint64_t reserved_22_63:42;
1560 #endif
1561     } s;
1562     struct cvmx_agl_gmx_tx_int_reg_cn52xx {
1563 #ifdef __BIG_ENDIAN_BITFIELD
1564         uint64_t reserved_18_63:46;
1565         uint64_t late_col:2;
1566         uint64_t reserved_14_15:2;
1567         uint64_t xsdef:2;
1568         uint64_t reserved_10_11:2;
1569         uint64_t xscol:2;
1570         uint64_t reserved_4_7:4;
1571         uint64_t undflw:2;
1572         uint64_t reserved_1_1:1;
1573         uint64_t pko_nxa:1;
1574 #else
1575         uint64_t pko_nxa:1;
1576         uint64_t reserved_1_1:1;
1577         uint64_t undflw:2;
1578         uint64_t reserved_4_7:4;
1579         uint64_t xscol:2;
1580         uint64_t reserved_10_11:2;
1581         uint64_t xsdef:2;
1582         uint64_t reserved_14_15:2;
1583         uint64_t late_col:2;
1584         uint64_t reserved_18_63:46;
1585 #endif
1586     } cn52xx;
1587     struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1588 #ifdef __BIG_ENDIAN_BITFIELD
1589         uint64_t reserved_17_63:47;
1590         uint64_t late_col:1;
1591         uint64_t reserved_13_15:3;
1592         uint64_t xsdef:1;
1593         uint64_t reserved_9_11:3;
1594         uint64_t xscol:1;
1595         uint64_t reserved_3_7:5;
1596         uint64_t undflw:1;
1597         uint64_t reserved_1_1:1;
1598         uint64_t pko_nxa:1;
1599 #else
1600         uint64_t pko_nxa:1;
1601         uint64_t reserved_1_1:1;
1602         uint64_t undflw:1;
1603         uint64_t reserved_3_7:5;
1604         uint64_t xscol:1;
1605         uint64_t reserved_9_11:3;
1606         uint64_t xsdef:1;
1607         uint64_t reserved_13_15:3;
1608         uint64_t late_col:1;
1609         uint64_t reserved_17_63:47;
1610 #endif
1611     } cn56xx;
1612 };
1613 
1614 union cvmx_agl_gmx_tx_jam {
1615     uint64_t u64;
1616     struct cvmx_agl_gmx_tx_jam_s {
1617 #ifdef __BIG_ENDIAN_BITFIELD
1618         uint64_t reserved_8_63:56;
1619         uint64_t jam:8;
1620 #else
1621         uint64_t jam:8;
1622         uint64_t reserved_8_63:56;
1623 #endif
1624     } s;
1625 };
1626 
1627 union cvmx_agl_gmx_tx_lfsr {
1628     uint64_t u64;
1629     struct cvmx_agl_gmx_tx_lfsr_s {
1630 #ifdef __BIG_ENDIAN_BITFIELD
1631         uint64_t reserved_16_63:48;
1632         uint64_t lfsr:16;
1633 #else
1634         uint64_t lfsr:16;
1635         uint64_t reserved_16_63:48;
1636 #endif
1637     } s;
1638 };
1639 
1640 union cvmx_agl_gmx_tx_ovr_bp {
1641     uint64_t u64;
1642     struct cvmx_agl_gmx_tx_ovr_bp_s {
1643 #ifdef __BIG_ENDIAN_BITFIELD
1644         uint64_t reserved_10_63:54;
1645         uint64_t en:2;
1646         uint64_t reserved_6_7:2;
1647         uint64_t bp:2;
1648         uint64_t reserved_2_3:2;
1649         uint64_t ign_full:2;
1650 #else
1651         uint64_t ign_full:2;
1652         uint64_t reserved_2_3:2;
1653         uint64_t bp:2;
1654         uint64_t reserved_6_7:2;
1655         uint64_t en:2;
1656         uint64_t reserved_10_63:54;
1657 #endif
1658     } s;
1659     struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1660 #ifdef __BIG_ENDIAN_BITFIELD
1661         uint64_t reserved_9_63:55;
1662         uint64_t en:1;
1663         uint64_t reserved_5_7:3;
1664         uint64_t bp:1;
1665         uint64_t reserved_1_3:3;
1666         uint64_t ign_full:1;
1667 #else
1668         uint64_t ign_full:1;
1669         uint64_t reserved_1_3:3;
1670         uint64_t bp:1;
1671         uint64_t reserved_5_7:3;
1672         uint64_t en:1;
1673         uint64_t reserved_9_63:55;
1674 #endif
1675     } cn56xx;
1676 };
1677 
1678 union cvmx_agl_gmx_tx_pause_pkt_dmac {
1679     uint64_t u64;
1680     struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1681 #ifdef __BIG_ENDIAN_BITFIELD
1682         uint64_t reserved_48_63:16;
1683         uint64_t dmac:48;
1684 #else
1685         uint64_t dmac:48;
1686         uint64_t reserved_48_63:16;
1687 #endif
1688     } s;
1689 };
1690 
1691 union cvmx_agl_gmx_tx_pause_pkt_type {
1692     uint64_t u64;
1693     struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1694 #ifdef __BIG_ENDIAN_BITFIELD
1695         uint64_t reserved_16_63:48;
1696         uint64_t type:16;
1697 #else
1698         uint64_t type:16;
1699         uint64_t reserved_16_63:48;
1700 #endif
1701     } s;
1702 };
1703 
1704 union cvmx_agl_prtx_ctl {
1705     uint64_t u64;
1706     struct cvmx_agl_prtx_ctl_s {
1707 #ifdef __BIG_ENDIAN_BITFIELD
1708         uint64_t drv_byp:1;
1709         uint64_t reserved_62_62:1;
1710         uint64_t cmp_pctl:6;
1711         uint64_t reserved_54_55:2;
1712         uint64_t cmp_nctl:6;
1713         uint64_t reserved_46_47:2;
1714         uint64_t drv_pctl:6;
1715         uint64_t reserved_38_39:2;
1716         uint64_t drv_nctl:6;
1717         uint64_t reserved_29_31:3;
1718         uint64_t clk_set:5;
1719         uint64_t clkrx_byp:1;
1720         uint64_t reserved_21_22:2;
1721         uint64_t clkrx_set:5;
1722         uint64_t clktx_byp:1;
1723         uint64_t reserved_13_14:2;
1724         uint64_t clktx_set:5;
1725         uint64_t reserved_5_7:3;
1726         uint64_t dllrst:1;
1727         uint64_t comp:1;
1728         uint64_t enable:1;
1729         uint64_t clkrst:1;
1730         uint64_t mode:1;
1731 #else
1732         uint64_t mode:1;
1733         uint64_t clkrst:1;
1734         uint64_t enable:1;
1735         uint64_t comp:1;
1736         uint64_t dllrst:1;
1737         uint64_t reserved_5_7:3;
1738         uint64_t clktx_set:5;
1739         uint64_t reserved_13_14:2;
1740         uint64_t clktx_byp:1;
1741         uint64_t clkrx_set:5;
1742         uint64_t reserved_21_22:2;
1743         uint64_t clkrx_byp:1;
1744         uint64_t clk_set:5;
1745         uint64_t reserved_29_31:3;
1746         uint64_t drv_nctl:6;
1747         uint64_t reserved_38_39:2;
1748         uint64_t drv_pctl:6;
1749         uint64_t reserved_46_47:2;
1750         uint64_t cmp_nctl:6;
1751         uint64_t reserved_54_55:2;
1752         uint64_t cmp_pctl:6;
1753         uint64_t reserved_62_62:1;
1754         uint64_t drv_byp:1;
1755 #endif
1756     } s;
1757 };
1758 
1759 #endif
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