asm/octeon/cvmx-address.h

0001 /***********************license start***************
0002  * Author: Cavium Networks
0003  *
0004  * Contact: support@caviumnetworks.com
0005  * This file is part of the OCTEON SDK
0006  *
0007  * Copyright (c) 2003-2009 Cavium Networks
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  *
0019  * You should have received a copy of the GNU General Public License
0020  * along with this file; if not, write to the Free Software
0021  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
0022  * or visit http://www.gnu.org/licenses/.
0023  *
0024  * This file may also be available under a different license from Cavium.
0025  * Contact Cavium Networks for more information
0026  ***********************license end**************************************/
0027
0028 /**
0029  * Typedefs and defines for working with Octeon physical addresses.
0030  *
0031  */
0032 #ifndef __CVMX_ADDRESS_H__
0033 #define __CVMX_ADDRESS_H__
0034
0035 #if 0
0036 typedef enum {
0037     CVMX_MIPS_SPACE_XKSEG = 3LL,
0038     CVMX_MIPS_SPACE_XKPHYS = 2LL,
0039     CVMX_MIPS_SPACE_XSSEG = 1LL,
0040     CVMX_MIPS_SPACE_XUSEG = 0LL
0041 } cvmx_mips_space_t;
0042 #endif
0043
0044 typedef enum {
0045     CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
0046     CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
0047     CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
0048     CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
0049 } cvmx_mips_xkseg_space_t;
0050
0051 /* decodes <14:13> of a kseg3 window address */
0052 typedef enum {
0053     CVMX_ADD_WIN_SCR = 0L,
0054     /* see cvmx_add_win_dma_dec_t for further decode */
0055     CVMX_ADD_WIN_DMA = 1L,
0056     CVMX_ADD_WIN_UNUSED = 2L,
0057     CVMX_ADD_WIN_UNUSED2 = 3L
0058 } cvmx_add_win_dec_t;
0059
0060 /* decode within DMA space */
0061 typedef enum {
0062     /*
0063      * Add store data to the write buffer entry, allocating it if
0064      * necessary.
0065      */
0066     CVMX_ADD_WIN_DMA_ADD = 0L,
0067     /* send out the write buffer entry to DRAM */
0068     CVMX_ADD_WIN_DMA_SENDMEM = 1L,
0069     /* store data must be normal DRAM memory space address in this case */
0070     /* send out the write buffer entry as an IOBDMA command */
0071     CVMX_ADD_WIN_DMA_SENDDMA = 2L,
0072     /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
0073     /* send out the write buffer entry as an IO write */
0074     CVMX_ADD_WIN_DMA_SENDIO = 3L,
0075     /* store data must be normal IO space address in this case */
0076     /* send out a single-tick command on the NCB bus */
0077     CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
0078     /* no write buffer data needed/used */
0079 } cvmx_add_win_dma_dec_t;
0080
0081 /*
0082  *   Physical Address Decode
0083  *
0084  * Octeon-I HW never interprets this X (<39:36> reserved
0085  * for future expansion), software should set to 0.
0086  *
0087  *  - 0x0 XXX0 0000 0000 to  DRAM         Cached
0088  *  - 0x0 XXX0 0FFF FFFF
0089  *
0090  *  - 0x0 XXX0 1000 0000 to  Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
0091  *  - 0x0 XXX0 1FFF FFFF     + EJTAG               to 0x1 00X0 1FFF FFFF)
0092  *
0093  *  - 0x0 XXX0 2000 0000 to  DRAM         Cached
0094  *  - 0x0 XXXF FFFF FFFF
0095  *
0096  *  - 0x1 00X0 0000 0000 to  Boot Bus     Uncached
0097  *  - 0x1 00XF FFFF FFFF
0098  *
0099  *  - 0x1 01X0 0000 0000 to  Other NCB    Uncached
0100  *  - 0x1 FFXF FFFF FFFF     devices
0101  *
0102  * Decode of all Octeon addresses
0103  */
0104 typedef union {
0105
0106     uint64_t u64;
0107 #ifdef __BIG_ENDIAN_BITFIELD
0108     /* mapped or unmapped virtual address */
0109     struct {
0110         uint64_t R:2;
0111         uint64_t offset:62;
0112     } sva;
0113
0114     /* mapped USEG virtual addresses (typically) */
0115     struct {
0116         uint64_t zeroes:33;
0117         uint64_t offset:31;
0118     } suseg;
0119
0120     /* mapped or unmapped virtual address */
0121     struct {
0122         uint64_t ones:33;
0123         uint64_t sp:2;
0124         uint64_t offset:29;
0125     } sxkseg;
0126
0127     /*
0128      * physical address accessed through xkphys unmapped virtual
0129      * address.
0130      */
0131     struct {
0132         uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */
0133         uint64_t cca:3; /* ignored by octeon */
0134         uint64_t mbz:10;
0135         uint64_t pa:49; /* physical address */
0136     } sxkphys;
0137
0138     /* physical address */
0139     struct {
0140         uint64_t mbz:15;
0141         /* if set, the address is uncached and resides on MCB bus */
0142         uint64_t is_io:1;
0143         /*
0144          * the hardware ignores this field when is_io==0, else
0145          * device ID.
0146          */
0147         uint64_t did:8;
0148         /* the hardware ignores <39:36> in Octeon I */
0149         uint64_t unaddr:4;
0150         uint64_t offset:36;
0151     } sphys;
0152
0153     /* physical mem address */
0154     struct {
0155         /* technically, <47:40> are dont-cares */
0156         uint64_t zeroes:24;
0157         /* the hardware ignores <39:36> in Octeon I */
0158         uint64_t unaddr:4;
0159         uint64_t offset:36;
0160     } smem;
0161
0162     /* physical IO address */
0163     struct {
0164         uint64_t mem_region:2;
0165         uint64_t mbz:13;
0166         /* 1 in this case */
0167         uint64_t is_io:1;
0168         /*
0169          * The hardware ignores this field when is_io==0, else
0170          * device ID.
0171          */
0172         uint64_t did:8;
0173         /* the hardware ignores <39:36> in Octeon I */
0174         uint64_t unaddr:4;
0175         uint64_t offset:36;
0176     } sio;
0177
0178     /*
0179      * Scratchpad virtual address - accessed through a window at
0180      * the end of kseg3
0181      */
0182     struct {
0183         uint64_t ones:49;
0184         /* CVMX_ADD_WIN_SCR (0) in this case */
0185         cvmx_add_win_dec_t csrdec:2;
0186         uint64_t addr:13;
0187     } sscr;
0188
0189     /* there should only be stores to IOBDMA space, no loads */
0190     /*
0191      * IOBDMA virtual address - accessed through a window at the
0192      * end of kseg3
0193      */
0194     struct {
0195         uint64_t ones:49;
0196         uint64_t csrdec:2;  /* CVMX_ADD_WIN_DMA (1) in this case */
0197         uint64_t unused2:3;
0198         uint64_t type:3;
0199         uint64_t addr:7;
0200     } sdma;
0201
0202     struct {
0203         uint64_t didspace:24;
0204         uint64_t unused:40;
0205     } sfilldidspace;
0206 #else
0207     struct {
0208         uint64_t offset:62;
0209         uint64_t R:2;
0210     } sva;
0211
0212     struct {
0213         uint64_t offset:31;
0214         uint64_t zeroes:33;
0215     } suseg;
0216
0217     struct {
0218         uint64_t offset:29;
0219         uint64_t sp:2;
0220         uint64_t ones:33;
0221     } sxkseg;
0222
0223     struct {
0224         uint64_t pa:49;
0225         uint64_t mbz:10;
0226         uint64_t cca:3;
0227         uint64_t R:2;
0228     } sxkphys;
0229
0230     struct {
0231         uint64_t offset:36;
0232         uint64_t unaddr:4;
0233         uint64_t did:8;
0234         uint64_t is_io:1;
0235         uint64_t mbz:15;
0236     } sphys;
0237
0238     struct {
0239         uint64_t offset:36;
0240         uint64_t unaddr:4;
0241         uint64_t zeroes:24;
0242     } smem;
0243
0244     struct {
0245         uint64_t offset:36;
0246         uint64_t unaddr:4;
0247         uint64_t did:8;
0248         uint64_t is_io:1;
0249         uint64_t mbz:13;
0250         uint64_t mem_region:2;
0251     } sio;
0252
0253     struct {
0254         uint64_t addr:13;
0255         cvmx_add_win_dec_t csrdec:2;
0256         uint64_t ones:49;
0257     } sscr;
0258
0259     struct {
0260         uint64_t addr:7;
0261         uint64_t type:3;
0262         uint64_t unused2:3;
0263         uint64_t csrdec:2;
0264         uint64_t ones:49;
0265     } sdma;
0266
0267     struct {
0268         uint64_t unused:40;
0269         uint64_t didspace:24;
0270     } sfilldidspace;
0271 #endif
0272
0273 } cvmx_addr_t;
0274
0275 /* These macros for used by 32 bit applications */
0276
0277 #define CVMX_MIPS32_SPACE_KSEG0 1l
0278 #define CVMX_ADD_SEG32(segment, add) \
0279     (((int32_t)segment << 31) | (int32_t)(add))
0280
0281 /*
0282  * Currently all IOs are performed using XKPHYS addressing. Linux uses
0283  * the CvmMemCtl register to enable XKPHYS addressing to IO space from
0284  * user mode.  Future OSes may need to change the upper bits of IO
0285  * addresses. The following define controls the upper two bits for all
0286  * IO addresses generated by the simple executive library.
0287  */
0288 #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
0289
0290 /* These macros simplify the process of creating common IO addresses */
0291 #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
0292 #ifndef CVMX_ADD_IO_SEG
0293 #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
0294 #endif
0295 #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
0296 #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
0297 #define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
0298
0299   /* from include/ncb_rsl_id.v */
0300 #define CVMX_OCT_DID_MIS 0ULL   /* misc stuff */
0301 #define CVMX_OCT_DID_GMX0 1ULL
0302 #define CVMX_OCT_DID_GMX1 2ULL
0303 #define CVMX_OCT_DID_PCI 3ULL
0304 #define CVMX_OCT_DID_KEY 4ULL
0305 #define CVMX_OCT_DID_FPA 5ULL
0306 #define CVMX_OCT_DID_DFA 6ULL
0307 #define CVMX_OCT_DID_ZIP 7ULL
0308 #define CVMX_OCT_DID_RNG 8ULL
0309 #define CVMX_OCT_DID_IPD 9ULL
0310 #define CVMX_OCT_DID_PKT 10ULL
0311 #define CVMX_OCT_DID_TIM 11ULL
0312 #define CVMX_OCT_DID_TAG 12ULL
0313   /* the rest are not on the IO bus */
0314 #define CVMX_OCT_DID_L2C 16ULL
0315 #define CVMX_OCT_DID_LMC 17ULL
0316 #define CVMX_OCT_DID_SPX0 18ULL
0317 #define CVMX_OCT_DID_SPX1 19ULL
0318 #define CVMX_OCT_DID_PIP 20ULL
0319 #define CVMX_OCT_DID_ASX0 22ULL
0320 #define CVMX_OCT_DID_ASX1 23ULL
0321 #define CVMX_OCT_DID_IOB 30ULL
0322
0323 #define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
0324 #define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
0325 #define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
0326 #define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
0327 #define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
0328 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
0329 #define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
0330 #define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
0331 #define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
0332 #define CVMX_OCT_DID_KEY_RW     CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
0333 #define CVMX_OCT_DID_PCI_6      CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
0334 #define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
0335 #define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
0336 #define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
0337 #define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
0338 #define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
0339 #define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
0340
0341 #endif /* __CVMX_ADDRESS_H__ */