include/asm/msc01_ic.h

0001 /*
0002  * PCI Register definitions for the MIPS System Controller.
0003  *
0004  * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file "COPYING" in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
0012 #define __ASM_MIPS_BOARDS_MSC01_IC_H
0013
0014 /*****************************************************************************
0015  * Register offset addresses
0016  *****************************************************************************/
0017
0018 #define MSC01_IC_RST_OFS     0x00008    /* Software reset          */
0019 #define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
0020 #define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
0021 #define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
0022 #define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
0023 #define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0         */
0024 #define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32        */
0025 #define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
0026 #define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
0027 #define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
0028 #define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)         */
0029 #define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out             */
0030 #define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out          */
0031 #define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
0032 #define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
0033 #define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
0034 #define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
0035 #define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
0036 #define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
0037 #define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
0038 #define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
0039 #define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
0040 #define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
0041 #define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
0042 #define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0         */
0043 #define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
0044
0045 /*****************************************************************************
0046  * Register field encodings
0047  *****************************************************************************/
0048
0049 #define MSC01_IC_RST_RST_SHF      0
0050 #define MSC01_IC_RST_RST_MSK      0x00000001
0051 #define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
0052 #define MSC01_IC_LVL_LVL_SHF      0
0053 #define MSC01_IC_LVL_LVL_MSK      0x000000ff
0054 #define MSC01_IC_LVL_SPUR_SHF     16
0055 #define MSC01_IC_LVL_SPUR_MSK     0x00010000
0056 #define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
0057 #define MSC01_IC_RAMW_RIPL_SHF    0
0058 #define MSC01_IC_RAMW_RIPL_MSK    0x0000003f
0059 #define MSC01_IC_RAMW_DATA_SHF    6
0060 #define MSC01_IC_RAMW_DATA_MSK    0x00000fc0
0061 #define MSC01_IC_RAMW_ADDR_SHF    25
0062 #define MSC01_IC_RAMW_ADDR_MSK    0x7e000000
0063 #define MSC01_IC_RAMW_READ_SHF    31
0064 #define MSC01_IC_RAMW_READ_MSK    0x80000000
0065 #define MSC01_IC_RAMW_READ_BIT    MSC01_IC_RAMW_READ_MSK
0066 #define MSC01_IC_OSB_OSB_SHF      0
0067 #define MSC01_IC_OSB_OSB_MSK      0x000000ff
0068 #define MSC01_IC_OSA_OSA_SHF      0
0069 #define MSC01_IC_OSA_OSA_MSK      0x000000ff
0070 #define MSC01_IC_GENA_GENA_SHF    0
0071 #define MSC01_IC_GENA_GENA_MSK    0x00000001
0072 #define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
0073 #define MSC01_IC_CFG_DIS_SHF      0
0074 #define MSC01_IC_CFG_DIS_MSK      0x00000001
0075 #define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
0076 #define MSC01_IC_CFG_SHFT_SHF     8
0077 #define MSC01_IC_CFG_SHFT_MSK     0x00000f00
0078 #define MSC01_IC_TCFG_ENA_SHF     0
0079 #define MSC01_IC_TCFG_ENA_MSK     0x00000001
0080 #define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
0081 #define MSC01_IC_TCFG_INT_SHF     8
0082 #define MSC01_IC_TCFG_INT_MSK     0x00000100
0083 #define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
0084 #define MSC01_IC_TCFG_EDGE_SHF    16
0085 #define MSC01_IC_TCFG_EDGE_MSK    0x00010000
0086 #define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
0087 #define MSC01_IC_SUP_PRI_SHF      0
0088 #define MSC01_IC_SUP_PRI_MSK      0x00000007
0089 #define MSC01_IC_SUP_EDGE_SHF     8
0090 #define MSC01_IC_SUP_EDGE_MSK     0x00000100
0091 #define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
0092 #define MSC01_IC_SUP_STEP     8
0093
0094 /*
0095  * MIPS System controller interrupt register base.
0096  *
0097  */
0098
0099 /*****************************************************************************
0100  * Absolute register addresses
0101  *****************************************************************************/
0102
0103 #define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
0104 #define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
0105 #define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
0106 #define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
0107 #define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
0108 #define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
0109 #define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
0110 #define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
0111 #define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
0112 #define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
0113 #define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
0114 #define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
0115 #define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
0116 #define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
0117 #define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
0118 #define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
0119 #define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
0120 #define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
0121 #define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
0122 #define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
0123 #define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
0124 #define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
0125 #define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
0126 #define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
0127 #define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
0128 #define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
0129
0130 /*
0131  * Soc-it interrupts are configurable.
0132  * Every board describes its IRQ mapping with this table.
0133  */
0134 typedef struct msc_irqmap {
0135     int im_irq;
0136     int im_type;
0137     int im_lvl;
0138 } msc_irqmap_t;
0139
0140 /* im_type */
0141 #define MSC01_IRQ_LEVEL     0
0142 #define MSC01_IRQ_EDGE      1
0143
0144 extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
0145 extern void ll_msc_irq(void);
0146
0147 #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */