include/asm/mipsmtregs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * MT regs definitions, follows on from mipsregs.h
0004  * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
0005  * Elizabeth Clarke et. al.
0006  *
0007  */
0008 #ifndef _ASM_MIPSMTREGS_H
0009 #define _ASM_MIPSMTREGS_H
0010
0011 #include <asm/mipsregs.h>
0012
0013 #ifndef __ASSEMBLY__
0014
0015 /*
0016  * C macros
0017  */
0018
0019 #define read_c0_mvpcontrol()        __read_32bit_c0_register($0, 1)
0020 #define write_c0_mvpcontrol(val)    __write_32bit_c0_register($0, 1, val)
0021
0022 #define read_c0_mvpconf0()      __read_32bit_c0_register($0, 2)
0023 #define read_c0_mvpconf1()      __read_32bit_c0_register($0, 3)
0024
0025 #define read_c0_vpecontrol()        __read_32bit_c0_register($1, 1)
0026 #define write_c0_vpecontrol(val)    __write_32bit_c0_register($1, 1, val)
0027
0028 #define read_c0_vpeconf0()      __read_32bit_c0_register($1, 2)
0029 #define write_c0_vpeconf0(val)      __write_32bit_c0_register($1, 2, val)
0030
0031 #define read_c0_vpeconf1()      __read_32bit_c0_register($1, 3)
0032 #define write_c0_vpeconf1(val)      __write_32bit_c0_register($1, 3, val)
0033
0034 #define read_c0_tcstatus()      __read_32bit_c0_register($2, 1)
0035 #define write_c0_tcstatus(val)      __write_32bit_c0_register($2, 1, val)
0036
0037 #define read_c0_tcbind()        __read_32bit_c0_register($2, 2)
0038
0039 #define write_c0_tchalt(val)        __write_32bit_c0_register($2, 4, val)
0040
0041 #define read_c0_tccontext()     __read_32bit_c0_register($2, 5)
0042 #define write_c0_tccontext(val)     __write_32bit_c0_register($2, 5, val)
0043
0044 #else /* Assembly */
0045 /*
0046  * Macros for use in assembly language code
0047  */
0048
0049 #define CP0_MVPCONTROL      $0, 1
0050 #define CP0_MVPCONF0        $0, 2
0051 #define CP0_MVPCONF1        $0, 3
0052 #define CP0_VPECONTROL      $1, 1
0053 #define CP0_VPECONF0        $1, 2
0054 #define CP0_VPECONF1        $1, 3
0055 #define CP0_YQMASK      $1, 4
0056 #define CP0_VPESCHEDULE     $1, 5
0057 #define CP0_VPESCHEFBK      $1, 6
0058 #define CP0_TCSTATUS        $2, 1
0059 #define CP0_TCBIND      $2, 2
0060 #define CP0_TCRESTART       $2, 3
0061 #define CP0_TCHALT      $2, 4
0062 #define CP0_TCCONTEXT       $2, 5
0063 #define CP0_TCSCHEDULE      $2, 6
0064 #define CP0_TCSCHEFBK       $2, 7
0065 #define CP0_SRSCONF0        $6, 1
0066 #define CP0_SRSCONF1        $6, 2
0067 #define CP0_SRSCONF2        $6, 3
0068 #define CP0_SRSCONF3        $6, 4
0069 #define CP0_SRSCONF4        $6, 5
0070
0071 #endif
0072
0073 /* MVPControl fields */
0074 #define MVPCONTROL_EVP      (_ULCAST_(1))
0075
0076 #define MVPCONTROL_VPC_SHIFT    1
0077 #define MVPCONTROL_VPC      (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
0078
0079 #define MVPCONTROL_STLB_SHIFT   2
0080 #define MVPCONTROL_STLB     (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
0081
0082
0083 /* MVPConf0 fields */
0084 #define MVPCONF0_PTC_SHIFT  0
0085 #define MVPCONF0_PTC        ( _ULCAST_(0xff))
0086 #define MVPCONF0_PVPE_SHIFT 10
0087 #define MVPCONF0_PVPE       ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
0088 #define MVPCONF0_TCA_SHIFT  15
0089 #define MVPCONF0_TCA        ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
0090 #define MVPCONF0_PTLBE_SHIFT    16
0091 #define MVPCONF0_PTLBE      (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
0092 #define MVPCONF0_TLBS_SHIFT 29
0093 #define MVPCONF0_TLBS       (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
0094 #define MVPCONF0_M_SHIFT    31
0095 #define MVPCONF0_M      (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
0096
0097
0098 /* config3 fields */
0099 #define CONFIG3_MT_SHIFT    2
0100 #define CONFIG3_MT      (_ULCAST_(1) << CONFIG3_MT_SHIFT)
0101
0102
0103 /* VPEControl fields (per VPE) */
0104 #define VPECONTROL_TARGTC   (_ULCAST_(0xff))
0105
0106 #define VPECONTROL_TE_SHIFT 15
0107 #define VPECONTROL_TE       (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
0108 #define VPECONTROL_EXCPT_SHIFT  16
0109 #define VPECONTROL_EXCPT    (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
0110
0111 /* Thread Exception Codes for EXCPT field */
0112 #define THREX_TU        0
0113 #define THREX_TO        1
0114 #define THREX_IYQ       2
0115 #define THREX_GSX       3
0116 #define THREX_YSCH      4
0117 #define THREX_GSSCH     5
0118
0119 #define VPECONTROL_GSI_SHIFT    20
0120 #define VPECONTROL_GSI      (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
0121 #define VPECONTROL_YSI_SHIFT    21
0122 #define VPECONTROL_YSI      (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
0123
0124 /* VPEConf0 fields (per VPE) */
0125 #define VPECONF0_VPA_SHIFT  0
0126 #define VPECONF0_VPA        (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
0127 #define VPECONF0_MVP_SHIFT  1
0128 #define VPECONF0_MVP        (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
0129 #define VPECONF0_XTC_SHIFT  21
0130 #define VPECONF0_XTC        (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
0131
0132 /* VPEConf1 fields (per VPE) */
0133 #define VPECONF1_NCP1_SHIFT 0
0134 #define VPECONF1_NCP1       (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
0135 #define VPECONF1_NCP2_SHIFT 10
0136 #define VPECONF1_NCP2       (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
0137 #define VPECONF1_NCX_SHIFT  20
0138 #define VPECONF1_NCX        (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
0139
0140 /* TCStatus fields (per TC) */
0141 #define TCSTATUS_TASID      (_ULCAST_(0xff))
0142 #define TCSTATUS_IXMT_SHIFT 10
0143 #define TCSTATUS_IXMT       (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
0144 #define TCSTATUS_TKSU_SHIFT 11
0145 #define TCSTATUS_TKSU       (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
0146 #define TCSTATUS_A_SHIFT    13
0147 #define TCSTATUS_A      (_ULCAST_(1) << TCSTATUS_A_SHIFT)
0148 #define TCSTATUS_DA_SHIFT   15
0149 #define TCSTATUS_DA     (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
0150 #define TCSTATUS_DT_SHIFT   20
0151 #define TCSTATUS_DT     (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
0152 #define TCSTATUS_TDS_SHIFT  21
0153 #define TCSTATUS_TDS        (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
0154 #define TCSTATUS_TSST_SHIFT 22
0155 #define TCSTATUS_TSST       (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
0156 #define TCSTATUS_RNST_SHIFT 23
0157 #define TCSTATUS_RNST       (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
0158 /* Codes for RNST */
0159 #define TC_RUNNING      0
0160 #define TC_WAITING      1
0161 #define TC_YIELDING     2
0162 #define TC_GATED        3
0163
0164 #define TCSTATUS_TMX_SHIFT  27
0165 #define TCSTATUS_TMX        (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
0166 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
0167
0168 /* TCBind */
0169 #define TCBIND_CURVPE_SHIFT 0
0170 #define TCBIND_CURVPE       (_ULCAST_(0xf))
0171
0172 #define TCBIND_CURTC_SHIFT  21
0173
0174 #define TCBIND_CURTC        (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
0175
0176 /* TCHalt */
0177 #define TCHALT_H        (_ULCAST_(1))
0178
0179 #ifndef __ASSEMBLY__
0180
0181 static inline unsigned core_nvpes(void)
0182 {
0183     unsigned conf0;
0184
0185     if (!cpu_has_mipsmt)
0186         return 1;
0187
0188     conf0 = read_c0_mvpconf0();
0189     return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
0190 }
0191
0192 static inline unsigned int dvpe(void)
0193 {
0194     int res = 0;
0195
0196     __asm__ __volatile__(
0197     "   .set    push                        \n"
0198     "   .set    noreorder                   \n"
0199     "   .set    noat                        \n"
0200     "   .set    mips32r2                    \n"
0201     "   .word   0x41610001      # dvpe $1       \n"
0202     "   move    %0, $1                      \n"
0203     "   ehb                         \n"
0204     "   .set    pop                     \n"
0205     : "=r" (res));
0206
0207     instruction_hazard();
0208
0209     return res;
0210 }
0211
0212 static inline void __raw_evpe(void)
0213 {
0214     __asm__ __volatile__(
0215     "   .set    push                        \n"
0216     "   .set    noreorder                   \n"
0217     "   .set    noat                        \n"
0218     "   .set    mips32r2                    \n"
0219     "   .word   0x41600021      # evpe          \n"
0220     "   ehb                         \n"
0221     "   .set    pop                     \n");
0222 }
0223
0224 /* Enable virtual processor execution if previous suggested it should be.
0225    EVPE_ENABLE to force */
0226
0227 #define EVPE_ENABLE MVPCONTROL_EVP
0228
0229 static inline void evpe(int previous)
0230 {
0231     if ((previous & MVPCONTROL_EVP))
0232         __raw_evpe();
0233 }
0234
0235 static inline unsigned int dmt(void)
0236 {
0237     int res;
0238
0239     __asm__ __volatile__(
0240     "   .set    push                        \n"
0241     "   .set    mips32r2                    \n"
0242     "   .set    noat                        \n"
0243     "   .word   0x41610BC1          # dmt $1    \n"
0244     "   ehb                         \n"
0245     "   move    %0, $1                      \n"
0246     "   .set    pop                     \n"
0247     : "=r" (res));
0248
0249     instruction_hazard();
0250
0251     return res;
0252 }
0253
0254 static inline void __raw_emt(void)
0255 {
0256     __asm__ __volatile__(
0257     "   .set    push                        \n"
0258     "   .set    noreorder                   \n"
0259     "   .set    mips32r2                    \n"
0260     "   .word   0x41600be1          # emt       \n"
0261     "   ehb                         \n"
0262     "   .set    pop");
0263 }
0264
0265 /* enable multi-threaded execution if previous suggested it should be.
0266    EMT_ENABLE to force */
0267
0268 #define EMT_ENABLE VPECONTROL_TE
0269
0270 static inline void emt(int previous)
0271 {
0272     if ((previous & EMT_ENABLE))
0273         __raw_emt();
0274 }
0275
0276 static inline void ehb(void)
0277 {
0278     __asm__ __volatile__(
0279     "   .set    push                    \n"
0280     "   .set    mips32r2                \n"
0281     "   ehb                     \n"
0282     "   .set    pop                 \n");
0283 }
0284
0285 #define mftc0(rt,sel)                           \
0286 ({                                  \
0287      unsigned long  __res;                      \
0288                                     \
0289     __asm__ __volatile__(                       \
0290     "   .set    push                    \n" \
0291     "   .set    mips32r2                \n" \
0292     "   .set    noat                    \n" \
0293     "   # mftc0 $1, $" #rt ", " #sel "          \n" \
0294     "   .word   0x41000800 | (" #rt " << 16) | " #sel " \n" \
0295     "   move    %0, $1                  \n" \
0296     "   .set    pop                 \n" \
0297     : "=r" (__res));                        \
0298                                     \
0299     __res;                              \
0300 })
0301
0302 #define mftgpr(rt)                          \
0303 ({                                  \
0304     unsigned long __res;                        \
0305                                     \
0306     __asm__ __volatile__(                       \
0307     "   .set    push                    \n" \
0308     "   .set    noat                    \n" \
0309     "   .set    mips32r2                \n" \
0310     "   # mftgpr $1," #rt "             \n" \
0311     "   .word   0x41000820 | (" #rt " << 16)        \n" \
0312     "   move    %0, $1                  \n" \
0313     "   .set    pop                 \n" \
0314     : "=r" (__res));                        \
0315                                     \
0316     __res;                              \
0317 })
0318
0319 #define mftr(rt, u, sel)                            \
0320 ({                                  \
0321     unsigned long __res;                        \
0322                                     \
0323     __asm__ __volatile__(                       \
0324     "   mftr    %0, " #rt ", " #u ", " #sel "       \n" \
0325     : "=r" (__res));                        \
0326                                     \
0327     __res;                              \
0328 })
0329
0330 #define mttgpr(rd,v)                            \
0331 do {                                    \
0332     __asm__ __volatile__(                       \
0333     "   .set    push                    \n" \
0334     "   .set    mips32r2                \n" \
0335     "   .set    noat                    \n" \
0336     "   move    $1, %0                  \n" \
0337     "   # mttgpr $1, " #rd "                \n" \
0338     "   .word   0x41810020 | (" #rd " << 11)        \n" \
0339     "   .set    pop                 \n" \
0340     : : "r" (v));                           \
0341 } while (0)
0342
0343 #define mttc0(rd, sel, v)                           \
0344 ({                                  \
0345     __asm__ __volatile__(                       \
0346     "   .set    push                    \n" \
0347     "   .set    mips32r2                \n" \
0348     "   .set    noat                    \n" \
0349     "   move    $1, %0                  \n" \
0350     "   # mttc0 %0," #rd ", " #sel "            \n" \
0351     "   .word   0x41810000 | (" #rd " << 11) | " #sel " \n" \
0352     "   .set    pop                 \n" \
0353     :                               \
0354     : "r" (v));                         \
0355 })
0356
0357
0358 #define mttr(rd, u, sel, v)                     \
0359 ({                                  \
0360     __asm__ __volatile__(                       \
0361     "mttr   %0," #rd ", " #u ", " #sel              \
0362     : : "r" (v));                           \
0363 })
0364
0365
0366 #define settc(tc)                           \
0367 do {                                    \
0368     write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
0369     ehb();                              \
0370 } while (0)
0371
0372
0373 /* you *must* set the target tc (settc) before trying to use these */
0374 #define read_vpe_c0_vpecontrol()    mftc0(1, 1)
0375 #define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
0376 #define read_vpe_c0_vpeconf0()      mftc0(1, 2)
0377 #define write_vpe_c0_vpeconf0(val)  mttc0(1, 2, val)
0378 #define read_vpe_c0_vpeconf1()      mftc0(1, 3)
0379 #define write_vpe_c0_vpeconf1(val)  mttc0(1, 3, val)
0380 #define read_vpe_c0_count()     mftc0(9, 0)
0381 #define write_vpe_c0_count(val)     mttc0(9, 0, val)
0382 #define read_vpe_c0_status()        mftc0(12, 0)
0383 #define write_vpe_c0_status(val)    mttc0(12, 0, val)
0384 #define read_vpe_c0_cause()     mftc0(13, 0)
0385 #define write_vpe_c0_cause(val)     mttc0(13, 0, val)
0386 #define read_vpe_c0_config()        mftc0(16, 0)
0387 #define write_vpe_c0_config(val)    mttc0(16, 0, val)
0388 #define read_vpe_c0_config1()       mftc0(16, 1)
0389 #define write_vpe_c0_config1(val)   mttc0(16, 1, val)
0390 #define read_vpe_c0_config7()       mftc0(16, 7)
0391 #define write_vpe_c0_config7(val)   mttc0(16, 7, val)
0392 #define read_vpe_c0_ebase()     mftc0(15, 1)
0393 #define write_vpe_c0_ebase(val)     mttc0(15, 1, val)
0394 #define write_vpe_c0_compare(val)   mttc0(11, 0, val)
0395 #define read_vpe_c0_badvaddr()      mftc0(8, 0)
0396 #define read_vpe_c0_epc()       mftc0(14, 0)
0397 #define write_vpe_c0_epc(val)       mttc0(14, 0, val)
0398
0399
0400 /* TC */
0401 #define read_tc_c0_tcstatus()       mftc0(2, 1)
0402 #define write_tc_c0_tcstatus(val)   mttc0(2, 1, val)
0403 #define read_tc_c0_tcbind()     mftc0(2, 2)
0404 #define write_tc_c0_tcbind(val)     mttc0(2, 2, val)
0405 #define read_tc_c0_tcrestart()      mftc0(2, 3)
0406 #define write_tc_c0_tcrestart(val)  mttc0(2, 3, val)
0407 #define read_tc_c0_tchalt()     mftc0(2, 4)
0408 #define write_tc_c0_tchalt(val)     mttc0(2, 4, val)
0409 #define read_tc_c0_tccontext()      mftc0(2, 5)
0410 #define write_tc_c0_tccontext(val)  mttc0(2, 5, val)
0411
0412 /* GPR */
0413 #define read_tc_gpr_sp()        mftgpr(29)
0414 #define write_tc_gpr_sp(val)        mttgpr(29, val)
0415 #define read_tc_gpr_gp()        mftgpr(28)
0416 #define write_tc_gpr_gp(val)        mttgpr(28, val)
0417
0418 __BUILD_SET_C0(mvpcontrol)
0419
0420 #endif /* Not __ASSEMBLY__ */
0421
0422 #endif