include/asm/mips-cpc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2013 Imagination Technologies
0004  * Author: Paul Burton <paul.burton@mips.com>
0005  */
0006
0007 #ifndef __MIPS_ASM_MIPS_CPS_H__
0008 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
0009 #endif
0010
0011 #ifndef __MIPS_ASM_MIPS_CPC_H__
0012 #define __MIPS_ASM_MIPS_CPC_H__
0013
0014 #include <linux/bitops.h>
0015 #include <linux/errno.h>
0016
0017 /* The base address of the CPC registers */
0018 extern void __iomem *mips_cpc_base;
0019
0020 /**
0021  * mips_cpc_default_phys_base - retrieve the default physical base address of
0022  *                              the CPC
0023  *
0024  * Returns the default physical base address of the Cluster Power Controller
0025  * memory mapped registers. This is platform dependant & must therefore be
0026  * implemented per-platform.
0027  */
0028 extern phys_addr_t mips_cpc_default_phys_base(void);
0029
0030 /**
0031  * mips_cpc_probe - probe for a Cluster Power Controller
0032  *
0033  * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
0034  * a CPC is successfully detected, else -errno.
0035  */
0036 #ifdef CONFIG_MIPS_CPC
0037 extern int mips_cpc_probe(void);
0038 #else
0039 static inline int mips_cpc_probe(void)
0040 {
0041     return -ENODEV;
0042 }
0043 #endif
0044
0045 /**
0046  * mips_cpc_present - determine whether a Cluster Power Controller is present
0047  *
0048  * Returns true if a CPC is present in the system, else false.
0049  */
0050 static inline bool mips_cpc_present(void)
0051 {
0052 #ifdef CONFIG_MIPS_CPC
0053     return mips_cpc_base != NULL;
0054 #else
0055     return false;
0056 #endif
0057 }
0058
0059 /* Offsets from the CPC base address to various control blocks */
0060 #define MIPS_CPC_GCB_OFS    0x0000
0061 #define MIPS_CPC_CLCB_OFS   0x2000
0062 #define MIPS_CPC_COCB_OFS   0x4000
0063
0064 #define CPC_ACCESSOR_RO(sz, off, name)                  \
0065     CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name)      \
0066     CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
0067
0068 #define CPC_ACCESSOR_RW(sz, off, name)                  \
0069     CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name)      \
0070     CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
0071
0072 #define CPC_CX_ACCESSOR_RO(sz, off, name)               \
0073     CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
0074     CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
0075
0076 #define CPC_CX_ACCESSOR_RW(sz, off, name)               \
0077     CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
0078     CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
0079
0080 /* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
0081 CPC_ACCESSOR_RW(32, 0x000, access)
0082
0083 /* CPC_SEQDEL - Configure delays between command sequencer steps */
0084 CPC_ACCESSOR_RW(32, 0x008, seqdel)
0085
0086 /* CPC_RAIL - Configure the delay from rail power-up to stability */
0087 CPC_ACCESSOR_RW(32, 0x010, rail)
0088
0089 /* CPC_RESETLEN - Configure the length of reset sequences */
0090 CPC_ACCESSOR_RW(32, 0x018, resetlen)
0091
0092 /* CPC_REVISION - Indicates the revisison of the CPC */
0093 CPC_ACCESSOR_RO(32, 0x020, revision)
0094
0095 /* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
0096 CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
0097 #define CPC_PWRUP_CTL_CM_PWRUP          BIT(0)
0098
0099 /* CPC_CONFIG - Mirrors GCR_CONFIG */
0100 CPC_ACCESSOR_RW(64, 0x138, config)
0101
0102 /* CPC_SYS_CONFIG - Control cluster endianness */
0103 CPC_ACCESSOR_RW(32, 0x140, sys_config)
0104 #define CPC_SYS_CONFIG_BE_IMMEDIATE     BIT(2)
0105 #define CPC_SYS_CONFIG_BE_STATUS        BIT(1)
0106 #define CPC_SYS_CONFIG_BE           BIT(0)
0107
0108 /* CPC_Cx_CMD - Instruct the CPC to take action on a core */
0109 CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
0110 #define CPC_Cx_CMD              GENMASK(3, 0)
0111 #define  CPC_Cx_CMD_CLOCKOFF            0x1
0112 #define  CPC_Cx_CMD_PWRDOWN         0x2
0113 #define  CPC_Cx_CMD_PWRUP           0x3
0114 #define  CPC_Cx_CMD_RESET           0x4
0115
0116 /* CPC_Cx_STAT_CONF - Indicates core configuration & state */
0117 CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
0118 #define CPC_Cx_STAT_CONF_PWRUPE         BIT(23)
0119 #define CPC_Cx_STAT_CONF_SEQSTATE       GENMASK(22, 19)
0120 #define  CPC_Cx_STAT_CONF_SEQSTATE_D0       0x0
0121 #define  CPC_Cx_STAT_CONF_SEQSTATE_U0       0x1
0122 #define  CPC_Cx_STAT_CONF_SEQSTATE_U1       0x2
0123 #define  CPC_Cx_STAT_CONF_SEQSTATE_U2       0x3
0124 #define  CPC_Cx_STAT_CONF_SEQSTATE_U3       0x4
0125 #define  CPC_Cx_STAT_CONF_SEQSTATE_U4       0x5
0126 #define  CPC_Cx_STAT_CONF_SEQSTATE_U5       0x6
0127 #define  CPC_Cx_STAT_CONF_SEQSTATE_U6       0x7
0128 #define  CPC_Cx_STAT_CONF_SEQSTATE_D1       0x8
0129 #define  CPC_Cx_STAT_CONF_SEQSTATE_D3       0x9
0130 #define  CPC_Cx_STAT_CONF_SEQSTATE_D2       0xa
0131 #define CPC_Cx_STAT_CONF_CLKGAT_IMPL        BIT(17)
0132 #define CPC_Cx_STAT_CONF_PWRDN_IMPL     BIT(16)
0133 #define CPC_Cx_STAT_CONF_EJTAG_PROBE        BIT(15)
0134
0135 /* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
0136 CPC_CX_ACCESSOR_RW(32, 0x010, other)
0137 #define CPC_Cx_OTHER_CORENUM            GENMASK(23, 16)
0138
0139 /* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
0140 CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
0141
0142 /* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
0143 CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
0144
0145 /* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
0146 CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
0147
0148 /* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
0149 CPC_CX_ACCESSOR_RW(32, 0x090, config)
0150
0151 #ifdef CONFIG_MIPS_CPC
0152
0153 /**
0154  * mips_cpc_lock_other - lock access to another core
0155  * core: the other core to be accessed
0156  *
0157  * Call before operating upon a core via the 'other' register region in
0158  * order to prevent the region being moved during access. Must be called
0159  * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
0160  * by a call to mips_cpc_unlock_other.
0161  */
0162 extern void mips_cpc_lock_other(unsigned int core);
0163
0164 /**
0165  * mips_cpc_unlock_other - unlock access to another core
0166  *
0167  * Call after operating upon another core via the 'other' register region.
0168  * Must be called after mips_cpc_lock_other.
0169  */
0170 extern void mips_cpc_unlock_other(void);
0171
0172 #else /* !CONFIG_MIPS_CPC */
0173
0174 static inline void mips_cpc_lock_other(unsigned int core) { }
0175 static inline void mips_cpc_unlock_other(void) { }
0176
0177 #endif /* !CONFIG_MIPS_CPC */
0178
0179 #endif /* __MIPS_ASM_MIPS_CPC_H__ */