include/asm/mips-cm.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2013 Imagination Technologies
0004  * Author: Paul Burton <paul.burton@mips.com>
0005  */
0006
0007 #ifndef __MIPS_ASM_MIPS_CPS_H__
0008 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
0009 #endif
0010
0011 #ifndef __MIPS_ASM_MIPS_CM_H__
0012 #define __MIPS_ASM_MIPS_CM_H__
0013
0014 #include <linux/bitfield.h>
0015 #include <linux/bitops.h>
0016 #include <linux/errno.h>
0017
0018 /* The base address of the CM GCR block */
0019 extern void __iomem *mips_gcr_base;
0020
0021 /* The base address of the CM L2-only sync region */
0022 extern void __iomem *mips_cm_l2sync_base;
0023
0024 /**
0025  * __mips_cm_phys_base - retrieve the physical base address of the CM
0026  *
0027  * This function returns the physical base address of the Coherence Manager
0028  * global control block, or 0 if no Coherence Manager is present. It provides
0029  * a default implementation which reads the CMGCRBase register where available,
0030  * and may be overridden by platforms which determine this address in a
0031  * different way by defining a function with the same prototype except for the
0032  * name mips_cm_phys_base (without underscores).
0033  */
0034 extern phys_addr_t __mips_cm_phys_base(void);
0035
0036 /*
0037  * mips_cm_is64 - determine CM register width
0038  *
0039  * The CM register width is determined by the version of the CM, with CM3
0040  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
0041  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
0042  * or vice-versa. This variable indicates the width of the memory accesses
0043  * that the kernel will perform to GCRs, which may differ from the actual
0044  * width of the GCRs.
0045  *
0046  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
0047  */
0048 extern int mips_cm_is64;
0049
0050 /**
0051  * mips_cm_error_report - Report CM cache errors
0052  */
0053 #ifdef CONFIG_MIPS_CM
0054 extern void mips_cm_error_report(void);
0055 #else
0056 static inline void mips_cm_error_report(void) {}
0057 #endif
0058
0059 /**
0060  * mips_cm_probe - probe for a Coherence Manager
0061  *
0062  * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
0063  * is successfully detected, else -errno.
0064  */
0065 #ifdef CONFIG_MIPS_CM
0066 extern int mips_cm_probe(void);
0067 #else
0068 static inline int mips_cm_probe(void)
0069 {
0070     return -ENODEV;
0071 }
0072 #endif
0073
0074 /**
0075  * mips_cm_present - determine whether a Coherence Manager is present
0076  *
0077  * Returns true if a CM is present in the system, else false.
0078  */
0079 static inline bool mips_cm_present(void)
0080 {
0081 #ifdef CONFIG_MIPS_CM
0082     return mips_gcr_base != NULL;
0083 #else
0084     return false;
0085 #endif
0086 }
0087
0088 /**
0089  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
0090  *
0091  * Returns true if the system implements an L2-only sync region, else false.
0092  */
0093 static inline bool mips_cm_has_l2sync(void)
0094 {
0095 #ifdef CONFIG_MIPS_CM
0096     return mips_cm_l2sync_base != NULL;
0097 #else
0098     return false;
0099 #endif
0100 }
0101
0102 /* Offsets to register blocks from the CM base address */
0103 #define MIPS_CM_GCB_OFS     0x0000 /* Global Control Block */
0104 #define MIPS_CM_CLCB_OFS    0x2000 /* Core Local Control Block */
0105 #define MIPS_CM_COCB_OFS    0x4000 /* Core Other Control Block */
0106 #define MIPS_CM_GDB_OFS     0x6000 /* Global Debug Block */
0107
0108 /* Total size of the CM memory mapped registers */
0109 #define MIPS_CM_GCR_SIZE    0x8000
0110
0111 /* Size of the L2-only sync region */
0112 #define MIPS_CM_L2SYNC_SIZE 0x1000
0113
0114 #define GCR_ACCESSOR_RO(sz, off, name)                  \
0115     CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)       \
0116     CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
0117
0118 #define GCR_ACCESSOR_RW(sz, off, name)                  \
0119     CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)       \
0120     CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
0121
0122 #define GCR_CX_ACCESSOR_RO(sz, off, name)               \
0123     CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
0124     CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
0125
0126 #define GCR_CX_ACCESSOR_RW(sz, off, name)               \
0127     CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
0128     CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
0129
0130 /* GCR_CONFIG - Information about the system */
0131 GCR_ACCESSOR_RO(64, 0x000, config)
0132 #define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE   BIT_ULL(43)
0133 #define CM_GCR_CONFIG_CLUSTER_ID        GENMASK_ULL(39, 32)
0134 #define CM_GCR_CONFIG_NUM_CLUSTERS      GENMASK(29, 23)
0135 #define CM_GCR_CONFIG_NUMIOCU           GENMASK(15, 8)
0136 #define CM_GCR_CONFIG_PCORES            GENMASK(7, 0)
0137
0138 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
0139 GCR_ACCESSOR_RW(64, 0x008, base)
0140 #define CM_GCR_BASE_GCRBASE         GENMASK_ULL(47, 15)
0141 #define CM_GCR_BASE_CMDEFTGT            GENMASK(1, 0)
0142 #define  CM_GCR_BASE_CMDEFTGT_MEM       0
0143 #define  CM_GCR_BASE_CMDEFTGT_RESERVED      1
0144 #define  CM_GCR_BASE_CMDEFTGT_IOCU0     2
0145 #define  CM_GCR_BASE_CMDEFTGT_IOCU1     3
0146
0147 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
0148 GCR_ACCESSOR_RW(32, 0x020, access)
0149 #define CM_GCR_ACCESS_ACCESSEN          GENMASK(7, 0)
0150
0151 /* GCR_REV - Indicates the Coherence Manager revision */
0152 GCR_ACCESSOR_RO(32, 0x030, rev)
0153 #define CM_GCR_REV_MAJOR            GENMASK(15, 8)
0154 #define CM_GCR_REV_MINOR            GENMASK(7, 0)
0155
0156 #define CM_ENCODE_REV(major, minor) \
0157         (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
0158          FIELD_PREP(CM_GCR_REV_MINOR, minor))
0159
0160 #define CM_REV_CM2              CM_ENCODE_REV(6, 0)
0161 #define CM_REV_CM2_5                CM_ENCODE_REV(7, 0)
0162 #define CM_REV_CM3              CM_ENCODE_REV(8, 0)
0163 #define CM_REV_CM3_5                CM_ENCODE_REV(9, 0)
0164
0165 /* GCR_ERR_CONTROL - Control error checking logic */
0166 GCR_ACCESSOR_RW(32, 0x038, err_control)
0167 #define CM_GCR_ERR_CONTROL_L2_ECC_EN        BIT(1)
0168 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT   BIT(0)
0169
0170 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
0171 GCR_ACCESSOR_RW(64, 0x040, error_mask)
0172
0173 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
0174 GCR_ACCESSOR_RW(64, 0x048, error_cause)
0175 #define CM_GCR_ERROR_CAUSE_ERRTYPE      GENMASK(31, 27)
0176 #define CM3_GCR_ERROR_CAUSE_ERRTYPE     GENMASK_ULL(63, 58)
0177 #define CM_GCR_ERROR_CAUSE_ERRINFO      GENMASK(26, 0)
0178
0179 /* GCR_ERR_ADDR - Indicates the address associated with an error */
0180 GCR_ACCESSOR_RW(64, 0x050, error_addr)
0181
0182 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
0183 GCR_ACCESSOR_RW(64, 0x058, error_mult)
0184 #define CM_GCR_ERROR_MULT_ERR2ND        GENMASK(4, 0)
0185
0186 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
0187 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
0188 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE   GENMASK(31, 12)
0189 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN     BIT(0)
0190
0191 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
0192 GCR_ACCESSOR_RW(64, 0x080, gic_base)
0193 #define CM_GCR_GIC_BASE_GICBASE         GENMASK(31, 17)
0194 #define CM_GCR_GIC_BASE_GICEN           BIT(0)
0195
0196 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
0197 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
0198 #define CM_GCR_CPC_BASE_CPCBASE         GENMASK(31, 15)
0199 #define CM_GCR_CPC_BASE_CPCEN           BIT(0)
0200
0201 /* GCR_REGn_BASE - Base addresses of CM address regions */
0202 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
0203 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
0204 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
0205 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
0206 #define CM_GCR_REGn_BASE_BASEADDR       GENMASK(31, 16)
0207
0208 /* GCR_REGn_MASK - Size & destination of CM address regions */
0209 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
0210 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
0211 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
0212 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
0213 #define CM_GCR_REGn_MASK_ADDRMASK       GENMASK(31, 16)
0214 #define CM_GCR_REGn_MASK_CCAOVR         GENMASK(7, 5)
0215 #define CM_GCR_REGn_MASK_CCAOVREN       BIT(4)
0216 #define CM_GCR_REGn_MASK_DROPL2         BIT(2)
0217 #define CM_GCR_REGn_MASK_CMTGT          GENMASK(1, 0)
0218 #define  CM_GCR_REGn_MASK_CMTGT_DISABLED    0x0
0219 #define  CM_GCR_REGn_MASK_CMTGT_MEM     0x1
0220 #define  CM_GCR_REGn_MASK_CMTGT_IOCU0       0x2
0221 #define  CM_GCR_REGn_MASK_CMTGT_IOCU1       0x3
0222
0223 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
0224 GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
0225 #define CM_GCR_GIC_STATUS_EX            BIT(0)
0226
0227 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
0228 GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
0229 #define CM_GCR_CPC_STATUS_EX            BIT(0)
0230
0231 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
0232 GCR_ACCESSOR_RW(32, 0x130, l2_config)
0233 #define CM_GCR_L2_CONFIG_BYPASS         BIT(20)
0234 #define CM_GCR_L2_CONFIG_SET_SIZE       GENMASK(15, 12)
0235 #define CM_GCR_L2_CONFIG_LINE_SIZE      GENMASK(11, 8)
0236 #define CM_GCR_L2_CONFIG_ASSOC          GENMASK(7, 0)
0237
0238 /* GCR_SYS_CONFIG2 - Further information about the system */
0239 GCR_ACCESSOR_RO(32, 0x150, sys_config2)
0240 #define CM_GCR_SYS_CONFIG2_MAXVPW       GENMASK(3, 0)
0241
0242 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
0243 GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
0244 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK      GENMASK(31, 12)
0245 #define CM_GCR_L2_PFT_CONTROL_PFTEN     BIT(8)
0246 #define CM_GCR_L2_PFT_CONTROL_NPFT      GENMASK(7, 0)
0247
0248 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
0249 GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
0250 #define CM_GCR_L2_PFT_CONTROL_B_CEN     BIT(8)
0251 #define CM_GCR_L2_PFT_CONTROL_B_PORTID      GENMASK(7, 0)
0252
0253 /* GCR_L2SM_COP - L2 cache op state machine control */
0254 GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
0255 #define CM_GCR_L2SM_COP_PRESENT         BIT(31)
0256 #define CM_GCR_L2SM_COP_RESULT          GENMASK(8, 6)
0257 #define  CM_GCR_L2SM_COP_RESULT_DONTCARE    0
0258 #define  CM_GCR_L2SM_COP_RESULT_DONE_OK     1
0259 #define  CM_GCR_L2SM_COP_RESULT_DONE_ERROR  2
0260 #define  CM_GCR_L2SM_COP_RESULT_ABORT_OK    3
0261 #define  CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
0262 #define CM_GCR_L2SM_COP_RUNNING         BIT(5)
0263 #define CM_GCR_L2SM_COP_TYPE            GENMASK(4, 2)
0264 #define  CM_GCR_L2SM_COP_TYPE_IDX_WBINV     0
0265 #define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAG  1
0266 #define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA  2
0267 #define  CM_GCR_L2SM_COP_TYPE_HIT_INV       4
0268 #define  CM_GCR_L2SM_COP_TYPE_HIT_WBINV     5
0269 #define  CM_GCR_L2SM_COP_TYPE_HIT_WB        6
0270 #define  CM_GCR_L2SM_COP_TYPE_FETCHLOCK     7
0271 #define CM_GCR_L2SM_COP_CMD         GENMASK(1, 0)
0272 #define  CM_GCR_L2SM_COP_CMD_START      1   /* only when idle */
0273 #define  CM_GCR_L2SM_COP_CMD_ABORT      3   /* only when running */
0274
0275 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
0276 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
0277 #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES  GENMASK_ULL(63, 48)
0278 #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG  GENMASK_ULL(47, 6)
0279
0280 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
0281 GCR_ACCESSOR_RW(64, 0x680, bev_base)
0282
0283 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
0284 GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
0285
0286 /* GCR_Cx_COHERENCE - Controls core coherence */
0287 GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
0288 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN     GENMASK(7, 0)
0289 #define CM3_GCR_Cx_COHERENCE_COHEN      BIT(0)
0290
0291 /* GCR_Cx_CONFIG - Information about a core's configuration */
0292 GCR_CX_ACCESSOR_RO(32, 0x010, config)
0293 #define CM_GCR_Cx_CONFIG_IOCUTYPE       GENMASK(11, 10)
0294 #define CM_GCR_Cx_CONFIG_PVPE           GENMASK(9, 0)
0295
0296 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
0297 GCR_CX_ACCESSOR_RW(32, 0x018, other)
0298 #define CM_GCR_Cx_OTHER_CORENUM         GENMASK(31, 16) /* CM < 3 */
0299 #define CM_GCR_Cx_OTHER_CLUSTER_EN      BIT(31)     /* CM >= 3.5 */
0300 #define CM_GCR_Cx_OTHER_GIC_EN          BIT(30)     /* CM >= 3.5 */
0301 #define CM_GCR_Cx_OTHER_BLOCK           GENMASK(25, 24) /* CM >= 3.5 */
0302 #define  CM_GCR_Cx_OTHER_BLOCK_LOCAL        0
0303 #define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL       1
0304 #define  CM_GCR_Cx_OTHER_BLOCK_USER     2
0305 #define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH  3
0306 #define CM_GCR_Cx_OTHER_CLUSTER         GENMASK(21, 16) /* CM >= 3.5 */
0307 #define CM3_GCR_Cx_OTHER_CORE           GENMASK(13, 8)  /* CM >= 3 */
0308 #define  CM_GCR_Cx_OTHER_CORE_CM        32
0309 #define CM3_GCR_Cx_OTHER_VP         GENMASK(2, 0)   /* CM >= 3 */
0310
0311 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
0312 GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
0313 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE     GENMASK(31, 12)
0314
0315 /* GCR_Cx_ID - Identify the current core */
0316 GCR_CX_ACCESSOR_RO(32, 0x028, id)
0317 #define CM_GCR_Cx_ID_CLUSTER            GENMASK(15, 8)
0318 #define CM_GCR_Cx_ID_CORE           GENMASK(7, 0)
0319
0320 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
0321 GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
0322 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET   BIT(31)
0323 #define CM_GCR_Cx_RESET_EXT_BASE_UEB        BIT(30)
0324 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
0325 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA   GENMASK(7, 1)
0326 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT    BIT(0)
0327
0328 /**
0329  * mips_cm_l2sync - perform an L2-only sync operation
0330  *
0331  * If an L2-only sync region is present in the system then this function
0332  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
0333  */
0334 static inline int mips_cm_l2sync(void)
0335 {
0336     if (!mips_cm_has_l2sync())
0337         return -ENODEV;
0338
0339     writel(0, mips_cm_l2sync_base);
0340     return 0;
0341 }
0342
0343 /**
0344  * mips_cm_revision() - return CM revision
0345  *
0346  * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
0347  * return value should be checked against the CM_REV_* macros.
0348  */
0349 static inline int mips_cm_revision(void)
0350 {
0351     if (!mips_cm_present())
0352         return 0;
0353
0354     return read_gcr_rev();
0355 }
0356
0357 /**
0358  * mips_cm_max_vp_width() - return the width in bits of VP indices
0359  *
0360  * Return: the width, in bits, of VP indices in fields that combine core & VP
0361  * indices.
0362  */
0363 static inline unsigned int mips_cm_max_vp_width(void)
0364 {
0365     extern int smp_num_siblings;
0366
0367     if (mips_cm_revision() >= CM_REV_CM3)
0368         return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
0369                  read_gcr_sys_config2());
0370
0371     if (mips_cm_present()) {
0372         /*
0373          * We presume that all cores in the system will have the same
0374          * number of VP(E)s, and if that ever changes then this will
0375          * need revisiting.
0376          */
0377         return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
0378     }
0379
0380     if (IS_ENABLED(CONFIG_SMP))
0381         return smp_num_siblings;
0382
0383     return 1;
0384 }
0385
0386 /**
0387  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
0388  * @cpu: the CPU whose VP ID to calculate
0389  *
0390  * Hardware such as the GIC uses identifiers for VPs which may not match the
0391  * CPU numbers used by Linux. This function calculates the hardware VP
0392  * identifier corresponding to a given CPU.
0393  *
0394  * Return: the VP ID for the CPU.
0395  */
0396 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
0397 {
0398     unsigned int core = cpu_core(&cpu_data[cpu]);
0399     unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
0400
0401     return (core * mips_cm_max_vp_width()) + vp;
0402 }
0403
0404 #ifdef CONFIG_MIPS_CM
0405
0406 /**
0407  * mips_cm_lock_other - lock access to redirect/other region
0408  * @cluster: the other cluster to be accessed
0409  * @core: the other core to be accessed
0410  * @vp: the VP within the other core to be accessed
0411  * @block: the register block to be accessed
0412  *
0413  * Configure the redirect/other region for the local core/VP (depending upon
0414  * the CM revision) to target the specified @cluster, @core, @vp & register
0415  * @block. Must be called before using the redirect/other region, and followed
0416  * by a call to mips_cm_unlock_other() when access to the redirect/other region
0417  * is complete.
0418  *
0419  * This function acquires a spinlock such that code between it &
0420  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
0421  * reconfigure the redirect/other region, and cannot be interfered with by
0422  * another VP in the core. As such calls to this function should not be nested.
0423  */
0424 extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
0425                    unsigned int vp, unsigned int block);
0426
0427 /**
0428  * mips_cm_unlock_other - unlock access to redirect/other region
0429  *
0430  * Must be called after mips_cm_lock_other() once all required access to the
0431  * redirect/other region has been completed.
0432  */
0433 extern void mips_cm_unlock_other(void);
0434
0435 #else /* !CONFIG_MIPS_CM */
0436
0437 static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
0438                       unsigned int vp, unsigned int block) { }
0439 static inline void mips_cm_unlock_other(void) { }
0440
0441 #endif /* !CONFIG_MIPS_CM */
0442
0443 /**
0444  * mips_cm_lock_other_cpu - lock access to redirect/other region
0445  * @cpu: the other CPU whose register we want to access
0446  *
0447  * Configure the redirect/other region for the local core/VP (depending upon
0448  * the CM revision) to target the specified @cpu & register @block. This is
0449  * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
0450  * for convenience.
0451  */
0452 static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
0453 {
0454     struct cpuinfo_mips *d = &cpu_data[cpu];
0455
0456     mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
0457 }
0458
0459 #endif /* __MIPS_ASM_MIPS_CM_H__ */