asm/mips-boards/sead3-addr.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2015 Imagination Technologies, Inc.
0007  *   written by Ralf Baechle <ralf@linux-mips.org>
0008  */
0009 #ifndef __ASM_MIPS_BOARDS_SEAD3_ADDR_H
0010 #define __ASM_MIPS_BOARDS_SEAD3_ADDR_H
0011
0012 /*
0013  * Target #0 Register Decode
0014  */
0015 #define SEAD3_SD_SPDCNF             0xbb000040
0016 #define SEAD3_SD_SPADDR             0xbb000048
0017 #define SEAD3_SD_DATA               0xbb000050
0018
0019 /*
0020  * Target #1 Register Decode
0021  */
0022 #define SEAD3_CFG               0xbb100110
0023 #define SEAD3_GIC_BASE_ADDRESS          0xbb1c0000
0024 #define SEAD3_SHARED_SECTION            0xbb1c0000
0025 #define SEAD3_VPE_LOCAL_SECTION         0xbb1c8000
0026 #define SEAD3_VPE_OTHER_SECTION         0xbb1cc000
0027 #define SEAD3_USER_MODE_VISIBLE_SECTION     0xbb1d0000
0028
0029 /*
0030  * Target #3 Register Decode
0031  */
0032 #define SEAD3_USB_HS_BASE           0xbb200000
0033 #define SEAD3_USB_HS_IDENTIFICATION_REGS    0xbb200000
0034 #define SEAD3_USB_HS_CAPABILITY_REGS        0xbb200100
0035 #define SEAD3_USB_HS_OPERATIONAL_REGS       0xbb200140
0036 #define SEAD3_RESERVED              0xbe800000
0037
0038 /*
0039  * Target #3 Register Decode
0040  */
0041 #define SEAD3_SRAM              0xbe000000
0042 #define SEAD3_OPTIONAL_SRAM         0xbe400000
0043 #define SEAD3_FPGA              0xbf000000
0044
0045 #define SEAD3_PI_PIC32_USB_STATUS       0xbf000060
0046 #define   SEAD3_PI_PIC32_USB_STATUS_IO_RDY  (1 << 0)
0047 #define   SEAD3_PI_PIC32_USB_STATUS_SPL_INT (1 << 1)
0048 #define   SEAD3_PI_PIC32_USB_STATUS_GPIOA_INT   (1 << 2)
0049 #define   SEAD3_PI_PIC32_USB_STATUS_GPIOB_INT   (1 << 3)
0050
0051 #define SEAD3_PI_SOFT_ENDIAN            0xbf000070
0052
0053 #define SEAD3_CPLD_P_SWITCH         0xbf000200
0054 #define SEAD3_CPLD_F_SWITCH         0xbf000208
0055 #define SEAD3_CPLD_P_LED            0xbf000210
0056 #define SEAD3_CPLD_F_LED            0xbf000218
0057 #define SEAD3_NEWSC_LIVE            0xbf000220
0058 #define SEAD3_NEWSC_REG             0xbf000228
0059 #define SEAD3_NEWSC_CTRL            0xbf000230
0060
0061 #define SEAD3_LCD_CONTROL           0xbf000400
0062 #define SEAD3_LCD_DATA              0xbf000408
0063 #define SEAD3_CPLD_LCD_STATUS           0xbf000410
0064 #define SEAD3_CPLD_LCD_DATA         0xbf000418
0065
0066 #define SEAD3_CPLD_PI_DEVRST            0xbf000480
0067 #define SEAD3_CPLD_PI_DEVRST_IC32_RST       (1 << 0)
0068 #define SEAD3_RESERVED_0            0xbf000500
0069
0070 #define SEAD3_PIC32_REGISTERS           0xbf000600
0071 #define SEAD3_RESERVED_1            0xbf000700
0072 #define SEAD3_UART_CH_0             0xbf000800
0073 #define SEAD3_UART_CH_1             0xbf000900
0074 #define SEAD3_RESERVED_2            0xbf000a00
0075 #define SEAD3_ETHERNET              0xbf010000
0076 #define SEAD3_RESERVED_3            0xbf020000
0077 #define SEAD3_USER_EXPANSION            0xbf400000
0078 #define SEAD3_RESERVED_4            0xbf800000
0079 #define SEAD3_BOOT_FLASH_EXTENSION      0xbfa00000
0080 #define SEAD3_BOOT_FLASH            0xbfc00000
0081 #define SEAD3_REVISION_REGISTER         0xbfc00010
0082
0083 #endif /* __ASM_MIPS_BOARDS_SEAD3_ADDR_H  */