asm/mips-boards/maltaint.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
0007  *  Carsten Langgaard <carstenl@mips.com>
0008  *  Steven J. Hill <sjhill@mips.com>
0009  */
0010 #ifndef _MIPS_MALTAINT_H
0011 #define _MIPS_MALTAINT_H
0012
0013 /*
0014  * Interrupts 0..15 are used for Malta ISA compatible interrupts
0015  */
0016 #define MALTA_INT_BASE      0
0017
0018 /* CPU interrupt offsets */
0019 #define MIPSCPU_INT_SW0     0
0020 #define MIPSCPU_INT_SW1     1
0021 #define MIPSCPU_INT_MB0     2
0022 #define MIPSCPU_INT_I8259A  MIPSCPU_INT_MB0
0023 #define MIPSCPU_INT_GIC     MIPSCPU_INT_MB0 /* GIC chained interrupt */
0024 #define MIPSCPU_INT_MB1     3
0025 #define MIPSCPU_INT_SMI     MIPSCPU_INT_MB1
0026 #define MIPSCPU_INT_MB2     4
0027 #define MIPSCPU_INT_MB3     5
0028 #define MIPSCPU_INT_COREHI  MIPSCPU_INT_MB3
0029 #define MIPSCPU_INT_MB4     6
0030 #define MIPSCPU_INT_CORELO  MIPSCPU_INT_MB4
0031
0032 /*
0033  * Interrupts 96..127 are used for Soc-it Classic interrupts
0034  */
0035 #define MSC01C_INT_BASE     96
0036
0037 /* SOC-it Classic interrupt offsets */
0038 #define MSC01C_INT_TMR      0
0039 #define MSC01C_INT_PCI      1
0040
0041 /*
0042  * Interrupts 96..127 are used for Soc-it EIC interrupts
0043  */
0044 #define MSC01E_INT_BASE     96
0045
0046 /* SOC-it EIC interrupt offsets */
0047 #define MSC01E_INT_SW0      1
0048 #define MSC01E_INT_SW1      2
0049 #define MSC01E_INT_MB0      3
0050 #define MSC01E_INT_I8259A   MSC01E_INT_MB0
0051 #define MSC01E_INT_MB1      4
0052 #define MSC01E_INT_SMI      MSC01E_INT_MB1
0053 #define MSC01E_INT_MB2      5
0054 #define MSC01E_INT_MB3      6
0055 #define MSC01E_INT_COREHI   MSC01E_INT_MB3
0056 #define MSC01E_INT_MB4      7
0057 #define MSC01E_INT_CORELO   MSC01E_INT_MB4
0058 #define MSC01E_INT_TMR      8
0059 #define MSC01E_INT_PCI      9
0060 #define MSC01E_INT_PERFCTR  10
0061 #define MSC01E_INT_CPUCTR   11
0062
0063 #endif /* !(_MIPS_MALTAINT_H) */