asm/mips-boards/malta.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Carsten Langgaard, carstenl@mips.com
0004  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
0005  *
0006  * Defines of the Malta board specific address-MAP, registers, etc.
0007  */
0008 #ifndef __ASM_MIPS_BOARDS_MALTA_H
0009 #define __ASM_MIPS_BOARDS_MALTA_H
0010
0011 #include <asm/addrspace.h>
0012 #include <asm/io.h>
0013 #include <asm/mips-boards/msc01_pci.h>
0014 #include <asm/gt64120.h>
0015
0016 /* Mips interrupt controller found in SOCit variations */
0017 #define MIPS_MSC01_IC_REG_BASE      0x1bc40000
0018 #define MIPS_SOCITSC_IC_REG_BASE    0x1ffa0000
0019
0020 /*
0021  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
0022  * Bonito system controllers.
0023  */
0024 #define MALTA_GT_PORT_BASE  get_gt_port_base(GT_PCI0IOLD_OFS)
0025 #define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
0026 #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
0027
0028 static inline unsigned long get_gt_port_base(unsigned long reg)
0029 {
0030     unsigned long addr;
0031     addr = GT_READ(reg);
0032     return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
0033 }
0034
0035 static inline unsigned long get_msc_port_base(unsigned long reg)
0036 {
0037     unsigned long addr;
0038     MSC_READ(reg, addr);
0039     return (unsigned long) ioremap(addr, 0x10000);
0040 }
0041
0042 /*
0043  * GCMP Specific definitions
0044  */
0045 #define GCMP_BASE_ADDR          0x1fbf8000
0046 #define GCMP_ADDRSPACE_SZ       (256 * 1024)
0047
0048 /*
0049  * GIC Specific definitions
0050  */
0051 #define GIC_BASE_ADDR           0x1bdc0000
0052 #define GIC_ADDRSPACE_SZ        (128 * 1024)
0053
0054 /*
0055  * CPC Specific definitions
0056  */
0057 #define CPC_BASE_ADDR           0x1bde0000
0058
0059 /*
0060  * MSC01 BIU Specific definitions
0061  * FIXME : These should be elsewhere ?
0062  */
0063 #define MSC01_BIU_REG_BASE      0x1bc80000
0064 #define MSC01_BIU_ADDRSPACE_SZ      (256 * 1024)
0065 #define MSC01_SC_CFG_OFS        0x0110
0066 #define MSC01_SC_CFG_GICPRES_MSK    0x00000004
0067 #define MSC01_SC_CFG_GICPRES_SHF    2
0068 #define MSC01_SC_CFG_GICENA_SHF     3
0069
0070 /*
0071  * Malta RTC-device indirect register access.
0072  */
0073 #define MALTA_RTC_ADR_REG   0x70
0074 #define MALTA_RTC_DAT_REG   0x71
0075
0076 /*
0077  * Malta SMSC FDC37M817 Super I/O Controller register.
0078  */
0079 #define SMSC_CONFIG_REG     0x3f0
0080 #define SMSC_DATA_REG       0x3f1
0081
0082 #define SMSC_CONFIG_DEVNUM  0x7
0083 #define SMSC_CONFIG_ACTIVATE    0x30
0084 #define SMSC_CONFIG_ENTER   0x55
0085 #define SMSC_CONFIG_EXIT    0xaa
0086
0087 #define SMSC_CONFIG_DEVNUM_FLOPPY     0
0088
0089 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
0090
0091 #define SMSC_WRITE(x, a)     outb(x, a)
0092
0093 #define MALTA_JMPRS_REG     0x1f000210
0094
0095 extern void __init *malta_dt_shim(void *fdt);
0096
0097 #endif /* __ASM_MIPS_BOARDS_MALTA_H */