asm/mips-boards/generic.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Defines of the MIPS boards specific address-MAP, registers, etc.
0007  *
0008  * Copyright (C) 2000,2012 MIPS Technologies, Inc.
0009  * All rights reserved.
0010  * Authors: Carsten Langgaard <carstenl@mips.com>
0011  *          Steven J. Hill <sjhill@mips.com>
0012  */
0013 #ifndef __ASM_MIPS_BOARDS_GENERIC_H
0014 #define __ASM_MIPS_BOARDS_GENERIC_H
0015
0016 #include <asm/addrspace.h>
0017 #include <asm/byteorder.h>
0018 #include <asm/mips-boards/bonito64.h>
0019
0020 /*
0021  * Display register base.
0022  */
0023 #define ASCII_DISPLAY_WORD_BASE    0x1f000410
0024 #define ASCII_DISPLAY_POS_BASE     0x1f000418
0025
0026 /*
0027  * Revision register.
0028  */
0029 #define MIPS_REVISION_REG          0x1fc00010
0030 #define MIPS_REVISION_CORID_QED_RM5261     0
0031 #define MIPS_REVISION_CORID_CORE_LV    1
0032 #define MIPS_REVISION_CORID_BONITO64       2
0033 #define MIPS_REVISION_CORID_CORE_20K       3
0034 #define MIPS_REVISION_CORID_CORE_FPGA      4
0035 #define MIPS_REVISION_CORID_CORE_MSC       5
0036 #define MIPS_REVISION_CORID_CORE_EMUL      6
0037 #define MIPS_REVISION_CORID_CORE_FPGA2     7
0038 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
0039 #define MIPS_REVISION_CORID_CORE_FPGA3     9
0040 #define MIPS_REVISION_CORID_CORE_24K       10
0041 #define MIPS_REVISION_CORID_CORE_FPGA4     11
0042 #define MIPS_REVISION_CORID_CORE_FPGA5     12
0043
0044 /**** Artificial corid defines ****/
0045 /*
0046  *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
0047  *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
0048  */
0049 #define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
0050 #define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
0051
0052 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
0053
0054 #define MIPS_REVISION_SCON_OTHER       0
0055 #define MIPS_REVISION_SCON_SOCITSC     1
0056 #define MIPS_REVISION_SCON_SOCITSCP    2
0057
0058 /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
0059 #define MIPS_REVISION_SCON_UNKNOWN     -1
0060 #define MIPS_REVISION_SCON_GT64120     -2
0061 #define MIPS_REVISION_SCON_BONITO      -3
0062 #define MIPS_REVISION_SCON_BRTL        -4
0063 #define MIPS_REVISION_SCON_SOCIT       -5
0064 #define MIPS_REVISION_SCON_ROCIT       -6
0065
0066 #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
0067
0068 extern int mips_revision_sconid;
0069
0070 #ifdef CONFIG_PCI
0071 extern void mips_pcibios_init(void);
0072 #else
0073 #define mips_pcibios_init() do { } while (0)
0074 #endif
0075
0076 extern void mips_scroll_message(void);
0077 extern void mips_display_message(const char *str);
0078
0079 #endif  /* __ASM_MIPS_BOARDS_GENERIC_H */