asm/mach-rc32434/irq.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_RC32434_IRQ_H
0003 #define __ASM_RC32434_IRQ_H
0004
0005 #define NR_IRQS 256
0006
0007 #include <asm/mach-generic/irq.h>
0008 #include <asm/mach-rc32434/rb.h>
0009
0010 /* Interrupt Controller */
0011 #define IC_GROUP0_PEND      (REGBASE + 0x38000)
0012 #define IC_GROUP0_MASK      (REGBASE + 0x38008)
0013 #define IC_GROUP_OFFSET     0x0C
0014
0015 #define NUM_INTR_GROUPS     5
0016
0017 /* 16550 UARTs */
0018 #define GROUP0_IRQ_BASE     8   /* GRP2 IRQ numbers start here */
0019                     /* GRP3 IRQ numbers start here */
0020 #define GROUP1_IRQ_BASE     (GROUP0_IRQ_BASE + 32)
0021                     /* GRP4 IRQ numbers start here */
0022 #define GROUP2_IRQ_BASE     (GROUP1_IRQ_BASE + 32)
0023                     /* GRP5 IRQ numbers start here */
0024 #define GROUP3_IRQ_BASE     (GROUP2_IRQ_BASE + 32)
0025 #define GROUP4_IRQ_BASE     (GROUP3_IRQ_BASE + 32)
0026
0027 #define UART0_IRQ       (GROUP3_IRQ_BASE + 0)
0028
0029 #define ETH0_DMA_RX_IRQ     (GROUP1_IRQ_BASE + 0)
0030 #define ETH0_DMA_TX_IRQ     (GROUP1_IRQ_BASE + 1)
0031 #define ETH0_RX_OVR_IRQ     (GROUP3_IRQ_BASE + 9)
0032 #define ETH0_TX_UND_IRQ     (GROUP3_IRQ_BASE + 10)
0033
0034 #define GPIO_MAPPED_IRQ_BASE    GROUP4_IRQ_BASE
0035 #define GPIO_MAPPED_IRQ_GROUP   4
0036
0037 #endif  /* __ASM_RC32434_IRQ_H */