asm/mach-rc32434/integ.h

0001 /*
0002  *  Definitions for the Watchdog registers
0003  *
0004  *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
0005  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
0006  *
0007  *  This program is free software; you can redistribute  it and/or modify it
0008  *  under  the terms of  the GNU General  Public License as published by the
0009  *  Free Software Foundation;  either version 2 of the  License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0013  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the  GNU General Public License along
0024  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  *
0027  */
0028
0029 #ifndef __RC32434_INTEG_H__
0030 #define __RC32434_INTEG_H__
0031
0032 #include <asm/mach-rc32434/rb.h>
0033
0034 #define INTEG0_BASE_ADDR    0x18030030
0035
0036 struct integ {
0037     u32 errcs;          /* sticky use ERRCS_ */
0038     u32 wtcount;            /* Watchdog timer count reg. */
0039     u32 wtcompare;          /* Watchdog timer timeout value. */
0040     u32 wtc;            /* Watchdog timer control. use WTC_ */
0041 };
0042
0043 /* Error counters */
0044 #define RC32434_ERR_WTO     0
0045 #define RC32434_ERR_WNE     1
0046 #define RC32434_ERR_UCW     2
0047 #define RC32434_ERR_UCR     3
0048 #define RC32434_ERR_UPW     4
0049 #define RC32434_ERR_UPR     5
0050 #define RC32434_ERR_UDW     6
0051 #define RC32434_ERR_UDR     7
0052 #define RC32434_ERR_SAE     8
0053 #define RC32434_ERR_WRE     9
0054
0055 /* Watchdog control bits */
0056 #define RC32434_WTC_EN      0
0057 #define RC32434_WTC_TO      1
0058
0059 #endif  /* __RC32434_INTEG_H__ */