asm/mach-rc32434/gpio.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2002 Integrated Device Technology, Inc.
0004  *  All rights reserved.
0005  *
0006  * GPIO register definition.
0007  *
0008  * Author : ryan.holmQVist@idt.com
0009  * Date   : 20011005
0010  * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
0011  * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
0012  */
0013
0014 #ifndef _RC32434_GPIO_H_
0015 #define _RC32434_GPIO_H_
0016
0017 struct rb532_gpio_reg {
0018     u32   gpiofunc;   /* GPIO Function Register
0019                * gpiofunc[x]==0 bit = gpio
0020                * func[x]==1  bit = altfunc
0021                */
0022     u32   gpiocfg;    /* GPIO Configuration Register
0023                * gpiocfg[x]==0 bit = input
0024                * gpiocfg[x]==1 bit = output
0025                */
0026     u32   gpiod;      /* GPIO Data Register
0027                * gpiod[x] read/write gpio pinX status
0028                */
0029     u32   gpioilevel; /* GPIO Interrupt Status Register
0030                * interrupt level (see gpioistat)
0031                */
0032     u32   gpioistat;  /* Gpio Interrupt Status Register
0033                * istat[x] = (gpiod[x] == level[x])
0034                * cleared in ISR (STICKY bits)
0035                */
0036     u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
0037 };
0038
0039 /* UART GPIO signals */
0040 #define RC32434_UART0_SOUT  (1 << 0)
0041 #define RC32434_UART0_SIN   (1 << 1)
0042 #define RC32434_UART0_RTS   (1 << 2)
0043 #define RC32434_UART0_CTS   (1 << 3)
0044
0045 /* M & P bus GPIO signals */
0046 #define RC32434_MP_BIT_22   (1 << 4)
0047 #define RC32434_MP_BIT_23   (1 << 5)
0048 #define RC32434_MP_BIT_24   (1 << 6)
0049 #define RC32434_MP_BIT_25   (1 << 7)
0050
0051 /* CPU GPIO signals */
0052 #define RC32434_CPU_GPIO    (1 << 8)
0053
0054 /* Reserved GPIO signals */
0055 #define RC32434_AF_SPARE_6  (1 << 9)
0056 #define RC32434_AF_SPARE_4  (1 << 10)
0057 #define RC32434_AF_SPARE_3  (1 << 11)
0058 #define RC32434_AF_SPARE_2  (1 << 12)
0059
0060 /* PCI messaging unit */
0061 #define RC32434_PCI_MSU_GPIO    (1 << 13)
0062
0063 /* NAND GPIO signals */
0064 #define GPIO_RDY        8
0065 #define GPIO_WPX    9
0066 #define GPIO_ALE        10
0067 #define GPIO_CLE        11
0068
0069 /* Compact Flash GPIO pin */
0070 #define CF_GPIO_NUM     13
0071
0072 /* S1 button GPIO (shared with UART0_SIN) */
0073 #define GPIO_BTN_S1     1
0074
0075 extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
0076 extern void rb532_gpio_set_istat(int bit, unsigned gpio);
0077 extern void rb532_gpio_set_func(unsigned gpio);
0078
0079 #endif /* _RC32434_GPIO_H_ */