asm/mach-rc32434/eth.h

0001 /*
0002  *  Definitions for the Ethernet registers
0003  *
0004  *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
0005  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
0006  *
0007  *  This program is free software; you can redistribute  it and/or modify it
0008  *  under  the terms of  the GNU General  Public License as published by the
0009  *  Free Software Foundation;  either version 2 of the  License, or (at your
0010  *  option) any later version.
0011  *
0012  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0013  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0014  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0015  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0016  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0017  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0018  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0019  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0020  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0021  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0022  *
0023  *  You should have received a copy of the  GNU General Public License along
0024  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0025  *  675 Mass Ave, Cambridge, MA 02139, USA.
0026  *
0027  */
0028
0029 #ifndef __ASM_RC32434_ETH_H
0030 #define __ASM_RC32434_ETH_H
0031
0032
0033 #define ETH0_BASE_ADDR      0x18060000
0034
0035 struct eth_regs {
0036     u32 ethintfc;
0037     u32 ethfifott;
0038     u32 etharc;
0039     u32 ethhash0;
0040     u32 ethhash1;
0041     u32 ethu0[4];       /* Reserved. */
0042     u32 ethpfs;
0043     u32 ethmcp;
0044     u32 eth_u1[10];     /* Reserved. */
0045     u32 ethspare;
0046     u32 eth_u2[42];     /* Reserved. */
0047     u32 ethsal0;
0048     u32 ethsah0;
0049     u32 ethsal1;
0050     u32 ethsah1;
0051     u32 ethsal2;
0052     u32 ethsah2;
0053     u32 ethsal3;
0054     u32 ethsah3;
0055     u32 ethrbc;
0056     u32 ethrpc;
0057     u32 ethrupc;
0058     u32 ethrfc;
0059     u32 ethtbc;
0060     u32 ethgpf;
0061     u32 eth_u9[50];     /* Reserved. */
0062     u32 ethmac1;
0063     u32 ethmac2;
0064     u32 ethipgt;
0065     u32 ethipgr;
0066     u32 ethclrt;
0067     u32 ethmaxf;
0068     u32 eth_u10;        /* Reserved. */
0069     u32 ethmtest;
0070     u32 miimcfg;
0071     u32 miimcmd;
0072     u32 miimaddr;
0073     u32 miimwtd;
0074     u32 miimrdd;
0075     u32 miimind;
0076     u32 eth_u11;        /* Reserved. */
0077     u32 eth_u12;        /* Reserved. */
0078     u32 ethcfsa0;
0079     u32 ethcfsa1;
0080     u32 ethcfsa2;
0081 };
0082
0083 /* Ethernet interrupt registers */
0084 #define ETH_INT_FC_EN       (1 << 0)
0085 #define ETH_INT_FC_ITS      (1 << 1)
0086 #define ETH_INT_FC_RIP      (1 << 2)
0087 #define ETH_INT_FC_JAM      (1 << 3)
0088 #define ETH_INT_FC_OVR      (1 << 4)
0089 #define ETH_INT_FC_UND      (1 << 5)
0090 #define ETH_INT_FC_IOC      0x000000c0
0091
0092 /* Ethernet FIFO registers */
0093 #define ETH_FIFI_TT_TTH_BIT 0
0094 #define ETH_FIFO_TT_TTH     0x0000007f
0095
0096 /* Ethernet ARC/multicast registers */
0097 #define ETH_ARC_PRO     (1 << 0)
0098 #define ETH_ARC_AM      (1 << 1)
0099 #define ETH_ARC_AFM     (1 << 2)
0100 #define ETH_ARC_AB      (1 << 3)
0101
0102 /* Ethernet SAL registers */
0103 #define ETH_SAL_BYTE_5      0x000000ff
0104 #define ETH_SAL_BYTE_4      0x0000ff00
0105 #define ETH_SAL_BYTE_3      0x00ff0000
0106 #define ETH_SAL_BYTE_2      0xff000000
0107
0108 /* Ethernet SAH registers */
0109 #define ETH_SAH_BYTE1       0x000000ff
0110 #define ETH_SAH_BYTE0       0x0000ff00
0111
0112 /* Ethernet GPF register */
0113 #define ETH_GPF_PTV     0x0000ffff
0114
0115 /* Ethernet PFG register */
0116 #define ETH_PFS_PFD     (1 << 0)
0117
0118 /* Ethernet CFSA[0-3] registers */
0119 #define ETH_CFSA0_CFSA4     0x000000ff
0120 #define ETH_CFSA0_CFSA5     0x0000ff00
0121 #define ETH_CFSA1_CFSA2     0x000000ff
0122 #define ETH_CFSA1_CFSA3     0x0000ff00
0123 #define ETH_CFSA1_CFSA0     0x000000ff
0124 #define ETH_CFSA1_CFSA1     0x0000ff00
0125
0126 /* Ethernet MAC1 registers */
0127 #define ETH_MAC1_RE     (1 << 0)
0128 #define ETH_MAC1_PAF        (1 << 1)
0129 #define ETH_MAC1_RFC        (1 << 2)
0130 #define ETH_MAC1_TFC        (1 << 3)
0131 #define ETH_MAC1_LB     (1 << 4)
0132 #define ETH_MAC1_MR     (1 << 31)
0133
0134 /* Ethernet MAC2 registers */
0135 #define ETH_MAC2_FD     (1 << 0)
0136 #define ETH_MAC2_FLC        (1 << 1)
0137 #define ETH_MAC2_HFE        (1 << 2)
0138 #define ETH_MAC2_DC     (1 << 3)
0139 #define ETH_MAC2_CEN        (1 << 4)
0140 #define ETH_MAC2_PE     (1 << 5)
0141 #define ETH_MAC2_VPE        (1 << 6)
0142 #define ETH_MAC2_APE        (1 << 7)
0143 #define ETH_MAC2_PPE        (1 << 8)
0144 #define ETH_MAC2_LPE        (1 << 9)
0145 #define ETH_MAC2_NB     (1 << 12)
0146 #define ETH_MAC2_BP     (1 << 13)
0147 #define ETH_MAC2_ED     (1 << 14)
0148
0149 /* Ethernet IPGT register */
0150 #define ETH_IPGT        0x0000007f
0151
0152 /* Ethernet IPGR registers */
0153 #define ETH_IPGR_IPGR2      0x0000007f
0154 #define ETH_IPGR_IPGR1      0x00007f00
0155
0156 /* Ethernet CLRT registers */
0157 #define ETH_CLRT_MAX_RET    0x0000000f
0158 #define ETH_CLRT_COL_WIN    0x00003f00
0159
0160 /* Ethernet MAXF register */
0161 #define ETH_MAXF        0x0000ffff
0162
0163 /* Ethernet test registers */
0164 #define ETH_TEST_REG        (1 << 2)
0165 #define ETH_MCP_DIV     0x000000ff
0166
0167 /* MII registers */
0168 #define ETH_MII_CFG_RSVD    0x0000000c
0169 #define ETH_MII_CMD_RD      (1 << 0)
0170 #define ETH_MII_CMD_SCN     (1 << 1)
0171 #define ETH_MII_REG_ADDR    0x0000001f
0172 #define ETH_MII_PHY_ADDR    0x00001f00
0173 #define ETH_MII_WTD_DATA    0x0000ffff
0174 #define ETH_MII_RDD_DATA    0x0000ffff
0175 #define ETH_MII_IND_BSY     (1 << 0)
0176 #define ETH_MII_IND_SCN     (1 << 1)
0177 #define ETH_MII_IND_NV      (1 << 2)
0178
0179 /*
0180  * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
0181  */
0182
0183 #define ETH_RX_FD       (1 << 0)
0184 #define ETH_RX_LD       (1 << 1)
0185 #define ETH_RX_ROK      (1 << 2)
0186 #define ETH_RX_FM       (1 << 3)
0187 #define ETH_RX_MP       (1 << 4)
0188 #define ETH_RX_BP       (1 << 5)
0189 #define ETH_RX_VLT      (1 << 6)
0190 #define ETH_RX_CF       (1 << 7)
0191 #define ETH_RX_OVR      (1 << 8)
0192 #define ETH_RX_CRC      (1 << 9)
0193 #define ETH_RX_CV       (1 << 10)
0194 #define ETH_RX_DB       (1 << 11)
0195 #define ETH_RX_LE       (1 << 12)
0196 #define ETH_RX_LOR      (1 << 13)
0197 #define ETH_RX_CES      (1 << 14)
0198 #define ETH_RX_LEN_BIT      16
0199 #define ETH_RX_LEN      0xffff0000
0200
0201 #define ETH_TX_FD       (1 << 0)
0202 #define ETH_TX_LD       (1 << 1)
0203 #define ETH_TX_OEN      (1 << 2)
0204 #define ETH_TX_PEN      (1 << 3)
0205 #define ETH_TX_CEN      (1 << 4)
0206 #define ETH_TX_HEN      (1 << 5)
0207 #define ETH_TX_TOK      (1 << 6)
0208 #define ETH_TX_MP       (1 << 7)
0209 #define ETH_TX_BP       (1 << 8)
0210 #define ETH_TX_UND      (1 << 9)
0211 #define ETH_TX_OF       (1 << 10)
0212 #define ETH_TX_ED       (1 << 11)
0213 #define ETH_TX_EC       (1 << 12)
0214 #define ETH_TX_LC       (1 << 13)
0215 #define ETH_TX_TD       (1 << 14)
0216 #define ETH_TX_CRC      (1 << 15)
0217 #define ETH_TX_LE       (1 << 16)
0218 #define ETH_TX_CC       0x001E0000
0219
0220 #endif  /* __ASM_RC32434_ETH_H */