asm/mach-rc32434/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2002 Integrated Device Technology, Inc.
0004  *      All rights reserved.
0005  *
0006  * DMA register definition.
0007  *
0008  * Author : ryan.holmQVist@idt.com
0009  * Date   : 20011005
0010  */
0011
0012 #ifndef __ASM_RC32434_DMA_H
0013 #define __ASM_RC32434_DMA_H
0014
0015 #include <asm/mach-rc32434/rb.h>
0016
0017 #define DMA0_BASE_ADDR          0x18040000
0018
0019 /*
0020  * DMA descriptor (in physical memory).
0021  */
0022
0023 struct dma_desc {
0024     u32 control;            /* Control. use DMAD_* */
0025     u32 ca;             /* Current Address. */
0026     u32 devcs;          /* Device control and status. */
0027     u32 link;           /* Next descriptor in chain. */
0028 };
0029
0030 #define DMA_DESC_SIZ            sizeof(struct dma_desc)
0031 #define DMA_DESC_COUNT_BIT      0
0032 #define DMA_DESC_COUNT_MSK      0x0003ffff
0033 #define DMA_DESC_DS_BIT         20
0034 #define DMA_DESC_DS_MSK         0x00300000
0035
0036 #define DMA_DESC_DEV_CMD_BIT        22
0037 #define DMA_DESC_DEV_CMD_MSK        0x01c00000
0038
0039 /* DMA command sizes */
0040 #define DMA_DESC_DEV_CMD_BYTE       0
0041 #define DMA_DESC_DEV_CMD_HLF_WD     1
0042 #define DMA_DESC_DEV_CMD_WORD       2
0043 #define DMA_DESC_DEV_CMD_2WORDS     3
0044 #define DMA_DESC_DEV_CMD_4WORDS     4
0045 #define DMA_DESC_DEV_CMD_6WORDS     5
0046 #define DMA_DESC_DEV_CMD_8WORDS     6
0047 #define DMA_DESC_DEV_CMD_16WORDS    7
0048
0049 /* DMA descriptors interrupts */
0050 #define DMA_DESC_COF            (1 << 25) /* Chain on finished */
0051 #define DMA_DESC_COD            (1 << 26) /* Chain on done */
0052 #define DMA_DESC_IOF            (1 << 27) /* Interrupt on finished */
0053 #define DMA_DESC_IOD            (1 << 28) /* Interrupt on done */
0054 #define DMA_DESC_TERM           (1 << 29) /* Terminated */
0055 #define DMA_DESC_DONE           (1 << 30) /* Done */
0056 #define DMA_DESC_FINI           (1 << 31) /* Finished */
0057
0058 /*
0059  * DMA register (within Internal Register Map).
0060  */
0061
0062 struct dma_reg {
0063     u32 dmac;       /* Control. */
0064     u32 dmas;       /* Status. */
0065     u32 dmasm;      /* Mask. */
0066     u32 dmadptr;        /* Descriptor pointer. */
0067     u32 dmandptr;       /* Next descriptor pointer. */
0068 };
0069
0070 /* DMA channels specific registers */
0071 #define DMA_CHAN_RUN_BIT        (1 << 0)
0072 #define DMA_CHAN_DONE_BIT       (1 << 1)
0073 #define DMA_CHAN_MODE_BIT       (1 << 2)
0074 #define DMA_CHAN_MODE_MSK       0x0000000c
0075 #define  DMA_CHAN_MODE_AUTO     0
0076 #define  DMA_CHAN_MODE_BURST        1
0077 #define  DMA_CHAN_MODE_XFRT     2
0078 #define  DMA_CHAN_MODE_RSVD     3
0079 #define DMA_CHAN_ACT_BIT        (1 << 4)
0080
0081 /* DMA status registers */
0082 #define DMA_STAT_FINI           (1 << 0)
0083 #define DMA_STAT_DONE           (1 << 1)
0084 #define DMA_STAT_CHAIN          (1 << 2)
0085 #define DMA_STAT_ERR            (1 << 3)
0086 #define DMA_STAT_HALT           (1 << 4)
0087
0088 /*
0089  * DMA channel definitions
0090  */
0091
0092 #define DMA_CHAN_ETH_RCV        0
0093 #define DMA_CHAN_ETH_XMT        1
0094 #define DMA_CHAN_MEM_TO_FIFO        2
0095 #define DMA_CHAN_FIFO_TO_MEM        3
0096 #define DMA_CHAN_PCI_TO_MEM     4
0097 #define DMA_CHAN_MEM_TO_PCI     5
0098 #define DMA_CHAN_COUNT          6
0099
0100 struct dma_channel {
0101     struct dma_reg ch[DMA_CHAN_COUNT];
0102 };
0103
0104 #endif  /* __ASM_RC32434_DMA_H */